Patent Application
20240420744
The technology presented herein relates to data processing systems, such as memory systems, and to sharing the status data among the components of the systems.
Data processing systems can comprise a number of processing nodes linked to a communication network. These systems can execute procedures arranged in server/client configurations, where a server procedure transmits commands from one node in the network to other nodes on the network at which the client procedures indicated by the commands are to be executed. In some cases, the server procedure gathers status information from the nodes in the network for management of the commands issued to the various client procedures.
For example, memory systems can comprise a memory controller device and a plurality of memory devices arranged in a bus topology. The memory controller device can include a bus master interface connected to a communication bus. A group of the memory devices can have respective bus slave interfaces connected to the communication bus. The memory devices maintain status information about one or more status units on the devices. In order for the memory controller to access this status information, it issues status read commands on the communication bus to each of the devices. In response to the read status command, the memory devices transmit status data back on the communication bus to the memory controller.
For example, a memory system known as a solid-state disk SSD can include a memory controller and many (e.g., 64) high density NAND flash memory devices. Each of the NAND flash memory devices can include one or more status units each having a different status, and capable of executing memory operations requested by the memory controller. A procedure that involves commands transmitted in sequence to each of the many NAND flash memory devices for status consumes substantial bus overhead, reducing the data throughput for the memory system.
Thus, procedures for gathering status information in memory systems, and in other data processing systems, can involve significant read status timing overhead, and as the number of nodes on the communication network increases, the overhead also increases.
It is desirable to provide technologies for improving the efficiency of data processing systems, including memory systems.
A technology is described that can significantly reduce communications overhead involved in retrieving status information from client nodes in a network, including bus topology networks.
One aspect of the technology is a system comprising a data bus, a source node device on the data bus and a group of bus node devices on the data bus. The source node device is configured to transmit a group read status command on the data bus. The bus node devices in the group are configured to respond to the group read status command in sequence, by transmitting status data on the data bus in respective, non-overlapping timing windows.
The technology can be applied in a variety of network configurations. According to one configuration described herein the data bus includes a set of bus signal lines. The group read status command is transmitted on specific lines in the set of bus signal lines, and the status data is transmitted on one or more of the same specific lines in the set of bus signal lines. According to another configuration described herein, the set of bus signal lines on the data bus includes a set of data lines and a separate set of command/address lines. The group read status command can be transmitted on the command/address lines. In some embodiments, the group read status command and the status data can be transmitted by the source node device and the bus node devices on the same command/address lines.
According to another aspect of the technology described herein, the status data includes multiple bits for each bus node device. For example, a bus node device can include a plurality of status units, each having status such as a ready status and a busy status. The status data transmitted by the bus node device in this case can include status of the plurality of status units for the bus node device.
Embodiments of the technology can be implemented in which the bus node devices respectively include a plurality of bonding pads connected to reference voltages, such as power and ground supply lines of the data bus, in different bonding patterns to provide local device addresses. The local device addresses can be used by logic on the bus node devices to determine the timing windows in which to transmit local status onto the bus.
In an aspect of the technology described herein, a bus node device comprises an integrated circuit device. The integrated circuit device can comprise a bus interface for connections to the data bus, and a circuit such as a status register, to provide status of resources on the integrated circuit device. For example, the integrated circuit device can comprise a high-density NAND flash memory device having a plurality of status units. The status register, or other status indicator, can provide status information for each of the status units in the plurality of status units.
The integrated circuit device can include a circuit to provide a local device identifier, such as a local device address within the group on the bus. The command decoder on the integrated circuit device is connected in communication with the bus interface. The command decoder includes circuits to detect a group read status command associated with an initial device identifier. In response to detection of the group read status command, the integrated circuit device executes an operation including:
Also, the operation can include outputting a transition state to the bus during transition timing windows at least one of before and after outputting the status.
Other aspects and advantages of the technology presented herein can be seen on review of the drawings, the detailed description and the claims, which follow.
A detailed description of embodiments of one or more aspects of the present technology is provided with reference to the
A first group of bus node devices 111, 112, . . . 113 is disposed on I/O BUS 1. A second group of bus node devices 121, 122, . . . 123 is disposed on I/O BUS 2. The bus node devices 111, 112 . . . 113 include bus slave interfaces to the bus signal lines on I/O BUS 1. The bus node devices 111, 112 . . . 113 each have a local device identifier, such as a device address unique as to other bus node devices on the same bus. In this example, bus node devices 111, 112 . . . 113 have respective local, device addresses LDA1, LDA2, LDAn, each of which is unique on I/O BUS 1. The bus node devices 121, 122 . . . 123 include bus slave interfaces to the bus signal lines on I/O BUS 2. The bus node devices 121, 122 . . . 123 each have a local device identifier, such as a device address unique as to other bus node devices on the same bus. In this example, bus node devices 121, 122 . . . 123 have respective local, device addresses LDA1, LDA2, LDAm, each of which is unique on I/O BUS 2.
The source node device 100 includes group read status logic which executes an operation to gather status information from the bus node devices in groups 1 and 2. A source node device may be distinguished in this context by having logic acting as a source of the group read status command. A bus node device may be distinguished by having logic to respond to a group read status command in this context. There may be more than one source node device. Also, a source node device may also include logic to act as a bus node device in systems having a plurality of source nodes.
In order to gather status information from bus node devices in group 1, the group read status logic at source node device 100 transmits one group read status command on the signal lines 110 of I/O BUS 1. The bus node devices 111, 112, 113 respond with status data in respective non-overlapping timing windows. The group read status logic at source node 100 links the status information with the corresponding operations at specific bus node devices based on the timing windows in which the status information is received.
Likewise, in order to gather status information from bus node devices in group 2, the group read status logic at source node device 100 transmits one group read status command on the signal lines 120 of I/O BUS 2. The bus node devices 121, 122, 123 respond with status data in respective non-overlapping timing windows. The group read status logic at source node device 100 links the status information with the corresponding operations at specific bus node devices based on the timing windows in which the status information is received.
The circuit 201 is connected for data communications with a bus interface 210, or other type of input/output I/O circuit. The bus interface 210 can be, for example, a bus slave interface, such as discussed with reference to
The bus interface 210 is connected to controller logic 230 on the integrated circuit device 200. In this example, the controller logic includes a device address counter 231, a multibit status register 232, and a command decoder 234. A local DA circuit 220 is provided that is connected to the control logic to provide a local device address LDA. The local device address LDA is a device identifier unique as to other bus node devices on the bus. The local DA circuit 220 can comprise a configuration register for the integrated circuit device 200. A configuration register can be implemented using nonvolatile memory cells, or one-time programmable memory cells. In some implementations, the local DA circuit 220 can be implemented using a register file, an SRAM, or other type of memory. Also, the local DA circuit 220 can be implemented using a plurality of pads on the integrated circuit device 200 that are connected to the reference voltages such as bus power and ground lines, in a pattern to set the local device address for the device 200. See for example,
The controller logic 230 executes an operation in response to detection of a group read status command by the command decoder 234, by which the status data from multibit status register 232 is transmitted via the bus interface 210 to the bus in a time window identified by the local device address indicated in the local DA circuit 220. As result, the status data for the integrated circuit device 200 is provided in a unique time window, relative to other bus node devices in a group. The status data may be transmitted in a data packet without an identifier of the bus node in some embodiments, other than the timing window. In other embodiments, the status data may be transmitted in a data packet with an identifier of the bus node as part of the data packet.
After loading the initial device identifier, the logic compares the local device address LDA provided by the circuit 220 to the output of the device address counter 231 (302). Next, it is determined whether the comparison of the local device address LDA provided by circuit 220 to the output of the device address counter 231 results in a match or not (303). If it is a match, the flow proceeds through point 304, and then the logic controller outputs a status packet (305) followed by an output transition packet (306). If there is not a match at block 303, then the flow proceeds through point 310, and the logic controller disables output on the bus (311), while the output status packet is output by a matching node as indicated in block 305, and disables output on the bus (312), and while the output transition packet is output by the matching node as indicated in block 306.
Transition intervals occur between the timing windows in which status data is transmitted on the bus by one of the bus nodes. When the transition interval occurs, then the controller logic outputs a transition state on the bus (306, 318). In the transition state, a fixed voltage, or fixed data, is outputted by the nodes to avoid the bus fighting issue between the matching die in the previous cycle and the matching die in the next cycle. The clock signal received by two dies may have an overlapping period, and there may be a bus fighting issue if two dies output different data. Therefore, fixed data (same data pattern or voltage for both dies) is outputted for both dies during the transition period to avoid the bus fighting. The transition state is output at the end of the status output by the matching die of the current cycle, and at the beginning of the status output for the matching die in the next cycle. The non-matching die can disable the respective bus drivers by setting a high impedance state.
After step 306 or step 312, the DA counter is advanced by incrementing the counter, in this example (315). Then, the logic compares the local device address LDA provided by the circuit 220 to the output of the device address counter 231 (316). Next, it is determined whether the comparison of the local device address LDA provided by circuit 220 to the output of the device address counter 231 results in a match or not (317). If it is a match, then the logic controller outputs an output transition packet, matching the output transition packet of the previously matching node. After block 318, then the operation loops to point 304 to output a status packet. If there is not a match at block 317, then the logic controller disables output on the bus (319), and then loops to point 310 to continue disabling the outputs.
As shown, the operation includes a bus timing window for outputting status packets (dashed box 350) and a bus timing window for outputting transition packets (dashed box 351).
If a command termination event occurs (not shown), then the operation terminates. A command termination event can comprise a transition of the control signal, such as a chip enable CE# control signal. Some alternative examples of a command termination event can be an overflow of the device address counter 231, a stop of toggling of a read enable signal, and expiry of the timeout interval.
The operation shown in
Also, the operation shown in
The flowchart of
As seen, the source node transmits a group read status command packet that includes a CMD field and an initial device address field, DA=1. At time t1, after toggling of the WE#, the bus nodes load the initial device address into the counter. At time t2 the bus nodes prepare their outputs for transmitting status data, and the RE# begins toggling and continues toggling until the completion of the operation. Also, the DQS signal toggles in coordination with the data transmitted by the bus nodes. At time t3, the bus node shown on line 411 outputs a status packet on the bus which is received at the source node on line 410. The status packet timing window ends at time t4. A transition interval is executed by the bus nodes between time t4 and t6, and the address counters on the bus nodes are incremented. At time t6, the bus node shown on line 412 outputs a status packet on the bus which is received at the source node. The timing window for the status packet ends at time t7. Thereafter a transition interval is executed by the bus nodes and the counters in the bus nodes are advanced, and the procedure continues until a termination event at which time all the bus nodes in the group of bus nodes on a given bus have transmitted status information to the source node. An example of a termination event can be changing a control signal on the bus from a toggling state to a steady state. For example a read enable signal RE# may be toggled by the source node during the group read status operation, and the termination event can be a stop of the toggling of the read enable signal.
As seen, the group read status command is transmitted by the source node on the data lines I/O[7:0], and the status packets include multiple bits, and are transmitted by the bus nodes on one or more of the same data lines I/O[7:0].
At time t4, a CA output write header is output on the CA[1:0] lines to start the output sequence. The CA_CLK begins toggling at a second clock rate. There are three clock cycles in this example to output status of each node. The first two are the status output cycles carrying 4 status bits, one for each plane on the CA[1] line. The third clock cycle corresponds with the transition interval in which the current node and the next node output the same voltage to prevent bus fighting. As shown in the drawing, there is a delay from the CA_CLK rising and falling edges to the data output at each node. Thus, as illustrated, during a timing window between t5 and t6, a status packet from device D0 is transmitted on the CA[1:0] lines. During a timing window between t6 and t7, a status packet from device D1 is transmitted on the CA[1:0] lines, and so on until the termination event is at time tn, indicated by a transition of the CA CE# signal to a high value.
As seen in this example, the group read status command is transmitted by the source on specific lines, which are the CA[1:0] lines in this example, and the status packets are transmitted on one of the specific lines (CA[1]) of the same CA[1:0] lines by the bus nodes. In other embodiments, both of the CA[1:0] lines may be utilized for the status packets. In other embodiments, the I/O[7:0] lines may be utilized for one or both of the command and the status packets.
In the embodiments of
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.
