Claims
- 1. In a computer system including at least one processing unit, a memory coupled to said at least one processing unit, and logic circuits coupled to said processing unit contributing to operation of said computer system, a method for controlling the operating mode and as a result the power consumption of said computer system between a plurality of operating modes each having a different electrical power consumption levels or ranges; said method comprising:
while operating in a first selected operating mode exhibiting that first selected mode's characteristic power consumption range, (i) monitoring said computer system to detect the occurrence or non-occurrence of a first event; and (ii) transitioning said computer system from said first selected operating mode to a second selected operating mode exhibiting that second selected operating mode's power consumption range.
- 2. The method in claim 1, wherein the first selected mode is a higher power consuming mode than the second selected mode.
- 3. The method in claim 1, wherein the first selected mode is a lower power consuming mode than the second selected mode.
- 4. The method in claim 1, wherein the computer system further comprises peripheral devices coupled to said at least one processing unit and said peripheral devices are power managed to reduce power consumption.
- 5. The method in claim 4, wherein said peripheral devices include a mass storage device storing data for retrieval of said data, and an output port for outputting selected portions of said stored data upon request.
- 6. The method in claim 1, wherein said first event comprises execution of a predetermined number of idle threads.
- 7. The method in claim 1, wherein said first event comprises execution of a single idle thread.
- 8. The method in claim 1, wherein said first event comprises execution of a predetermined plurality of idle threads.
- 9. The method in claim 1, wherein said first event comprises a wake on LAN signal event.
- 10. The method in claim 1, wherein said first event comprises the occurrence of some specified level of CPU processing capability availability that is derived from either an enumeration or a statistical evaluation of the idle thread or idle threads that are being or have been executed during some time period.
- 11. The method in claim 1, wherein one of said first and second events comprises a measured decrease in server load.
- 12. The method in claim 1, wherein one of said first and second events comprises a predicted decrease in server load.
- 13. The method in claim 1, wherein one of said first and second events comprises a measured decrease in processor tasking.
- 14. The method in claim 1, wherein one of said first and second events comprises a predicted decrease in processor tasking.
- 15. The method in claim 1, wherein one of said first and second events comprises a measured decrease in communication channel bandwidth.
- 16. The method in claim 1, wherein one of said first and second events comprises predicted decrease in communication channel bandwidth.
- 17. The method in claim 12, wherein said predicted decrease in server load is a prediction based at least in part on time of day.
- 18. The method in claim 12, wherein said predicted decrease in server load is a prediction based at least in part on a quality of service requirement.
- 19. The method in claim 12, wherein said predicted decrease in processor tasking is a prediction based at least in part on time of day.
- 20. The method in claim 12, wherein said predicted decrease in processor tasking is a prediction based at least in part type of content to be processed by the computer system.
- 21. The method in claim 12, wherein said predicted decrease in server loading is a prediction based at least in part type of content to be served by the computer system.
- 22. The method in claim 12, wherein the manner of said prediction is further based on the content served by the server computer system.
- 23. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 1) in which said processing unit is operated at substantially maximum rated processing unit clock frequency and at substantially maximum rated processing unit core voltage, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency and at a substantially maximum rated logic circuit operating voltage.
- 24. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 2) in which said processing unit is operated at less than maximum rated processing unit clock frequency and at less than or equal to a maximum rated processing unit core voltage, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency and at a substantially maximum rated logic circuit operating voltage.
- 25. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 2′) in which said processing unit is operated at less than maximum rated processing unit clock frequency and at less than a maximum rated processing unit core voltage, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency and at a substantially maximum rated logic circuit operating voltage.
- 26. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 2″) in which said processing unit is operated at less than maximum rated processing unit clock frequency and at less than a maximum rated processing unit core voltage, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency and at a substantially maximum rated logic circuit operating voltage.
- 27. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 2′″) in which said processing unit is operated at less than maximum rated processing unit clock frequency and at less than a maximum rated processing unit core voltage just sufficient to maintain switching circuits in said processor unit at said processing unit clock frequency, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency and at a substantially maximum rated logic circuit operating voltage.
- 28. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 3) in which said processing unit is operated at a slow but non-zero frequency processing unit clock frequency and at less than or equal to a maximum rated processing unit core voltage sufficient to maintain processor unit state, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency and at a substantially maximum rated logic circuit operating voltage.
- 29. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 3′) in which said processing unit is operated at a substantially zero frequency processing unit clock frequency (clock stopped) and at less than or equal to a maximum rated processing unit core voltage, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency and at a substantially maximum rated logic circuit operating voltage.
- 30. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 3″) in which said processing unit is operated at a substantially zero frequency processing unit clock frequency (processing unit clock stopped) and at a processing unit core voltage just sufficient to maintain processor unit state, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency and at a substantially maximum rated logic circuit operating voltage.
- 31. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 3′″) in which said processing unit is operated at a substantially zero frequency processing unit clock frequency (processing unit clock stopped) and at a processing unit core voltage just sufficient to maintain processor unit state, and said logic circuit is operated at a logic circuit clock frequency less than a maximum rated logic circuit clock frequency and at a logic circuit operating voltage that is less than or equal to a maximum rated logic circuit operating voltage.
- 32. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 3″″) in which said processing unit is operated at a substantially zero frequency processing unit clock frequency (processing unit clock stopped) and at a processing unit core voltage just sufficient to maintain processor unit state, and said logic circuit is operated at a logic circuit clock frequency less than a maximum rated logic circuit clock frequency and at a logic circuit operating voltage that is less than a maximum rated logic circuit operating voltage.
- 33. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 3′″″) in which said processing unit is operated at a substantially zero frequency processing unit clock frequency (processing unit clock stopped) and at a processing unit core voltage just sufficient to maintain processor unit state, and said logic circuit is operated at a substantially zero logic circuit clock frequency and at a logic circuit operating voltage that is just sufficient to maintain logic circuit operating state.
- 34. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 4) in which said processing unit is powered off by removing a processing unit clock frequency (processing unit clock stopped) and a processing unit core voltage.
- 35. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 4′) in which said processing unit is powered off by removing a processing unit clock frequency (processing unit clock stopped) and a processing unit core voltage; and said logic circuit is powered off by removing said logic circuit clock and by removing said logic circuit operating voltage or by setting said logic circuit operating voltage below a level that will maintain state, except that a real-time clock and circuit for waking said logic circuit and said processing unit are maintained in operation.
- 36. The method in claim 1, wherein one of said first selected operating mode and said second selected operating mode comprises a mode (Mode 4″) in which said processing unit is powered off by removing a processing unit clock frequency (processing unit clock stopped) and a processing unit core voltage; and said logic circuit is powered off by removing said logic circuit clock and by removing said logic circuit operating voltage or by setting said logic circuit operating voltage below a level that will maintain state, except that a circuit for waking said logic circuit and said processing unit are maintained in operation.
- 37. The method in claim 1, further comprising:
while operating in said second selected operating mode exhibiting that second selected mode's characteristic power consumption range, (i) monitoring said computer system to detect the occurrence or non-occurrence of a second event; and (ii) transitioning said computer system from said second selected operating mode to a third selected operating mode exhibiting that third selected operating mode's power consumption range.
- 38. The method in claim 1, wherein said first selected operating mode and said second selected operating mode comprises different operating modes selected from the set of operating modes consisting of:
(i) a mode in which said processing unit is operated at substantially maximum rated processing unit clock frequency and at substantially maximum rated processing unit core voltage, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency; (ii) a mode in which said processing unit is operated at less than maximum rated processing unit clock frequency and at less than or equal to a maximum rated processing unit core voltage, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency; and (iii) a mode in which said processing unit is operated at a substantially zero frequency processing unit clock frequency (clock stopped) and at less than or equal to a maximum rated processing unit core voltage sufficient to maintain processor unit state, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency.
- 39. The method in claim 38, wherein said set further consists of a mode in which said processing unit is powered off by removing a processing unit clock frequency (processing unit clock stopped) and a processing unit core voltage.
- 40. The method in claim 1, further comprising:
while operating in said second selected operating mode exhibiting that second selected mode's characteristic power consumption range, (i) monitoring said computer system to detect the occurrence or non-occurrence of a second event; and (ii) transitioning said computer system from said second selected operating mode to a third selected operating mode exhibiting that third selected operating mode's power consumption range.
- 41. The method in claim 40, wherein said first selected operating mode and said second selected operating mode comprises different operating modes, and said second selected operating mode and said third selected operating mode comprise different operating modes, each of said first, second, and third operating modes being selected from the set of modes consisting of:
(i) a mode in which said processing unit is operated at substantially maximum rated processing unit clock frequency and at substantially maximum rated processing unit core voltage, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency; (ii) a mode in which said processing unit is operated at less than maximum rated processing unit clock frequency and at less than or equal to a maximum rated processing unit core voltage, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency; and (iii) a mode in which said processing unit is operated at a substantially zero frequency processing unit clock frequency (clock stopped) and at less than or equal to a maximum rated processing unit core voltage sufficient to maintain processor unit state, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency.
- 42. The method in claim 41, wherein said set further consists of a mode in which said processing unit is powered off by removing a processing unit clock frequency (processing unit clock stopped) and a processing unit core voltage.
- 43. A computer program product for use in conjunction with a computer system including at least one processing unit, a memory coupled to said at least one processing unit, and logic circuits coupled to said processing unit contributing to operation of said computer system, a method for controlling the operating mode and as a result the power consumption of said computer system between a plurality of operating modes each having a different electrical power consumption levels or ranges; the computer program product comprising a computer readable storage medium and a computer program mechanism embedded therein, the computer program mechanism, comprising:
a program module that directs said computer system to function in a specified manner, the program module including instructions for:
(i) monitoring said computer system to detect the occurrence or non-occurrence of a first event while operating in a first selected operating mode exhibiting that first selected mode's characteristic power consumption range; and (ii) transitioning said computer system from said first selected operating mode to a second selected operating mode exhibiting that second selected operating mode's power consumption range.
- 44. The computer program product in claim 43, wherein the program module further including instructions for:
while operating in said second selected operating mode exhibiting that second selected mode's characteristic power consumption range, (i) monitoring said computer system to detect the occurrence or non-occurrence of a second event; and (ii) transitioning said computer system from said second selected operating mode to a third selected operating mode exhibiting that third selected operating mode's power consumption range.
- 45. The computer program product in claim 44, wherein said first selected operating mode and said second selected operating mode comprises different operating modes, and said second selected operating mode and said third selected operating mode comprise different operating modes, each of said first, second, and third operating modes being selected from the set of modes consisting of:
(i) a mode in which said processing unit is operated at substantially maximum rated processing unit clock frequency and at substantially maximum rated processing unit core voltage, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency; (ii) a mode in which said processing unit is operated at less than maximum rated processing unit clock frequency and at less than or equal to a maximum rated processing unit core voltage, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency; and (iii) a mode in which said processing unit is operated at a substantially zero frequency processing unit clock frequency and at less than or equal to a maximum rated processing unit core voltage sufficient to maintain processor unit state, and said logic circuit is operated at substantially maximum rated logic circuit clock frequency.
- 46. The computer program product in claim 45, wherein said set further consists of a mode in which said processing unit is powered off by removing a processing unit clock frequency and a processing unit core voltage.
- 47. A computer system comprising:
at least one processing unit and a memory coupled to said at least one processing unit; and logic circuits coupled to said processing unit contributing to operation of said computer system; a controller for controlling the operating mode and as a result, the power consumption of said computer system between a plurality of operating modes each having a different electrical power consumption levels or ranges; said controller being operable while operating in a first selected operating mode exhibiting that first selected mode's characteristic power consumption range, (i) to monitor said computer system to detect the occurrence or non-occurrence of a first event; and (ii) to transition said computer system from said first selected operating mode to a second selected operating mode exhibiting that second selected operating mode's power consumption range.
RELATED APPLICATIONS
[0001] This application is a continuing application under 35 U.S.C. §§119(e) and 120, wherein applicant and inventor claim the benefit of priority to U.S. Provisional Application Ser. No. 60/283,375 entitled System, Method And Architecture For Dynamic Server Power Management And Dynamic Workload Management for Multi-Server Environment filed Apr. 11, 2001; U.S. Provisional Application Ser. No. 60/236,043 entitled System, Apparatus, and Method for Power-Conserving Multi-Node Server Architecture filed Sep. 27, 2000; and U.S. Provisional Application Ser. No. 60/236,062 entitled System, Apparatus, and Method for Power Conserving and Disc-Drive Life Prolonging RAID Configuration filed Sep. 27, 2000; each of which application is hereby incorporated by reference.
[0002] The following United States Utility Patent Applications are also related applications: U.S. Utility patent application Ser. No. 09/______ ,______ (Attorney Docket No. A-70531/RMA) entitled System, Method, and Architecture for Dynamic Server Power Management and Dynamic Workload Management for Multi-server Environment filed May __, 2001; U.S. Utility patent application Ser. No. 09/___,___ (Attorney Docket No. A-70532/RMA) entitled System and Method for Activity or Event Based Dynamic Energy Conserving Server Reconfiguration filed May __, 2001; U.S. Utility patent application Ser. No. 09/___,___ (Attorney Docket No. A-70533/RMA) entitled System, Method, Architecture, and Computer Program Product for Dynamic Power Management in a Computer System filed May __, 2001; U.S. Utility patent application Ser. No. 09/___,___ (Attorney Docket No. A-70534/RMA) entitled Apparatus, Architecture, and Method for Integrated Modular Server System Providing Dynamically Power-managed and Work-load Managed Network Devices filed May __, 2001; U.S. Utility patent application Ser. No.09/___,___ (Attorney Docket No. A-70535/RMA) entitled System, Architecture, and Method for Logical Server and Other Network Devices in a Dynamically Configurable Multi-server Network Environment filed May __, 2001; U.S. Utility patent application Ser. No. 09/______,______ (Attorney Docket No. A-70536/RMA) entitled Apparatus and Method for Modular Dynamically Power-Managed Power Supply and Cooling System for Computer Systems, Server Applications, and Other Electronic Devices filed May __, 2001; and, U.S. Utility patent application Ser. No. 09/______,______ (Attorney Docket No. A-70537/RMA) entitled Power on Demand and Workload Management System and Method; each of which applications is hereby incorporated by reference.
[0003] This is also a continuing application claiming the benefit of priority under 35 U.S.C. §120 to each of the following applications: U.S. patent application Ser. No. 09/558,473 filed Apr. 25, 2000, entitled System and Method Of Computer Operating Mode Clock Control For Power Consumption Reduction; which is a continuation of U.S. patent application Ser. No. 09/121,352 filed Jul. 23, 1998, entitled System and Method of Computer Operating Mode Control for Power Consumption Reduction; which is a division of application Ser. No. 08/767,821 filed Dec. 17, 1996, entitled Computer Activity Monitor Providing Idle Thread and Other Event Sensitive Clock and Power Control abandoned; which is a continuation of application Ser. No. 08/460,191 filed Jun. 2, 1995, entitled Activity Monitor That Allows Activity Sensitive Reduced Power Operation of a Computer System abandoned; which is a continuation of application Ser. No. 08/285,169 filed Aug. 3, 1994, entitled Power Management for Data Processing System, abandoned; which is a continuation of application Ser. No.08/017,975 filed Feb. 12, 1993 entitled Power Conservation Apparatus Having Multiple Power Reduction Levels Dependent Upon the Activity of a Computer System, U.S. Pat. No. 5,396,635; which is a continuation of application Ser. No. 07/908,533 filed Jun. 29, 1992 entitled Improved Power Management for Data Processing System, abandoned; which is a continuation of application Ser. No. 07/532,314 filed Jun. 1, 1990 entitled, Power Management for Data Processing System, now abandoned; each of which applications are hereby incorporated by reference.
[0004] This application is also related to: U.S. Pat. No. 6,079,025 issued Jun. 20, 2000 entitled system and Method of Computer Operating Mode Control For Power Consumption System; U.S. Pat. No. 5,892,959 issued Apr. 6, 1999 entitled Computer Activity Monitor Providing Idle Thread And Other Event Sensitive Clock and Power Control; U.S. Pat. No. 5,799,198 issued Aug. 25, 1998 entitled Activity Monitor For Computer systems Power Management; U.S. Pat. No. 5,758,175 issued May 26, 1998 entitled Multi-Mode Power Switching For Computer Systems; U.S. Pat. No. 5,710,929 issued Jan. 20, 1998 entitled Multi-State Power Management For Computer System; and U.S. Pat. No. 5,396,635 issued Mar. 7, 1995 for Power Conservation Apparatus Having Multiple Power Reduction Levels Dependent Upon the Activity of a Computer System; each of which patents are herein incorporated by reference.
Provisional Applications (3)
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Number |
Date |
Country |
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60283375 |
Apr 2001 |
US |
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60236043 |
Sep 2000 |
US |
|
60236062 |
Sep 2000 |
US |
Continuations (8)
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Number |
Date |
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| Parent |
09121352 |
Jul 1998 |
US |
| Child |
09860303 |
May 2001 |
US |
| Parent |
08767821 |
Dec 1996 |
US |
| Child |
09860303 |
May 2001 |
US |
| Parent |
08460191 |
Jun 1995 |
US |
| Child |
09860303 |
May 2001 |
US |
| Parent |
08285169 |
Aug 1994 |
US |
| Child |
09860303 |
May 2001 |
US |
| Parent |
09558473 |
Apr 2000 |
US |
| Child |
09860303 |
May 2001 |
US |
| Parent |
08017975 |
Feb 1993 |
US |
| Child |
09860303 |
May 2001 |
US |
| Parent |
07908533 |
Jun 1992 |
US |
| Child |
09860303 |
May 2001 |
US |
| Parent |
07532314 |
Jun 1990 |
US |
| Child |
09860303 |
May 2001 |
US |
Patent Application
20020004915
