Patent Application
20190172047
The present invention relates to the field of chip technologies, and in particular, to a system on chip and a processing device.
Mobile payment (Mobile Payment) is a service manner of allowing a user to pay for consumed goods or services by using a mobile terminal, for example, a mobile phone, a tablet computer, or a wearable device. At present, there are three manners of implementing mobile payment by using a mobile terminal. The three manners are respectively a secure digital (SD) card solution, a subscriber identity module (SIM) solution, and an all-terminal solution combining Near Field Communication (NFC) and a secure element (SE). Currently, the all-terminal solution combining Near Field Communication and a secure element is becoming a mainstream solution of implementing mobile payment. In addition, these several solutions present a tendency of being combined. For example, the secure element may also have a SIM function or another function.
An existing all-terminal solution is shown in
The all-terminal solution may include online payment and offline payment. During offline payment, as shown in
The Chinese Patent Application No. 201510201343.9 provides a solution of integrating the secure element 102 and the central processing unit 103 (or optionally including a mobile communication unit 105) on a same semiconductor substrate, that is, integrating the secure element 102 and the central processing unit 103 on a main chip 106. In addition, the secure element 102 may load, from a storage unit outside the main chip 106, general-purpose operating system software required by the central processing unit 103, such as Android or Windows operating system software. A system formed by integrating multiple components on one semiconductor substrate or semiconductor chip may be referred to as an SoC. Obviously, integrating the secure element 102 and the central processing unit 103 on the SoC may have many advantages. For example, costs are greatly reduced, and layout space of the SoC on a PCB (printed circuit board) is reduced, so that the secure element 102 and the central processing unit 103 can be based on a same advanced integrated circuit manufacturing technology. Improvement of the technology means enhancement of security.
With development of a mobile application scenario, there are more types of software application executed by the secure element 102, and an application scenario of the secure element 102 is no longer limited to mobile payment, and may further include some software related to SIM cards, for example, software application customized by a communications operator. Therefore, complexity of an SoC implemented in an integrated manner becomes higher, and how to implement an SoC having high integration and complex functions and fully meeting a security requirement has become a problem. For example, in the Chinese Patent No. 201510201343.9, a central processing unit may form a trustzone (TZ) outside an environment of a general-purpose operating system. The TZ is a trusted execution environment (TEE). A user may enter some information related to a security application such as mobile payment in the TEE, and application operations of different security levels are implemented in the TEE and the environment of the general-purpose operating system respectively. Because the TEE is an environment generated by the central processing unit, security of the TEE still needs to be improved. For example, the secure element 102 may exchange some particular information with a peripheral device through the existing TEE. For example, the secure element 102 exchanges fingerprint data with a fingerprint sensor through the TEE. Because related information may be transmitted through the TEE, security of the information exchange may be reduced. Therefore, how to implement a mobile payment service based on NFC communication on an SoC on the premise of ensuring security becomes a problem that needs to be resolved urgently.
Embodiments of the present invention provide an SoC and a processing device, so as to improve security of a mobile payment service based on NFC communication in a highly-integrated SoC.
According to a first aspect, an embodiment of the present invention provides an SoC, where the SoC is integrated on a first semiconductor chip, and includes: a system bus, at least one processor coupled to the system bus, and a security processor system coupled to the system bus, where security isolation exists between the security processor system and the at least one processor; the at least one processor includes at least one central processing unit, where the at least one central processing unit is configured to: execute general-purpose operating system software, and communicate with the security processor system through the system bus under the action of the general-purpose operating system software; and the security processor system includes a security processor, a first memory, multiple interfaces, and a security bus, where the security processor, the first memory, and the multiple interfaces are coupled to the security bus, and the security bus is coupled to the system bus, where the security processor is configured to execute security operating system software and at least one security software application based on the security operating system software, where the at least one security software application includes mobile payment software used to implement mobile payment; the first memory is configured to provide storage space used by the security processor to execute the security operating system software and the at least one security software application; and the multiple interfaces include a near field communication NFC interface and a biometric recognition input interface, where the NFC interface is configured to exchange NFC information related to the mobile payment with an NFC peer through an NFC processor; and the biometric recognition input interface is configured to receive biometric recognition data from a biometric recognition sensor, where the biometric recognition data is used for user authentication based on biometric recognition in the mobile payment. Optionally, the NFC information includes at least one of a mobile payment instruction, mobile payment data, or NFC authentication information. Further, under the security isolation, the at least one processor cannot directly access the first memory or at least one register in the security processor system. For example, the at least one processor may be coupled to the security processor system through a dedicated interaction channel.
The foregoing SoC integrates functions of a processor and a security processor system, so that implementation costs and an area of the entire system can be reduced. In addition, a function equivalent to that of a secure element is implemented in the security processor system, and at least one security software application including mobile payment software can be executed. In addition, a biometric recognition input interface belonging to the security processor system is integrated in the security processor system, so that biometric recognition data can be conveniently obtained. Besides, security isolation exists between the security processor system and the at least one processor. When a mobile payment service based on NFC communication is performed, this solution has higher security, compared with a solution of transferring biometric recognition data of a user to the security processor system through a TEE of a central processing unit.
According to the description of the first aspect, in a possible implementation, communication between the at least one central processing unit and the security processor system includes exchange of data or exchange of an instruction. The instruction may be an instruction for controlling or operating the security processor system by the at least one central processing unit, and includes but is not limited to a startup instruction, a disable instruction, a restart instruction, a sleep instruction, an instruction for entering or exiting a low power consumption state, or an operation suspension or recovery instruction. By means of the foregoing exchange process, an operating state of the security processor system may be controlled by the at least one central processing unit, but security of data in the security processor system is not affected.
According to the description of the first aspect, in a possible implementation, the security processor system may be configured to implement a function of a secure element or a SIM function. The security processor equivalently implements the function of the secure element, and may further integrate another function. Therefore, the at least one security software application may include other security software applications, such as SIM software. By implementing functions of the software in the security processor system, a security application scenario of the SoC may be expanded.
According to the description of the first aspect, in a possible implementation, the first memory may be a volatile memory, for example, a random access memory (RAM). The first memory may be configured to store the security operating system software and the at least one security software application that are loaded, and may be further configured to store secure temporary data generated when the security operating system software and the at least one security software application are executed. The secure temporary data is intermediate data, an intermediate operation result, or other information that is related to the security software application or executing of the security software application and that does not need to be stored for a long time, where the secure temporary data is generated when the security processor executes the security operating system software and the at least one security software application. Therefore, the RAM is a volatile storage device, for example, an SRAM (static random access memory), a DRAM (dynamic random access memory), or an SDRAM (synchronous dynamic random access memory), and preferably, is an SRAM. The RAM is integrated in the SoC. Therefore, the RAM may use a manufacturing technology the same as that of the at least one central processing unit, and the technology is relatively easy to implement.
According to the description of the first aspect, in a possible implementation, the multiple interfaces further include a security input interface, configured to receive user information related to the mobile payment that is input by a user. Optionally, the user information includes a password, a user instruction, or a financial transaction amount. Optionally, the security input interface is coupled to an input device, to receive the user information by using the input device. For example, the input device may be a touchscreen or a key. In this implementation, because an interface of the user information is also integrated in the security processor system, acquiring of the user information does not rely on a TEE of the central processing unit anymore, and higher security can be implemented.
According to the description of the first aspect, in a possible implementation, the multiple interfaces further include a peripheral interface, configured to indicate, by using a peripheral device, to the user that the mobile payment is performed. For example, the peripheral device is an indication device, and the peripheral interface is coupled to the indication device. The indication device may be an indicator, a loudspeaker configured to play a sound, or a vibrator, and is configured to prompt the user that the mobile payment is being performed, has been performed, or is to be performed. In this implementation, because the peripheral interface is also integrated in the security processor system, transmission of indication information does not need to rely on the TEE of the central processing unit anymore either, and higher security can be implemented.
According to the description of the first aspect, in a possible implementation, the security processor system further includes a nonvolatile second memory that is coupled to the security bus and that is configured to store the security operating system software and the at least one security software application; and the security processor is configured to: read the security operating system software and the at least one security software application from the second memory, and load the security operating system software and the at least one security software application to the first memory to execute the security operating system software and the at least one security software application. Because the second memory is also integrated in the SoC, all software executed by the security processor is stored in the second memory for a long time, and there is no need to rely on a memory outside the SoC to store the security operating system software and the at least one security software application, so that the security is high.
According to the description of the first aspect, in a possible implementation, under the security isolation, the security processor system further includes a security isolation device that is coupled to the security bus and that is configured to implement the security isolation. The at least one processor communicates with the security processor system through the system bus and the security isolation device. Further, the security isolation device includes at least one of an isolation memory or a bus bridge; and the isolation memory or the bus bridge is configured to exchange data or instruction between the at least one processor and the security processor system. For example, the at least one central processing unit may be coupled to the security processor system through the system bus and the isolation memory or the bus bridge under the action of the general-purpose operating system software, to communicate with the security processor system. Content of the communication includes data or an instruction. The bus bridge may be a bus bridging between the security bus and the system bus. Further, under the security isolation, the at least one processor cannot directly access any component in the security processor system except the isolation memory or the bus bridge. The at least one processor and the security processor system only use either the isolation memory or the bus bridge as a dedicated interaction channel, or even a unique interaction channel. Therefore, the at least one processor is prevented from directly accessing the first memory or any component or module in the security processor system, so that the security can be improved.
According to the description of the first aspect, in a possible implementation, the security processor system further includes a secure boot memory that is coupled to the security bus and that is configured to store a boot program instruction for initialization of the security processor; and before executing the security operating system software and the at least one security software application, the security processor obtains the boot program instruction from the secure boot memory to initialize the security processor. The secure boot memory is a nonvolatile memory, for example, a ROM. Similar to a BIOS (basic input/output system) in a conventional PC (personal computer), the secure boot memory ensures that an initial startup of the security processor system starts form the secure boot memory each time, to ensure startup security. For example, when the security processor system is powered on, the security processor is configured to: read the boot program instruction from the secure boot memory, and load the security operating system software to the first memory under the action of the boot program instruction, to execute the security operating system software.
In the foregoing implementation, optionally, the boot program instruction is an encrypted boot program instruction; and when the security processor obtains the boot program instruction from the secure boot memory, the boot program instruction is decrypted by a decryption logic circuit to obtain a decrypted boot program instruction, where the decrypted boot program instruction is used to initialize the security processor. This solution can further ensure the startup security.
According to the description of the first aspect, in a possible implementation, the security processor system further includes a one-time programmable (OTP) memory that is coupled to the security bus and that is configured to store a security parameter of the security processor system, where the security parameter includes at least one of a root key, a calibration parameter, a configuration parameter, or an enable parameter. For example, the root key is used to generate another key for encryption and decryption of the security processor system. The calibration parameter includes a parameter for performing calibration on at least one component in the security processor system. The configuration parameter includes a configuration parameter of at least one component in the security processor system. The enable parameter includes a parameter for controlling at least one component in the security processor system to turn on or turn off. The security parameter may be programmed in the OTP memory, to calibrate, configure, or set the security processor system, or close or disable functions of some devices in the security processor system. Therefore, the OTP memory makes some internal functions of the corresponding security processor system still configurable or changeable after the SoC is manufactured. This improves design flexibility after the SoC is manufactured.
In the foregoing implementation, optionally, the OTP memory is further configured to store a patch program instruction of the boot program instruction for the initialization of the security processor. The patch program instruction may be a supplement to the boot program instruction or a replacement of some programs in the boot program instruction. For example, after the SoC is manufactured, if it is found that the boot program instruction has a deficiency, the deficiency of the existing boot program instruction may still be compensated for by programming the patch program instruction in the OTP memory, so that implementation is more flexible.
According to the description of the first aspect, in a possible implementation, the security processor system further includes an anti-attack sensor, configured to: detect an exception of an operating parameter of the security processor system, and trigger at least one of the following operations when the exception occurs: the security processor system performs an alarm, the security processor resets, or the first memory or at least one register in the security processor system is reset or emptied, where the operating parameter includes at least one of a voltage, a current, a clock frequency, a temperature, or a laser intensity. By means of this implementation, the security of the security processor system executing the security software application is further improved.
According to the description of the first aspect, in a possible implementation, the security processor system further includes an anti-attack metal layer, where the anti-attack metal layer is located on one or more topmost layers of the first semiconductor chip, and covers at least one part of the security processor system in a layout; and the anti-attack metal layer is configured to: detect an external physical detection or attack, and generate an electrical signal when the physical detection or attack is detected, where the electrical signal is used to trigger at least one of the following operations: the security processor system performs an alarm, the security processor resets, or the first memory or the at least one register in the security processor system is reset or emptied. In this implementation, an anti-attack metal layer technology is effectively applied to the SoC, so that the security of the security processor system executing the security software application is further improved. Optionally, the anti-attack metal layer is a shielding metal layer.
According to the description of the first aspect, in a possible implementation, the security bus includes at least one of an advanced high-performance bus (AHB) or an advanced peripheral bus (APB). Optionally, different parts, elements, or circuits in the security processor system may be further classified into different security levels. Connection is performed by using bus technologies of different levels, so that rate requirements and security requirements of different components in the security processor system can be satisfied. Optionally, data transmitted on the security bus or a related address may be processed in one or more manners such as encryption, scrambling, or cyclic redundancy check (CRC), to ensure privacy and integrity of the data on the security bus and the address.
According to the description of the first aspect, in a possible implementation, the security processor system further includes a direct memory access (DMA) controller that is coupled to the security bus and that is configured to: read data from the first memory and output the data to the security bus, or write data to the first memory by using the security bus. Because of the DMA controller, data read or write efficiency is improved.
According to the description of the first aspect, in a possible implementation, the security processor system further includes a cipher system coupled to the security bus, where the cipher system includes at least one of the following: an encryption and decryption device, configured to perform encryption and decryption processing on at least one type of data in the security processor system; an authentication device, configured to authenticate at least one type of data in the security processor system; a random number generator, configured to generate a random number, where the random number is used as a seed for generating a key or a unique chip identifier; or a key manager, configured to generate, distribute, or destruct, in the security processor system, a key for performing the encryption and decryption processing or the authentication. Optionally, the cipher system is a hardware accelerator that can implement quick and secure operations or processing, and processing security of the cipher system is higher than security of processing performed by a software program executed by the security processor.
Optionally, in the foregoing implementation, the authentication device is configured to perform the user authentication based on the biometric recognition. Alternatively, the user authentication may be performed by the security processor. It can be understood that efficiency of performing the user authentication by using the authentication device is higher, but costs are slightly increased.
In the foregoing implementation, optionally, the at least one processor further includes: a communication processor, configured to send first communication data to a wireless access point or receive second communication data from the wireless access point; and a speech signal processor, configured to: process a speech signal from the user to generate the first communication data sent by the communication processor, or process the second communication data received by the communication processor to obtain a speech signal needed by the user, where the encryption and decryption device is further configured to perform encryption processing on the first communication data or perform decryption processing on the second communication data. In the integrated SoC, the encryption and decryption device in the security processor system originally implementing a function of a secure element is further configured to perform another function, for example, speech signal-based encryption and decryption processing on communication data, so that diversified security processing capabilities are implemented. Optionally, the speech signal may be a PS (packet switched) domain speech signal or a CS (circuit switched) domain speech signal. Optionally, the speech signal processor may include at least one of a HiFi (high-fidelity) processor or a speech codec. The HiFi processor may be configured to implement processing on the speech signal, such as echo cancellation, smoothing, or timbre enhancement. The speech codec may be configured to implement speech coding and decoding operations, to implement conversion between the speech signal in a digital form and a natural analog speech signal (a common voice signal). Optionally, the wireless access point may be a base station, and the communication processor may be a cellular communication processor.
Alternatively, the at least one processor may further include: a communication processor. The encryption and decryption device is further configured to perform encryption processing on the biometric recognition data to obtain encrypted biometric recognition data; and the communication processor is configured to send, through a wireless access point, the encrypted biometric recognition data to a server configured to perform the user authentication. In this implementation, the biometric recognition data may be uploaded to the server by using the communication processor, and the server implements the user authentication, so that authentication costs of the SoC are reduced. Optionally, the communication processor includes at least one of a cellular communication processor or a short-range communication processor. That is, communication transmission may be implemented in multiple different manners.
Optionally, for the foregoing possible implementations, the cellular communication processor may support at least one of the following cellular wireless communications protocols: GSM, UMTS, WiMAX, TDS-CDMA, CDMA2000, LTE, or 5G. Optionally, the short-range communication processor may support at least one of infrared, Wireless Fidelity (WiFi), Bluetooth, or LTE D2D (device to device).
According to the description of the first aspect, in a possible implementation, the at least one processor further includes at least one of the following: a graphics processing unit (GPU), a system power management unit, or a system peripheral interface. The GPU is configured to process an image signal. The system power management unit is configured to control system power consumption of the SoC, for example, manage and control a clock and a working voltage of the SoC or at least one component in the SoC. There may be multiple system peripheral interfaces that are respectively configured to be coupled to multiple peripheral devices. For example, the peripheral device may be at least one of a USB (Universal Serial Bus) device, a display, a sensor, a camera, a headset, or a loudspeaker.
According to the description of the first aspect, in a possible implementation, the SoC further includes: the NFC processor. Alternatively, the NFC processor may be disposed outside the SoC. When the NFC processor is included in the SoC, manufacturing costs of the entire system can be further reduced.
According to the description of the first aspect, in a possible implementation, the security processor is further configured to perform the user authentication by using the biometric recognition data. Alternatively, the security processor system further includes: a biometric recognition authenticator, configured to perform the user authentication by using the biometric recognition data. When the dedicated biometric recognition authenticator is used, the biometric recognition authenticator is equivalent to a hardware accelerator, and equivalently, a user authentication function is actually implemented by using the dedicated accelerator, so that the security and a speed are higher. Oppositely, if the user authentication is implemented by using the security processor, costs for manufacturing and designing the dedicated accelerator can be saved.
According to the description of the first aspect, in a possible implementation, the multiple interfaces further include a storage interface, configured to be coupled to a third memory, where the third memory is configured to store the security operating system software and the at least one security software application; and the security processor is configured to: read the security operating system software and the at least one security software application from the third memory by using the storage interface, and load the security operating system software and the at least one security software application to the first memory to execute the security operating system software and the at least one security software application. In this implementation, the third memory is coupled to the security processor system through the dedicated storage interface. In this way, the security operating system software and the at least one security software application are both read by using the dedicated storage interface without relying on the TEE of the central processing unit, so that higher security can be implemented. Optionally, the third memory is integrated on a second semiconductor chip different from the first semiconductor chip. Optionally, the third memory is a nonvolatile memory, and may be a flash memory. Optionally, the third memory is dedicated to storing the security operating system software and the at least one security software application, and is not configured to store insecure common software, so that higher security is implemented.
According to the description of the first aspect, in a possible implementation, the biometric recognition includes at least one of the following: fingerprint recognition, iris recognition, voiceprint recognition, human face recognition, or smell recognition. Correspondingly, the biometric recognition sensor may include at least one of the following: a fingerprint sensor, an iris sensor, a voiceprint sensor, an image sensor, or a smell sensor. Correspondingly, the biometric recognition input interface may include at least one of the following: a fingerprint input interface, an iris data input interface, a voiceprint input interface, a human-face image input interface, or a smell data input interface.
According to a second aspect, an embodiment of the present invention further provides a processing device, including the SoC according to the first aspect or any possible implementation of the first aspect. The processing device further includes a fourth memory integrated on a third semiconductor chip, where the SoC is coupled to the fourth memory through an inter-chip interface, and the fourth memory includes a secure storage area and a common storage area that are mutually isolated; the secure storage area is used to store the security operating system software and the at least one security software application; the common storage area is used to store the general-purpose operating system software; the at least one central processing unit is configured to: obtain the general-purpose operating system software from the common storage area by using the inter-chip interface, and execute the general-purpose operating system software; and the security processor is configured to: obtain the security operating system software and the at least one security software application from the secure storage area by using the inter-chip interface, a system bus, and a security bus, and execute the security operating system software and the at least one security software application. In the second aspect, both secure software and insecure software may be stored in the fourth memory. Therefore, hardware reuse is implemented, and costs are reduced. Optionally, the processing device is a mobile terminal. Optionally, the fourth memory is a nonvolatile memory, for example, an EMMC (embedded multimedia card) or a UFS (universal flash storage).
According to a third aspect, an embodiment of the present invention further provides a data processing method. The method is performed by the SoC according to the first aspect or any possible implementation of the first aspect. The method includes at least: exchanging NFC information related to the mobile payment with an NFC peer through an NFC interface; receiving biometric recognition data from a biometric recognition sensor, where the biometric recognition data is used for user authentication based on biometric recognition in the mobile payment; and displaying at least one item of display information to a user by using a user interface (UI). Optionally, the display information includes at least one of a user information input interface, a transaction interface of the mobile payment, or a transaction success interface.
Optionally, according to the description of the third aspect, in a possible implementation, the user interface is formed as driven by UI software that is executed by the at least one central processing unit and that is based on the general-purpose operating system software, or the user interface is formed as driven by secure user interface software in the at least one security software application executed by the security processor.
According to the embodiments of the present invention, the security processor system receives various types of information by using a dedicated interface of the security processor system without relying on a conventional TEE, so that security is improved.
To describe the technical solutions in the embodiments of the present invention or in the prior art more clearly, the following briefly describes the accompanying drawings required for describing the embodiments or the prior art. Apparently, the accompanying drawings in the following description show merely some embodiments of the present invention or the prior art, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.
The following clearly describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are merely some but not all of the embodiments of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
In the embodiments of the present invention, a mobile terminal may also be referred to as user equipment (UE), a wireless terminal, or a user terminal, and may enjoy a wireless access service of a service station or a wireless access point. The service station or the wireless access point is generally a base station, for example, an eNodeB or a NodeB in LTE (Long Term Evolution), or may be an access point configured to connect user equipment to a mobile communications network, for example, a base station controller in a GSM mode. When the service station provides a connection service to a mobile terminal, one or more cells may be formed. One cell may geographically cover a particular range and occupy a carrier segment or a frequency band segment in a frequency domain. Specifically, the mobile terminal and the service station may implement a communication process by executing a wireless communications protocol. The wireless communications protocol includes but is not limited to various cellular wireless communications protocols such as GSM, UMTS, WiMAX, TDS-CDMA, CDMA2000, LTE, or 5G.
The system on chip (SoC) used in this embodiment of the present invention is a system manufactured on a same semiconductor chip or semiconductor substrate by using an integrated circuit technology. The semiconductor chip is also briefly referred to as a chip, and may be a set of integrated circuits formed on an integrated circuit substrate (which is usually a semiconductor material such as silicon) by means of manufacturing of the integrated circuit technology. An external layer of the semiconductor chip is usually packaged by a semiconductor package material. The integrated circuit may include various types of functional devices. Each type of functional device includes a logic gate circuit or a transistor such as a metal-oxide-semiconductor (MOS) transistor, a bipolar transistor, or a diode, or may include another component such as a capacitor, a resistor, or an inductor. The functional device may operate independently or operate under the action of necessary drive software, and may implement various functions such as communication, operation, or storage. Therefore, functional devices or modules of the apparatus mentioned in the embodiments of the present invention may be hardware, and each functional device may include multiple logic gate circuits or transistors. In this embodiment, the system memory 22 and the system on chip 21 are located on different semiconductor chips respectively. For example, the system on chip 21 is located on a first semiconductor chip, and the system memory 22 is located on a third semiconductor chip. Optionally, the system memory 22 is a nonvolatile memory, for example, an EMMC or a UFS.
In
In each embodiment of the present invention, the security isolation can be used to restrict access of the at least one processor to a device or a module in the security processor system 23. Under the security isolation, the at least one processor including the central processing unit 211 cannot directly access the random access memory 32 or at least one register in the security processor system 23, and therefore, cannot randomly read data or information in the security processor system 23.
In
In
The communication processor 213 in
The speech signal processor 214 in
The security processor 31 is configured to execute security operating system software and at least one security software application based on the security operating system software, where the at least one security software application includes mobile payment software. The security processor can implement mobile payment by executing the mobile payment software. Optionally, the at least one security software application may further include SIM card software application. The SIM card software application includes but is not limited to virtual SIM software or SIM feature software application customized by a communication operator. The security processor 31 equivalently implements the function of the secure element in the prior art, and may further integrate another function, to expand a security application scenario of the system on chip 21. The random access memory 32 is configured to provide storage space used by the security processor 31 to execute the security operating system software and the at least one security software application. The random access memory 32 may be configured to store the security operating system software and the at least one security software application that are loaded, and may be further configured to store secure temporary data generated when the security operating system software and the at least one security software application are executed. After being powered on, the security processor 31 may load the security operating system software and the at least one security software application to the random access memory 32, and execute corresponding software by using internal storage space of the random access memory 32. The secure temporary data is intermediate data, an intermediate operation result, or other information that is related to the security software application or executing of the security software application and that does not need to be stored for a long time, for example, various types of intermediate operation result data or configuration data during operation processing, where the secure temporary data is generated when the security processor 31 executes the security operating system software and the at least one security software application. In this case, the random access memory 32 equivalently implements a memory function of a computer, and is a volatile storage device that may be any one of an SRAM, a DRAM, an SDRAM, or a DDR SDRAM (double data rate synchronous dynamic random access memory). The random access memory 32 is integrated in the system on chip 21. Therefore, the random access memory 32 may use a manufacturing technology the same as that of another component in the system on chip 21. The technology is relatively easy to implement. The security processor 31 may be configured to: guide initialization of another component in the security processor system 23 during a power-on startup process, and load the security operating system software and the at least one security software application to the random access memory 32, to perform a related operation. The security processor 31 may be a processor whose operation speed or implementation complexity is lower than that of the at least one central processing unit 211, but usually has lower power consumption and higher security. For example, the security processor 31 may be a processor of an ARM architecture, or may be another dedicated anti-attack processor, or may be a digital signal processor (DSP).
The security operating system software executed by the security processor 31 may be a chip operating system (COS). The COS is also referred to as a COS image, and may have a function of operating system software in a resident smart card or a financial integrated circuit (IC) card. In this case, the security processor system 23 has functions of a conventional secure element, and the resident smart card or the financial card, and is configured to provide, to an external POS machine, a card reader, or a cloud financial server, data for a mobile payment service such as card swiping, for example, data related to banking and financial services or personal account data of a user such as a personal account, a password, or various types of verification information used by a bank server to verify a personal account. In addition, the COS image may be an operation platform receiving and processing external payment information (for example, various types of payment information sent by the financial server, the card reader, or the POS machine), and may be selectively configured to execute various instructions sent from the outside, for example, an operation such as an authentication operation. The COS is usually designed based on a JAVA computer programming language. The COS may be preset in the security processor system 23, and the mobile terminal 20 may dynamically download and install various types of security software applications, for example, various types of financial software application, based on the COS. A specific design of the COS is content belonging to the prior art, and is not discussed in this application.
In
The multiple interfaces 24 in
In
It should be understood that although this embodiment of the present invention describes the interface 242 by using fingerprint recognition as an example, actually, the interface 242 may be replaced with an interface of another type, for example, an interface configured to transmit iris data, voiceprint data, human face data, or smell data. In this case, the user authentication is not authentication based on fingerprint recognition anymore, but may be based on iris recognition, voiceprint recognition, human face recognition, or smell recognition. A corresponding sensor may be: an iris sensor, a voiceprint sensor, an image sensor configured to acquire a human face image, or a smell sensor. That is, related user identity authentication can be implemented by acquiring particular biometric recognition data of a user, and transmitting the biometric recognition data to the security processor system 23 through a related interface. Certainly, the security processor system 23 may include a biometric recognition input interface supporting all the foregoing types of biometric recognition data, to implement more flexible user identity authentication. The accompanying drawings related to the embodiments are merely schematic drawings. The one or more biometric recognition input interfaces may be SWP interfaces, or certainly, may be interfaces of another type, for example, SPI interfaces or I2C interfaces.
Referring to
The storage interface 245 may be coupled to a security memory 45 outside the system on chip 21, and the storage interface 245 may be an SPI interface or an interface of another type. The security memory 45 may be configured to store the security operating system software and the at least one security software application. Optionally, the security memory 45 includes a memory having enhanced features such as preventing physical and logical attacks, so as to securely store the security operating system software and the at least one security software application. The security processor 31 is configured to: read the security operating system software and the at least one security software application from the security memory 45 by using the storage interface 245, and execute the security operating system software and the at least one security software application. The storage interface 245 is a dedicated interface. The security memory 45 is a processor dedicated to security processing. In this way, the security operating system software and the at least one security software application are both read by using the dedicated storage interface 245 without relying on a TEE of the central processing unit 211, so that higher security can be implemented. The security memory 45 may be an erasable nonvolatile memory, for example, a flash. The security memory 45 is integrated on a second semiconductor chip different from the first semiconductor chip on which the system on chip 21 is located. Because the security memory 45 is dedicated to storing the security operating system software and the at least one security software application, and is not configured to store insecure software, higher security is implemented. Data stored in the security memory 45 is different from intermediate data or temporary data, and can be stored for a long time. On the contrary, temporary data, also known as intermediate data or memory data, stored in the random access memory 32 is process data generated by executing software, does not need to be stored for a long time, and may be lost as a device or an apparatus is powered off. The security processor 31 may load the security operating system software and the at least one security software application from the security memory 45 to the random access memory 32 after the security processor 31 is powered on or based on trigger of a user instruction or another condition. The random access memory 32 provides storage space for executing related software.
Alternatively, with development of a storage technology, the security memory 45 may be replaced with an internal memory in the security processor system 23 in function. The internal memory may be a ROM on chip, or may be an electrically erasable programmable read-only memory (EEPROM) or another nonvolatile memory in chip, is configured to store the security operating system software and the at least one security software application, and is a nonvolatile memory. The internal memory enables the security processor system 23 to store the security operating system software and the at least one security software application without relying on an external memory. The security is high, but higher costs are caused.
In the corresponding system on chip 21 in
In the system on chip 21, under the security isolation, the system bus 210 is coupled to the security bus 35 through the isolation memory 36. That is, the at least one processor located outside the security processor system 23 exchanges data or instructions with the security processor system 23 through the isolation memory 36. In an example, the at least one processor including the central processing unit 211 cannot directly access any component in the security processor system 23 except the isolation memory 36. For example, the at least one central processing unit 211 may be coupled to the security processor system 23 through the system bus 210 and the isolation memory 36 under the action of the general-purpose operating system software, to communicate with the security processor system 23. Content of the communication includes data or an instruction, for example, data is transmitted to at least one element in the security processor system 23. In this case, the isolation memory 36 is a dedicated interaction channel, or even a unique channel, for interaction between the security processor system 23 and the outside, that is, a mailbox channel configured to exchange data or information, so that the at least one processor in the outside is prevented from directly accessing the random access memory 32 or any component or module in the security processor system 23, so as to improve the security.
Preferably, the isolation memory 36 is a volatile memory, for example, a RAM, but may be alternatively replaced with a nonvolatile memory, for example, a ROM. When needing to write data to the security processor system 23, one or more insecurity processors, for example, the central processing unit 211, in the system on chip 21 first write the data to the isolation memory 36, and then notify the security processor 31 in the security processor system 23 by using interrupt or other indication information, and the security processor 31 reads and transfers the data from the isolation memory 36. Reversely, the security processor 31 writes the data or information to the isolation memory 36, and instructs, by using interrupt or other indication information, another processor outside the security processor system 23 to read the data from the isolation memory 36.
Alternatively, the isolation memory 36 used in
By implementing the security isolation by the security isolation device such as the isolation memory 36 or the bus bridge, the at least one processor outside the security processor system 23 cannot randomly access a memory or a register in the security processor system 23. The security processor system 23 may selectively transmit data required to be read by a processor coupled to the system bus 210, to the processor through the security isolation device. Data that the security processor system 23 does not require the processor to obtain is not transmitted to the processor through the security isolation device. For example, the data that the security processor system 23 does not require the processor to obtain may include fingerprint data obtained by using the fingerprint input interface 242, secure temporary data temporarily stored in the random access memory 32, or the security operating system software and the at least one security software application that are loaded to the random access memory 32.
The security processor system 23 and the at least one processor may be coupled through the dedicated transmission channel, to exchange data or instruction, so as to implement the security isolation. The isolation memory 36 or the bus bridge is a form of the dedicated interaction channel. The dedicated interaction channel may be a unique channel coupled between the security processor system 23 and the at least one processor.
The security processor system 23 in
Further, as shown in
Further, the OTP memory 34 in
The security parameter may be programmed in the OTP memory 34, to calibrate, configure, or set the security processor system 23, or close or disable functions of some devices in the security processor system 23. Therefore, the OTP memory 34 makes some internal functions of the security processor system 23 still configurable or changeable after the system on chip 21 is manufactured. This improves design flexibility after the manufacturing is completed. Further, the OTP memory 34 is further configured to store a patch program instruction of the boot program instruction for the initialization of the security processor 31. The patch program instruction may be a supplement to the boot program instruction or a replacement of some programs in the boot program instruction. For example, after the system on chip 21 is manufactured, if it is found that the boot program instruction applied to the security processor system 23 has a deficiency, and information or data in the secure boot memory 33 is not rewritable, in this case, a related patch program instruction may still be programmed in the OTP memory 34 to compensate for the deficiency or an error of the existing boot program instruction, so that implementation is more flexible. When the security processor 31 is started, the security processor 31 may read a part of the programmed patch program instruction from the OTP memory 34, to replace at least one part of the boot program instruction read from the secure boot memory 33. For example, when reading some boot program instructions from the secure boot memory 33, the security processor 31 may jump to the OTP memory 34 to read a related patch program instruction, and may jump back to continue to read other boot program instructions of the secure boot memory 33 when necessary, to implement secure startup.
A person skilled in the art may understand that another security measure may be further added to the OTP memory 34. For example, measures are taken to improve the security, for example, using some security authentication devices to perform authentication on data or information that is read from the OTP memory 34, perform power supply exception detection and alarm on the OTP memory 34, perform read/write exception detection and alarm on the OTP memory 34, encrypt internally read information of the OTP memory 34, or disorder a data storage address in the OTP memory 34. The OTP memory 34 may be a nonvolatile memory.
Because the random access memory 32 in
Further, the security processor system 23 further includes a DMA controller 37 coupled to the security bus 35. The DMA controller 37 is configured to: read data from the random access memory 32, and output the data to the security bus, or write the data to the random access memory 32 by using the security bus. For example, when data needs to be transmitted from the NFC interface to the random access memory 32 through the security bus 35, a related transmission operation may be performed by the DMA controller 37 instead of the security processor 31, so that data read or write efficiency is improved. Therefore, the DMA controller 37 in this embodiment of the present invention plays a role of replacing the security processor 31 to perform data transfer and migration. For a specific operating principle of the DMA controller 37, refer to a description in the prior art, and details are not described herein.
Further, the security processor system 23 further includes an anti-attack system, to improve the security. The anti-attack system may include various anti-attack measures or devices, for example, an anti-attack metal layer 38, and the anti-attack sensor 39. The anti-attack sensor 39 is configured to: detect whether various operating parameters of the security processor system 23 have an exception, generate a trigger signal when the exception occurs, and transmit the trigger signal to the security processor system 23, to trigger at least one of the following operations: the security processor system 23 performs an alarm, the security processor 31 resets, or the random access memory 32 or the at least one register in the security processor system 23 is reset or emptied. Specifically, the operating parameter includes at least one of a voltage, a current, a clock frequency, a temperature, or a laser intensity. Therefore, as shown in
In an implementation, the voltage monitor 61 is configured to: detect whether a voltage of the security processor system 23 or at least one component in the security processor system 23 is normal, and when the voltage is abnormal, report the exception to the security processor 31 or another element configured to receive the exception report in the security processor system 23. An alarm operation is performed by using the security processor 31 or the element. Determining whether the voltage is abnormal by the voltage monitor 61 may include comparing the detected voltage with a voltage threshold, or performing data matching, to determine whether the voltage falls within a normal range or reaches the preset voltage threshold. When the voltage falls within the normal range or does not reach the preset voltage threshold, the exception is not reported, or a normal status is reported. Otherwise, the voltage monitor 61 reports the exception. For example, the voltage monitor 61 may include a detection component (that is, a sensor) configured to sense a voltage and a determining component configured to perform comparison or matching processing. Specifically, when an alarm operation is performed, the security processor 31 or the element may send an alarm instruction to the peripheral interface 244 through the security bus 35, and send an alarm instruction signal to the peripheral device 44 through the peripheral interface 244, to alert the user. Alternatively, the security processor 31 may perform a reset operation after receiving the exception report, or selectively, the security processor 31 or the element may trigger the random access memory 32 or the one or more registers in the security processor system 23 to be reset or emptied. The voltage monitor 61 may recognize a voltage exception caused by an external attack, for example, an external voltage spike attack, and perform a corresponding operation, so as to avoid data or information leakage. Some calibration parameters of the voltage monitor 61 may be stored in the OTP memory 34.
Further, the current monitor 62 is configured to detect whether a current of the security processor system 23 or at least one component in the security processor system 23 is abnormal, and may selectively include a component for detecting the current and a component for determining a current exception, and perform a corresponding operation such as an alarm operation, reset, or empty when the exception occurs, to accurately recognize a current exception caused by an external attack.
The clock frequency monitor 63 is configured to: detect whether a working clock frequency of the security processor system 23 or at least one component in the security processor system 23 is abnormal, and perform a corresponding alarm operation or a reset operation when an exception occurs, and may selectively include a component for detecting the clock frequency and a component for determining a clock frequency exception, to accurately recognize a working clock exception or instability caused by an external attack. Because the clock of the entire system has a complex structure, multi-level frequency multiplication or frequency division is performed on a clock frequency transmitted to the security processor system 23, so that a frequency attack difficulty is increased. Reducing the clock frequency usually makes it easier to apply an attack from the outside, so the outside requires that the clock frequency of the working clock supplied to the security processor system 23 should be located and changed more easily. A complex clock change of the system makes it difficult for an external device to accurately locate a specific clock of the security processor system 23. Therefore, anti-attack detection can be implemented by using the clock frequency monitor 63 to detect a clock related to the security processor system 23. For example, both the working clock of the security processor system 23 and a source clock generating the working clock, that is, a frequency division or frequency multiplication clock of the working clock, may be detected.
Further, a principle of the temperature monitor 64 is similar to that of other detectors mentioned above. The temperature monitor 64 is configured to: detect whether a temperature of the security processor system 23 or at least one component in the security processor system 23 is abnormal, and perform a corresponding alarm operation or reset operation when an exception occurs, and may selectively include a component for detecting the temperature and a component for determining a temperature exception, to recognize an abnormal temperature change caused by an external attack to improve the security. The temperature monitor 64 configured to prevent an attack may be used with another temperature sensor configured to implement heat protection or heat reduction in the system on chip, so as to provide heat protection and further protect the system from being attacked and broken by a low temperature from the outside.
The laser intensity detector 65 is configured to: detect whether a laser signal intensity in the security processor system 23 or in an internal part of the security processor system 23 exceeds a preset threshold to recognize an exception, and perform a corresponding alarm, reset, or empty operation when the exception occurs. The laser intensity detector 65 is mainly configured to prevent an external laser attack. For example, when an external device intrudes the security processor system 23 by using a laser cutting technology, the laser intensity detector 65 can detect a laser signal, or can detect that an intensity of the laser signal exceeds the threshold, and trigger a corresponding operation, for example, the operation such as the alarm, reset, or empty operation described above.
In the anti-attack system in
As shown in
Further, the system bus 210 or the security bus 35 may include at least one of an AHB or an APB. Different parts, elements, or circuits in the security processor system 23 may be further classified into different security levels. Connection is performed by using bus technologies of different levels, so that rate requirements and security requirements of different components in the security processor system can be satisfied. For example, the security bus 35 may use a bus transmission manner of combining the AHB and the APB. Security levels of the AHB and the APB are different, and transmission rates may also be different. For example, a transmission rate of the AHB may be higher than that of the APB, but a security level may be lower than that of the APB. Coupling between different components, for example, between the security processor 31 and a storage system or an anti-attack system may use an AHB technology, while coupling between the security processor 31 and a cipher system 30 uses an APB technology. A specific bus transmission manner may have another implementation, and details are not described herein. Further, to improve the security, data transmitted on the security bus 35 or a related address may be encrypted, scrambled, or subject to a CRC, so as to prevent the related data or address from being cracked from the outside, and ensure privacy and integrity of the data on the security bus 35 and the address. Specifically, when a read/write initiation component (Master) in the security processor system 23 accesses another component (Slave) by using the security bus 35, security processing such as scrambling or interleaving may also be performed on a read/write address of the security bus 35, that is, addresses of the components Master and Slave that occupy the security bus 35.
Further, in
The authentication device 302 is configured to authenticate at least one type of data in the security processor system 23. The authentication may include hash authentication. For example, authentication processing is performed on data exchanged by the security processor system 23 with the outside world through any interface. For example, when any component in the security processor system 23, for example, the security processor 21, needs to write data to the security memory 45, the authentication device 302 performs hash processing on the related data and writes data obtained after the hash processing to the security memory 45. When the security processor 21 needs to read the data from the security memory 45, the data is first sent to the authentication device 302 for performing a hash decryption operation. The data is considered as not intruded or changed only when hash decryption authentication succeeds, and the data is sent to the security processor 21. In this way, the security is ensured. Optionally, the authentication device 302 may be further configured to perform the user authentication based on fingerprint recognition mentioned in the foregoing embodiment.
In
In an optional implementation, the security processor 31 may be further configured to perform the user authentication by using the fingerprint data transmitted by the fingerprint input interface 242. Alternatively, the authentication function may be implemented by another fingerprint authenticator (not shown in the figure) in the security processor system 23. The fingerprint authenticator is equivalent to a hardware accelerator, to implement a higher processing speed and higher security.
In
An embodiment of the present invention provides a system on chip 21 that can support multiple security application services. A security processor system 23 in the system on chip 21 may also be referred to as a security protection module (SPM), and is functionally similar to a secure element in a bank card, but implements higher security and integration. The security of the security processor system 23 may reach the CC EAL4+ (common criteria evaluation assurance level 4+) applied to the financial industry, and the security processor system 23 implements security, reliability, and information privacy protection of various security application products or solutions. Compared with an existing non-integrated solution or low-integration solution, costs are greatly reduced, and complex debugging between chips and layout space on a PCB are not required. In addition, a central processing unit 211 in the system on chip 21 and the security processor system 23 use a totally same integrated circuit manufacturing technology, so that performance is better. In addition, in this solution of this embodiment, multiple external interfaces are integrated in the security processor system 23, and transmission of related data does not rely on a TEE of the central processing unit 211 anymore.
In an implementation, as shown in
In another implementation, as shown in
In an implementation, a schematic flowchart of performing a mobile payment-related method by the system on chip 21 may be shown in
In the foregoing implementations, the communication processor 213 may include a baseband communication processor and an RF processor. In a communication mode, the communication processor 213 may include a cellular communication processor or a short-range communication processor. That is, there may be multiple communication transmission manners or supported communications protocols. The wireless access point may be a WiFi access point, for example, a WiFi router. In this case, the communication processor 213 is a WiFi communication processor. Alternatively, the wireless access point may be a base station, for example, a cellular communication access point supporting GSM, UMTS, WiMAX, TDS-CDMA, CDMA2000, LTE, or 5G. In this case, the communication processor 213 is a cellular communication processor communicating with the access point. The cellular communication access point may be, for example, an LTE base station, for example, an eNodeB. Therefore, the speech signal may be a PS domain speech signal, for example, a VoLTE speech signal. Alternatively, the speech signal may be a CS domain speech signal, for example, a GSM, WCDMA, or CDMA2000 speech signal. In this application scenario, the user may input a voice signal by using an input device, for example, a microphone, and transmit the voice signal to the speech signal processor 214 through a system peripheral interface 215 and the system bus 210. The voice signal is processed by the speech signal processor 214, is transmitted to the cipher system 30 through the system bus 210, an isolation memory 36 (or a bus bridge), and the security bus 35, and is encrypted by the encryption and decryption device 301 in the cipher system 30. Encrypted data is transmitted to the communication processor 213 through the security bus 35, the isolation memory 36 (or the bus bridge), and the system bus 210, so that the communication processor 213 transmits the encrypted data to the wireless access point, to improve the security. Reversely, when receiving an encrypted speech signal sent by the wireless access point, the communication processor 213 may transmit the encrypted speech signal to the encryption and decryption device 301 through a similar signal transmission path. The encryption and decryption device 301 decrypts the encrypted speech signal to obtain speech information, and transmits the speech information to the speech signal processor 214. The speech signal processor 214 processes the signal to obtain the voice signal. The voice signal in this embodiment is an analog speech signal, and may be played to the user by using a loudspeaker, to implement a secure user call function. Alternatively, a decryption function of the encryption and decryption device 301 may be implemented by the security processor 31.
In an implementation,
After acquiring the fingerprint data, the fingerprint sensor 42 may trigger the security processor 31 to perform a corresponding authentication operation. The security processor 31 may be triggered to obtain the pre-stored fingerprint data from an external memory, for example, like in
As shown in
It can be understood that all or some steps of the method or procedure that is performed by software and that is used in each embodiment of the present invention may also be implemented in a form of a software functional unit and sold or used as an independent product. The related software functional unit may be a computer program product, or may be stored in a computer readable storage medium. The computer program product may include all or some of the general-purpose operating system software, the common software application based on the general-purpose operating system software, the security operating system software, and the at least one security software application based on the security operating system software that are mentioned in the previous embodiments. Based on the understanding, at least one part of a technical solution corresponding to the method may be embodied in a form of computer code. The computer code may be stored in a storage medium, and includes several instructions used to enable a computer device (which may be the mobile terminal mentioned above, or a personal computer) to perform all or some steps of the corresponding method. The foregoing storage medium includes: any medium that can store program code, such as a USB flash drive, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc.
It can be understood that a typical application scenario of the mobile terminal 20 mentioned in the embodiments of the present invention may be a mobile phone, for example, various smartphones. Each component in the system on chip 21, for example, the at least one processor or the security processor system 23, may include multiple transistors or logic gate circuits, and may operate under driven by necessary software. Alternatively, some devices, for example, which may be a pure hardware accelerator, may selectively operate without software.
It should be noted that the mobile payment in the embodiments of the present invention is a generalized definition, and includes both a commercial or financial mobile payment service and a payment service of another type, for example, public transport, an identity card, or a social security card. That is, by means of mobile payment, a mobile terminal may be connected to a communication peer, to finally exchange payment information with a server, and to implement a data transaction, data redemption, or data settlement associated with one or more accounts in the mobile terminal. In addition to currency, a unit of a data transaction, redemption, or data settlement may also be another unit that can be used to implement payment, redemption, or transaction settlement, for example, virtual currency, various types of bonus points or a line of credit. This is not limited in this embodiment. The account includes but is not limited to a personal account, a group account, or an organization account. Compared with a payment behavior implemented only on a fixed terminal, implementation of the mobile payment is more flexible. The mobile payment is executed by the mobile terminal 20 shown in
It should be noted that the system on chip 21 mentioned in the embodiments of the present invention is applied to a mobile terminal 20, but actually, may also be applied to another processing device not having a mobile communication function, for example, a handheld device not having a mobile communication capability. Therefore, functions of some devices or units in the system on chip 21 mentioned in the embodiments of the present invention are not necessary. For example, the at least one processor may be omitted. For example, one or more of the graphics processing unit 212, the communication processor 213, the speech signal processor 214, the system peripheral interface 215, the image signal processor 217, or the like may be selectively omitted. The central processing unit 211 or the system power management unit 216 may also be omitted and replaced with a control circuit having simpler functions and design. Therefore, a form of a related processing device including the system on chip 21 is not limited.
The foregoing are merely example embodiments of the present invention. A person skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. For example, specific shapes or structures of components in the accompanying drawings in the embodiments of the present invention may be adjusted according to an actual application scenario.
This application is a continuation of International Application No. PCT/CN2016/094226, filed on Aug. 9, 2016, the disclosure of which is hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2016/094226 | Aug 2016 | US |
| Child | 16268294 | US |
