Patent Application
20070019317
The present invention relates to Hard Disk Drives (“HDD”) and more particularly, to a novel partitioning of the analog and digital functions that are used in hard disk drive integrated chip sets and associated circuit boards.
Hard disk drives typically include at least three integrated circuits. The essential analog and digital functions comprising the hard disk drive are distributed amongst the three integrated circuits. One of the integrated circuits is usually an analog integrated circuit including a preamplifier. Another of the integrated circuits is also analog and includes a motor controller. At least one of the integrated circuits in a typical hard disk drive chip set is usually a “mixed signal”, “system on a chip” integrated circuit that includes both a plurality of both digital and analog functions, such as read channels and a hard disk controller.
The problem with the mixed signal integrated circuit is that this leads to an inefficient use of process technology. Although it is certainly possible to integrate digital and analog functions on the same chip with the same process technology, these process technologies are more expensive and problematic that other process technologies that are suited only for analog circuits (BiCMOS) or digital circuits (CMOS). Further, the use of one or more mixed signal integrated circuits in the chip set can add to the component count and to the cost of the overall system.
In general, the challenge for a desirable hard disk drive chip set is how to achieve high speed and low dynamic and static power dissipation to enable “system on a chip” integration and how to minimize the number of integrated circuits and hard disk drive printed circuit boards for resource optimization and to further reduce power dissipation.
What is desired, therefore, is a more efficient partitioning of the analog and digital functions in a hard disk drive chip set.
According to an embodiment of the present invention, a hard disk drive chip set includes an analog chip including all of the analog functions for the hard disk drive except for a motor controller, and a digital chip including all of the digital functions for the hard disk drive including a plurality of read channels. The analog chip is implemented in a BiCMOS process and includes read path amplification including a variable gain amplifier, reference and bias circuitry, thermal asperity control and magneto resistivity asymmetry compensation circuitry, as well as other analog functions. The digital chip is implemented in a CMOS process and includes an analog-to-digital converter, a servo processor circuit, and a hard disk controller. Each of the read channels in the digital chip include an FIR filter, an ITR circuit, and a Viterbi detector.
According to another embodiment of the present invention, a hard disk drive includes the analog chip including all of the analog functions for the hard disk drive except for a motor controller on a first circuit board, and the digital chip including all of the digital functions for the hard disk drive including a plurality of read channels, an external memory, and a motor controller on a second circuit board. The first circuit board can be a flexible circuit board, if desired. The second circuit board can be a printed circuit board physically coupled to a hard drive. The analog chip and the digital chip are coupled to each other with a multi-wire connector. The digital chip is coupled to a hard drive with a ribbon cable. The analog chip is coupled to a head of a hard drive.
In another embodiment, the motor controller functions are divided into analog and digital functions and absorbed into the first, analog chip and the second, digital chip.
The aforementioned and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of a preferred embodiment taken in conjunction with the accompanying drawings, wherein:
Referring now to
Referring now to
Analog chip 202 includes analog control logic 210, which is a plurality of registers for setting gain and cutoff frequencies in the preamplifiers 214 and 216, and other control functions. The control logic block 210 can be designed using bipolar, CMOS, or BiCMOS logic. Variable current sources I1 and I2 are coupled to the read head terminals for biasing. The read head 214 is capacitively coupled to the analog chip 202 through capacitors C1 and C2. A preamplification chain 214, 216 includes amplifiers A1 and A2, as well as variable gain amplifier 218. The output of the variable gain amplifier 218 is coupled to block 220, which includes the thermal asperity control and magneto resistivity asymmetry control functions for compensating for thermal variations and variations in the magnetic element of the hard disk. The output of block 220 is coupled to a low pass filter 224, which can be implemented using bipolar, CMOS, or BiCMOS design techniques. An automatic gain control block 212 is coupled to the variable gain amplifier 218, as well as to the outputs of the low pass filter 224. The automatic gain control block 212 is used to adjust the amplitude of the input signal of a given target and can be implemented using bipolar, CMOS, or BiCMOS design techniques. A reference/bias block 226 provides reference voltages and bias currents for amplifiers A1 and A2, as well as the heater element 230 and write bridge 232, which are described in further detail below. A microprocessor interface block 228 receives digital signals from the digital chip and converts these signals into analog voltages and currents for controlling the reference/bias block 226, the variable gain amplifier 218, block 220, and the low pass filter 224. The microprocessor interface block 228 can be implemented using bipolar, CMOS, or BiCMOS design techniques. An optional heater 230 can be coupled to the write head 276. The input of the heater 230 is coupled to a current generator (not shown in
Digital chip 204 includes capacitors C3 and C4 for capacitively coupling the output of the low pass filter 224 from the analog chip 202 through transmission lines 236. A buffer 238 supplies the signal to a plurality of analog-to-digital converters 240. A frequency synthesizer 244 receives a signal from the off-chip crystal 280, and provides a clock signal to the analog-to-digital converters 240 and to the write pre-compensation block 246. The write pre-compensation block is used to adjust a transition spacing signal before it is written to the disk. The output of the analog-to-digital converter block 240 is coupled to a collector (memory) 242, which is in turn coupled to a plurality of read channels 248. While only three channels are shown, any number may be used. Each of the channels is selectable so that the final chip set can be customized to work in a wide range of different applications, substantially reducing the number of dedicated chip sets that would otherwise have to be created. Each read channel 248 includes a Finite Input Response filter (“FIR”) 250, an Interpolating Timing Recovery (“ITR”) block 252, and a Viterbi algorithm block 254. The output of the analog-to-digital converter block 240 is also directly coupled to a servo processor block which also includes an FIR filter 258, ITR block 260, as well as a demodulator block (“DMOD”) 262.
Further digital processing is provided in digital chip 204 by a hard disk controller (“HDC”) 264, a microcontroller (“μC”) 266, and an interface block 268 (“Multi-Interface PHYsical”). Interface block 268 communicates with the user via digital bus 270. Still further digital processing is provided by microcontroller 272, as well as memory block 274. The first microcontroller 266 and second microcontroller 272 are used to control all of the digital functions on the chip including retrieval of data and interfacing. While two microcontrollers are shown, any number can be used and the digital functions distributed between the microcontrollers as desired.
While an embodiment of the present invention has been shown and described, it will be apparent to those skilled in the art that there are many further changes that could be made if desired for a specific application. For example, the digital chip could or could not contain the analog-to-digital converters depending on board layout constraints and/or selected process technology features. The analog chip could embed a time base generator (PLL) as well as some of the servo control logic for different system implementations. The present invention is not limited by the final interface chosen, as this could be analog (i.e. Serial ATA) or digital (i.e. ATA) in nature. Typically, the HDD electronics reside on a Flex Board (Preamplifier) and a PCBA (SOC/Motor Controller/connector). In other implementations, depending on the sizes of components and size of the HDD electronics, all of the electronics could be assembled on a single board (Flex or PCBA) or a different partitioning could be used.
While there have been described above the principles of the present invention in conjunction with specific components, circuitry and bias techniques, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
