S.D. Rao et al., An Approach to Scheduling and Allocation using Regularity Extraction, 4th European Conference on Design Automation, pp. 557-561, Feb. 1993. |
A. Chowdary et al., A General Aproach For Regularity Extraction of Datapath Circuits, International Conference on Computer-Aided Design, pp. 332-339, Nov. 1998. |
A Chowdhary et al., Extraction of Functional Regularity in Datapath Circuits, IEEE Transactions on Computer-Aided Design, pp. 1279-1296, Sep. 1999. |
S.R. Arikati and R. Varadarajan. "A Signature Based Approach to Regularity Extraction". In Proceedings of International Conference on CAD, pp. 542-545, Nov. 1997. |
A. Chowdhary and J.P. Hayes. "Technology Mapping for Field-Programmable Gate Arrays Using Integer Programming". In Proc. Int'l. Conf. on CAD, pp. 346-352. Nov. 1995. |
M.R. Corazao, et al. "Performance Optimization Using Template Mapping for Datapath-Intensive High-Level Synthesis". IEEE Trans. on CAD, 15(8): 877-888. Aug. 1996. |
D.W. Dobberpuhl. "Circuits and Technology for Digital's StrongARM and ALPHA Microprocessors". In Proc. Conf. on Advanced Research in VLSI, pp. 2-11, Sep. 1997. |
E. Detjens et al. "Technology Mapping in MIS". In Proc Int'l Conf. on CAD, pp. 116-119, 1987. |
R. Gupta and S. Liao. "Using a Programming Language for Digital System Design". IEEE Design and Test of Computers, pp. 72-80, Apr. 1997. |
M.C. Hansen and J.P. Hayes. "High-Level Test Generation Using Physically-Induced Faults". In Proc. VLSI Test Symp., pp. 20-28, May 1995. |
M. Hirsch and D. Siewiorek. "Automatically Extracting Structure From a Logical Design". In Proc. Int'l. Conf. on CAD, pp. 456-459, Nov. 1988. |
K. Keutzer. "Dagon: Technology Binding and Local Optimization by DAG Matching". In Proc. 24th Design Automation Conf., pp. 341-347, Jun. 1987. |
J. Li and R. Gupta. "HDL Code Restructuring Using Time Decision Tables". In Proc. 6th Int'l Workshop on Codesign, pp. 131-135, Mar. 1998. |
G. Odawara, T. Hiraide, and O. Nishina. "Partitioning and Placement Technique for CMOS Gate Arrays". IEEE Trans. on CAD, 6(3): 355-363, May 1987. |
J.M. Rabaey, C. Chu, P. Hoang and M. Potkonjak. "Fast Prototyping of Datapath-Intensive Architectures". IEEE Design and Test of Computers, pp. 40-51, Jun. 1991. |
D. S. Rao ad F.J. Kurdahi. "On Clustering for Maximal Regularity Extraction". IEEE Trans on CAD, 12(8): 1198-1208, Aug. 1993. |
H. Yalcin, J.P. Hayes, and K.A. Sakallah. "An Approximate Timing Analysis Method for Datapath Circuits". In Proc Int'l Conf. on CAD, pp. 114-118, Nov. 1996. |
R.X.T. Nijssen and C.A.J. van Eijk. "Regular Layout Generation of Logically Optimized Datapaths". In Proc. Int'l Symp. on Physical Design. pp. 42-47, 1997. |
R.X.T. Nijssen and C.A.J. van Eijk. "A Methodology For Utilizing Datapath Regularity in Stand Design Flows". In Integration the VLSI Journal 25, pp. 111-135, 1998, 11/1. |