Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation

Abstract

In an embodiment of the invention, a method comprises: fetching a first set of descriptors from a memory device and writing the first set of descriptors to a buffer; retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation; and if space is available in the buffer, fetching a second set of descriptors from the memory device and writing the second set of descriptors to the buffer during or after the processing of the first set of descriptors. In another embodiment of the invention, an apparatus comprises: a fetching module configured to fetch a first set of descriptors from a memory device and to write the first set of descriptors to a buffer; a sequencer configured to retrieve the first set of descriptors from the buffer and to process the first set of descriptors to permit a Direct Memory Access (DMA) operation; and wherein if space is available in the buffer, the fetching module is configured to fetch a second set of descriptors from the memory device and to write the second set of descriptors to the buffer during or after the processing of the first set of descriptors.

Description

FIELD

Embodiments of the invention relate generally to the acquisition of data wherein a usage of descriptors is formulated to handle the operations of Direct Memory Access (DMA) Engines in a system and/or in a network.

DESCRIPTION OF RELATED ART

The background description provided herein is for the purpose of generally presenting the context of the disclosure of the invention. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against this present disclosure of the invention.

In some conventional systems, a descriptor management system is formulated to store the descriptors in a shared memory and accessed by a single processor or by multiple processors. A single sequencer or a descriptor management unit is used to fetch the descriptors from the shared memory to the processor. Examples of descriptor management systems are disclosed, for example, in U.S. Pat. No. 6,963,946 which discloses descriptor management systems and methods for transferring data between a host and a peripheral, and in U.S. Patent Application Publication No. 2005/0080952 which discloses descriptor-based load-balancing systems.

However, these types of descriptor management systems are only able to optimize the usage of a single sequencer unit to work with the fetching of the descriptors from memory to the host processor and host 10 (input/output interface). The lone sequencer unit will become a bottleneck to the optimization of the operation of the host processor(s).

SUMMARY

One or more embodiments of the invention relates to the acquisition of data wherein a method of usage of descriptors is formulated to handle the operation of Direct Memory Access (DMA) Engines in a system and/or in a network. An embodiment of the invention is able to optimize the usage and communication between a plurality of Flash DMA engines which, in turn, minimizes the load of processor operation for multiple accesses to a peripheral device and/or memory and overcomes the issue on processor transactions versus time. Multiple accesses are also described, for example, in commonly-owned and commonly-assigned U.S. patent application Ser. No. 14/217,249 which is entitled SCATTER-GATHER APPROACH FOR PARALLEL DATA TRANSFER IN A MASS STORAGE SYSTEM and in commonly-owned and commonly-assigned U.S. Patent Application No. 61/980,628 which is entitled SCATTER-GATHER APPROACH FOR PARALLEL DATA TRANSFER IN A MASS STORAGE SYSTEM.

In an embodiment of the invention, the multiple DMA engines paved a way to a new concept of using a descriptor pipeline system flow and inter-descriptor concurrent transactions from the memory to the DMA engines. Each of the DMA Engines has its own respective slot in the shared memory and has its own respective fetching module. This aforementioned memory slot is filled up with a number of descriptors hierarchically organized into groups. These descriptors can also be systematically fetched, linked, queued, and/or even aborted on-the-fly by both its corresponding fetching module and/or its corresponding DMA engine.

According to an embodiment of the invention, in cases of concurrent operations, interlinking information between descriptor groups within a single engine and across other descriptor groups of another DMA engine is provided. Such feature also provides a flow control in the concurrency of the operations and interaction between DMA engines.

Flash Intelligent DMA engines are activated via descriptors that determine the operation(s) of the flash intelligent DMA engines. These descriptors are organized in a hierarchical manner according to the usage of the descriptor(s) in a specific operation. A series of descriptors words are bundled together to form a single descriptor queue and each descriptor queue are linked together to form a descriptor queue group.

One embodiment of the invention includes flash Intelligent DMA engines. In general, a descriptor is simply a command. Hence, an embodiment of this invention also applies to other kinds of cores as long as said cores receive commands, and not limited to just DMA engines (e.g., core=CPU, software modules, etc.).

In an embodiment of the invention, the descriptors are loaded into the DMA engine in two ways: (1) direct loading of the descriptors into the DMA engine via memory writes from a processor core, and/or (2) DMA engine pre-fetching of the descriptors. Pre-fetch performed by a DMA engine is done in two ways: (1) Fixed Addressing—The normal priority descriptor groups can be written in a fixed position in memory where the DMA engine can continuously pre-fetch (via DMA reads) the succeeding descriptors; and/or (2) Linked List Addressing—The descriptor has a linked list structure that allows continuous pre-fetch of succeeding descriptors across different positions in memory. In an embodiment of the invention, the descriptor also employs tagging that allows monitoring which descriptor is pending, in-service, and done (wherein a descriptor has the status of done when a DMA engine has already executed the descriptor and performed the DMA operation by executing the descriptor).

These descriptors can be set up and updated continuously on the fly by adding into the linked list or the fixed memory descriptor locations. Descriptors are then loaded and executed by the DMA engine with minimal processor intervention.

In an embodiment of the invention, the high priority descriptor can be set up using a fixed addressing method. When present, the high priority descriptor can sneak in during execution of the normal priority descriptors.

In an embodiment of the invention, a method comprises: fetching a first set of descriptors from a memory device and writing the first set of descriptors to a buffer; retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation; and if space is available in the buffer, fetching a second set of descriptors from the memory device and writing the second set of descriptors to the buffer during or after the processing of the first set of descriptors.

In another embodiment of the invention, an apparatus comprises: a fetching module configured to fetch a first set of descriptors from a memory device and to write the first set of descriptors to a buffer; a sequencer configured to retrieve the first set of descriptors from the buffer and to process the first set of descriptors to permit a Direct Memory Access (DMA) operation; and wherein if space is available in the buffer, the fetching module is configured to fetch a second set of descriptors from the memory device and to write the second set of descriptors to the buffer during or after the processing of the first set of descriptors.

In yet another embodiment of the invention, an article of manufacture, comprises: a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: fetching a first set of descriptors from a memory device and writing the first set of descriptors to a buffer; retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation; and if space is available in the buffer, fetching a second set of descriptors from the memory device and writing the second set of descriptors to the buffer during or after the processing of the first set of descriptors.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one (several) embodiment(s) of the invention and together with the description, serve to explain the principles of the invention.

BRIEF DESCRIPTION OF DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the present invention may admit to other equally effective embodiments.

FIG. 1 is a block diagram illustrating a data storage system comprising a descriptor queuing system (descriptor queuing apparatus) including components used in a Direct Memory Access (DMA) Engine operation according to an embodiment of the invention.

FIG. 2 is a chart diagram representation of an organization of the descriptors in a memory device according to an embodiment of the invention.

FIG. 3 is a block diagram illustrating a structure of a single descriptor queue Group (DQG) and the basic partitions of a single unit of a DMA Descriptor Queue (DQ) which handles the operation of a DMA engine according to an embodiment of the invention.

FIG. 4 is a block diagram illustrating a method of continuous transfer of DQGs from the memory stack to the buffer using a pre-fetching module according to an embodiment of the invention.

FIG. 5 is a flow chart diagram of an algorithm on the continuous pre-fetching process of the DQGs according to an embodiment of the invention.

FIG. 6a and FIG. 6b are detailed diagrams on the stages of manipulating the DQGs including the transfer from the buffer to the sequencer, the sequencer mechanism of handling the DQGs, and the execution of the DQGs to perform the operation on a single DMA Engine according to an embodiment of the invention.

FIG. 7 is diagram of an algorithm on the manipulation of the DQGs from the alteration of the sequence of DQGs to the execution of these descriptors according to an embodiment of the invention.

FIG. 8 is a block diagram illustrating a linking mechanism according to an embodiment of the invention.

DETAILED DESCRIPTION

In the following detailed description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the various embodiments of the present invention. Those of ordinary skill in the art will realize that these various embodiments of the present invention are illustrative only and are not intended to be limiting in any way. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefit of this disclosure.

In addition, for clarity purposes, not all of the routine features of the embodiments described herein are shown or described. One of ordinary skill in the art would readily appreciate that in the development of any such actual implementation, numerous implementation-specific decisions may be required to achieve specific design objectives. These design objectives will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine engineering undertaking for those of ordinary skill in the art having the benefit of this disclosure. The various embodiments disclosed herein are not intended to limit the scope and spirit of the herein disclosure.

Exemplary embodiments for carrying out the principles of the present invention are described herein with reference to the drawings. However, the present invention is not limited to the specifically described and illustrated embodiments. A person skilled in the art will appreciate that many other embodiments are possible without deviating from the basic concept of the invention. Therefore, the principles of the present invention extend to any work that falls within the scope of the appended claims.

As used herein, the terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items.

An embodiment of the invention relates to the acquisition of data wherein a method of usage of descriptors is formulated to handle the operation of Direct Memory Access (DMA) Engines in a system and/or in a network. An embodiment of the invention can optimize the usage and communication between a plurality of Flash DMA engines which, in turn, minimizes the load of processor operation for multiple accesses to a peripheral and/or memory and overcomes the issue on processor transactions versus time.

FIG. 1 is a block diagram illustrating a data storage system 160 comprising a descriptor queuing system 162 (descriptor queuing apparatus 162) according to an embodiment of the invention. The system 162 (apparatus 162) comprises components used in a Direct Memory Access (DMA) Engine operation according to an embodiment of the invention.

In order to maximize the usage of the flash devices, a plurality of DMA engines 106˜107 (i.e., DMA engines 106 through 107) are installed. Given the N number of DMA engines (wherein N is an integer), a systematic queuing method of command descriptors is formulated to control the operation of these DMA engines. The DMA engines (and corresponding flash controllers and flash device arrays) can each vary in number as in noted by, for example, the dot symbols 150. In other embodiments, the number of fetching modules is not necessarily equal to the number of DMA engines. Sometimes multiple DMA engines share a single fetching module. Sometimes, a single DMA engine can have multiple fetching modules, wherein each fetching module fetches a different set/linklist/group of descriptors.

In one embodiment of the invention, the system 160 comprises seven (7) major components which are shown as: (a) V number of Flash Device Arrays 100˜101 arranged to allow progressive expansion of the flash devices in an array manner, wherein V is an integer and, by way of example and not by way of limitation, the flash device array 100 comprises flash devices 1˜4 (i.e., flash devices 1, 2, 3, and 4) and flash device array 101 comprises flash devices V-4, V-3, V-2, and V-1; (b) Y number of Flash Controllers 102˜103, with each flash controller controlling its own respective array of Flash Devices; (c) A plurality of processors 139˜141 (processors 139, 140, and 141) responsible for the creation of the descriptors; (d) Several Memory Banks 128, 129, and 130 where the descriptors 133˜135 (descriptors 133, 134, and 135) are written by a plurality of processors; (e) a plurality of buffers from buffer [0] 114 to buffer [N−1] 115 which temporarily stores the descriptors 116˜117, wherein each of the descriptors corresponds to one DMA engine 106 via DMA-Buffer Bus [0] 112 or to another DMA engine 107 via DMA-Buffer Bus [N−1] 113; (f) a plurality of Fetching modules from Fetching Module [0] 121 to Fetching Module [N−1] 122, equal to the number of DMA engines, are responsible for the optimized transfer of the Descriptor Queues 133, 134, and 135 from the Memory banks 128, 129, and 130, respectively, to the Buffers 114˜115 via a System Bus 125 of a different protocol; and (g) a plurality of DMA Engines 106˜107 responsible for the organization of the Descriptor Queue Groups 116˜117 and execution of these descriptor queue groups 116 and 117.

The number of DMA engines corresponds to the optimization of the usage of a Flashbus protocol or other bus IO standard protocol (e.g., PCIe) 104˜105 and the plurality of Flash device controllers 102˜103 that handles stacks of flash devices in the flash device arrays 100˜101.

The descriptors 133, 134, and 135 are created by a plurality of processors and written by the processors into the memory banks 128, 129, and 130, respectively. The descriptors may vary in number as noted by, for example, the dot symbols 151. These memory banks 128, 129, and 130 can be an SDRAM or an SRAM or any other device of similar architecture. A single Memory bank piles up an M number of words 131 (where M is an integer) and each word is equal to an N-byte sized Descriptor Queue 132. On the other side of the memory banks, Fetching modules 121˜122 are installed and can initially transfer these descriptors 133˜135 from any of the memory banks 128, 129, and 130 to the Buffers 114˜115 via the System Bus 125. For example, the fetching module 121 transfers the descriptors from memory bank 128 via bus interface 126 and system bus 125 and bus interface 123 and to the buffer 114 via bus 118. The fetching module 122 transfers the descriptors from memory bank 130 via bus interface 127 and system bus 125 and bus interface 124 and to the buffer 115 via bus 119. Another fetching module (not shown in FIG. 1) similarly transfers the descriptors from memory bank 129 via bus interfaces and system bus 125 to a buffer (not shown) between the buffers 114 and 115.

For a faster and direct accessibility of the descriptors to be used by a plurality of DMA engines, a buffer is installed per DMA engine. The command descriptors 133, 134, and 135 scattered in the memory bank are initially transferred by the fetching modules 121˜122 to its respective buffers 114˜115 where these descriptors could later be retrieved by the DMA Engine that owns the respective buffer. In the example of FIG. 1, the DMA engines 106 and 107 owns the buffers 114 and 115, respectively.

These descriptors, once accessed and read by the DMA engine, undergo certain stages of dissection before the descriptors can fully be used in controlling the DMA engines. The sequencers 110˜111 (descriptor management units 110˜111) are found internally in each of the DMA engines 106˜107, respectively, and the DMA engines ensure that these descriptors are properly organized before the descriptors are executed. The DMA engines then translate the descriptors to several Flash operations by the DMA Interfaces 108˜109 and received by the Flash Controllers 102˜103 via the Flash Buses 104˜105. These Flash Controllers 102˜103 then directly manages the activation of the Flash Devices in the flash device arrays 100˜101 and performs monitoring of the operations of the respective flash array that is managed by the corresponding flash controller.

As shown in the illustration in FIG. 1, a control and status line 120 is connected to the processors 139, 140, and 141, fetching modules 121˜122, buffers 114˜115, and DMA Engines 106˜107. These lines 120 are used in order for the fetching modules 121˜122 to communicate, monitor, and perform message passing to each other.

It is also noted that the processors 139, 140, and 141 perform memory transactions (e.g., writes and reads) 136, 137, and 138, respectively, on any of the memory banks 128, 129, and 130.

FIG. 2 is a chart diagram illustrating a hierarchical representation 250 of the Descriptors (or organization 250 of the descriptors) in a Memory Device 200 with multiple Memory Banks 201, 202, and 203, according to an embodiment of the invention. The memory banks in a memory device can vary in number as noted by, for example, the dot symbols 251.

Each memory bank comprises a plurality of Descriptor Links arranged from the highest priority to be fetched and serviced to the lower priorities for fetching and servicing. As illustrated in the example of FIG. 2, the memory bank [0] 201 comprises Descriptor Link 204 with priority [0], Descriptor Link 205 with priority [1], and up to Descriptor Link 206 with priority [j−1] 206, wherein j is an integer and wherein the order of the highest priority to lowest priority is priority [0], priority [1], and priority [j−1]. The descriptor links in a memory bank can vary in number as noted by, for example, the dot symbols 252.

Each Descriptor Link comprises a plurality of Descriptor Queue Groups (DQGs). For example, descriptor link 204 comprises Descriptor Queue Group [0] 207, Descriptor Queue Group [1] 208, and up to Descriptor Queue Group [k−1] 209, wherein k is an integer. The descriptor queue groups in a descriptor link can vary in number as noted by, for example, the dot symbols 253.

Each Descriptor Queue Group comprises an n number of Descriptor Queues (DQs), wherein n is an integer. For example, Descriptor Queue Group [0] 207 comprises Descriptor Queue [0] 210, Descriptor Queue [1] 211, and up to Descriptor Queue [n−1] 212. The descriptor queues in a descriptor queue group can vary in number as noted by, for example, the dot symbols 254. A single Descriptor Queue Group mainly handles one DMA operation with its Descriptor Queues describing the details required to complete the DMA operation of a DMA engine.

FIG. 3 is a block diagram illustrating a structure of a single descriptor queue Group (DQG) 300 and the basic partitions of a single unit of a DMA Descriptor Queue (DQ) which handles the operation of a DMA engine according to an embodiment of the invention. Examples of DQGs are also shown in FIG. 2 as DQGs 207, 208, and 209.

In the example of FIG. 3, the DQG 300 comprises an n number of Descriptor Queues 304, 309, . . . , 314, and 320. The descriptor queues in a descriptor queue group can vary in number as noted by, for example, the dot symbols 354. Therefore, there can be additional descriptor queues (not shown) between the descriptor queues 309 and 314, or the number of descriptor queues in DQG 300 can be less than four descriptor queues.

A DQG 300 contains a Descriptor Group Tag Number 301 used for as a reference in tracing the Descriptor Queue Group. This is also useful in abort and/or suspend or recovery stages of the Descriptor Queue Group monitored by the processor. A DQG 300 also contains the sequence information 302 which includes the Fetching priority number and the DMA engine service priority number which is used by the DMA engine to trace and re-arrange the service priority sequence of this descriptor queue group along with other descriptor queue groups in a Descriptor Link. This sequence information 302 can be dynamically changed by the processor in the buffer or other buffer memory components while the sequence information 302 is still queuing for the DMA engine. The Group Link Information 303 basically describes how the current descriptor queue Group is linked to the next DQG as well as providing information for monitoring the status of the preceding DQG. The Group Link Information 303 can also be used to determine whether the DQG 300 is linked to another DQG of the same descriptor Queue Link (e.g., descriptor link 204) or a different descriptor Queue Link within a single DMA engine or across a plurality of DMA engines. Descriptor queue links are also shown in FIG. 2 as example descriptor link 204 (with a first priority [0]), descriptor link 205 (with a second priority [1]), and up to descriptor link 206 (with another priority [j−1]). Other descriptor queue link information includes the atomic linking (see FIG. 8) wherein an injection of a high priority descriptor Queue Group(s) could not break the chain of Descriptor Queue Groups but rather waits for the whole descriptor queue link to be processed and stops the processing of the next set of linked descriptors.

Each Descriptor Queue 304, 309, . . . , 314, and 320 contains the four basic information: (1) Descriptor Address 308, 313, . . . , 318, 324, respectively, which are each the Memory bank address or the Buffer Address depending on where the descriptor is initially written; (2) Link information 307, 312, . . . , 317, 323, respectively, which contain the address of the next Descriptor that the descriptor is linked to as well as the preceding descriptor information and next Descriptor information and which DMA engine that will process the descriptor; (3) The Control Information 305, 310, . . . , 315, 321, respectively, which manipulate the basic operations of the DMA Engine, and (4) the configuration of the descriptor 306, 311, . . . , 316, 322, respectively, which determine whether the descriptor is used as a command or status descriptor as well as whether the descriptor is dynamically altered by software or hardware and whether the descriptor queue is aborted or suspended on-the-fly by the processor or the DMA engine itself.

FIG. 4 is a block diagram illustrating a method of continuous transfer of DQGs from the memory stack to the buffer using a pre-fetching module (fetching module 401) according to an embodiment of the invention. This block diagram shows exemplary illustrations of the descriptor link structure during a single DMA descriptor pre-fetching from the Memory Device to the DMA Buffer. To show the method in a simplified manner, FIG. 4 illustrates a sample setup comprising the following components, wherein at least some of the following components are also similarly illustrated in FIG. 1: (a) a processor 400; (b) a memory device 402; (c) a couple of memory banks 410˜411; (d) a single fetching module 401; (e) a buffer interface 409; (f) a singular buffer 403; and (g) multiple descriptor queue groups (DQGs) 413˜414. The processor 400 initially writes the details of each of the descriptors in a Memory Bank 410˜411 with different fetching priorities via the bus 406 and via the Memory Interface 412. The Control and Status lines 407˜408 are used as communication lines between the processor 400 and the Buffer interface 409 and the Fetching module 401. For example, the processor 409 transmits a processor fetch signal 450 via control and status line 408 to inform the fetching module 401 about the next set of descriptors to be fetched by the fetching module 401 from the memory banks of memory device 402. Given the information in each of the DQG 413˜414, as previously discussed above with reference to FIG. 3, the fetching module 401 continuously snoops at the Descriptor Queue Group Sequence information 302 and then performs the transfer process referring to the aforementioned information 302. A single fetching module 401 can concurrently or sequentially perform the transfer from different memory banks 410 and 411 via the Memory Busses 404 and 405 to the buffer 403. The Fetching movement relies on the Link Information forming sets of Descriptor Links; in FIG. 4, Memory bank 0410 has a 1^st priority Descriptor Queue Links 415, 416, 417, and 418 (DQL Priority 0) and Memory Bank 1411 has a 2^nd priority Descriptor Links 419, 420, and 421 (DQL Priority 1). The final stage of the fetching process is when the Descriptor Links (e.g., links 415˜418 and 419˜421) are successfully copied as links 422 and 423 in the buffer 403. Note that this process is not limited to the simplified setup and therefore can be replicated independently for multiple DMA engines as similarly discussed below with reference to FIG. 8.

In the example of FIG. 4, the descriptor link 415 comprises the connection _from_— descriptor queue group G2 _to_— G5 in memory bank 410.

The descriptor link 416 comprises the connection _from_— descriptor queue group G5 _to_— G10 in memory bank 410.

The descriptor link 417 comprises the connection _from_— descriptor queue group G10 _to_— G1 in memory bank 410.

The descriptor link 418 comprises the connection _from_— descriptor queue group G1 _to_— G3 in memory bank 410.

The descriptor link 416 comprises the descriptor queue groups G5, G6, G7, G8, G9, and G10 in memory bank 410.

The descriptor link 417 comprises the descriptor queue groups G1, G2, G3, G4, G5, G6, G7, G8, G9, and G10 in memory bank 410.

The descriptor link 418 comprises the descriptor queue groups G1, G2, and G3 in memory bank 410.

The descriptor link 419 comprises the connection _from_— descriptor queue group G0 _to_— G2 in memory bank 411.

The descriptor link 420 comprises the connection _from_— descriptor queue group G2 _to_— G1 in memory bank 411.

The descriptor link 421 comprises the connection _from_— descriptor queue group G1 _to_— G10 in memory bank 411.

FIG. 5 is a flow chart diagram of an algorithm 550 on the continuous pre-fetching process of the DQGs according to an embodiment of the invention. This fetching process 550 is performed by a Pre-fetching module (e.g., pre-fetching modules 121 or 401).

Reference is now made to FIGS. 4 and 5. At 500, the software represented (or executed) by processors 400 or any IO (input/output) device initially starts to write the descriptors queues to the memory device 402. At 501, the software informs and sends a processor fetch signal to the Fetching module 401 that enough descriptors are written in memory and are ready to be fetched and to be transferred.

At 502, the processor fetch signal 450 sent via the control lines 408 will immediately activate the fetching module 401.

At 504, the fetching module 401 then evaluates if there is space in the buffer 403 so that the buffer 403 is ready to receive descriptors. If the buffer 403 is full, the fetching module 401 will remain in busy mode at 503. At 504, if the buffer 403 has space, then at 505, the fetching module starts Fetching a first set of descriptors in Descriptor Links (e.g., links 415˜418 and/or links 419˜421).

At 506, when the fetching module 401 sees or detects an End-Of-Link information (e.g., end-of-link information 323 in FIG. 3), then the fetching module 401 assumes that the Group fetched (fetching of DQG 413 or DQG 414) is complete. At 506, if the Group fetched is not complete, then at 505, the fetching module 401 continues to fetch the descriptor links.

At 507, the fetching module 401 finishes the writes in the buffer 403 and informs the DMA engine (which owns or is associated with the buffer 403 and which will process the descriptor groups 413 and 414) that the descriptors are in the buffer 403 are ready to be safely retrieved and processed by the DMA engine (e.g., DMA engine 106 in FIG. 1) so that the descriptors permit the DMA engine to perform a DMA operation.

At 508, the fetching module 401 checks if the fetching module 401 sees (detects) a next set of descriptors to be fetched by fetching module 401 from the memory device 402. If there are no descriptors to be fetched, then at 509, the fetching module 401 is de-activated and waits for re-activation via processor fetch signal 450. At 508, if there is a next set of descriptors to be fetched, then the fetching module 502 is activated at 502 as similarly discussed above and the subsequent operations in method 550 are performed again as similarly discussed above. While the DMA engine is retrieving the above-mentioned first set of descriptors from the buffer 403 and is executing the first set of descriptors, at 505, the fetching module 401 starts to fetch a second set of descriptors from the memory device 402 and writes the second set of descriptors into the buffer 403 if the fetching module 401 determines at 504 that the buffer 403 has space for receiving the second set of descriptors.

FIG. 6a and FIG. 6b are detailed diagrams on the stages of manipulating the DQGs including the transfer from the buffer to the sequencer, the sequencer mechanism of handling the DQGs, and the execution of the DQGs to perform the operation on a single DMA Engine according to an embodiment of the invention.

FIG. 6a is a system 650 illustrating an example of the flow of the descriptors from the buffer 601 to the DMA Engine 605 and showing the initial stage on how the information illustrated in FIG. 3 controls the flow and sequence between the buffer 601 and the DMA engine 605. The diagram of the system 650 shows (1) a fetching module 600, (2) a single buffer 601 having the Buffer-to-DMA engine interface 602, processor interface 603, and Fetching module interface 604; (3) a DMA Engine 605 that comprises a sequencer 606 (descriptor management unit 606) that is subdivided into a plurality of Descriptor Channels (e.g., Channel 1607, Channel 2608, Channel 3609, and up to Channel X 610, wherein X is an integer) and Control Circuit 611 with a DMA-Flash Interface 612; (4) a Flash Controller 615; and (5) one set of Flash Array 616.

The fetching module 600 is coupled via bus 624 to the fetching module interface 604 of the buffer 601. The buffer-DMA interface 602 of the buffer 601 is coupled via bus 613 to the DMA-Buffer interface 617 of the DMA engine 605. The DMA-Flash interface 612 of the DMA engine 605 is coupled via Flashbus protocol or other bus IO standard protocol (e.g., PCIe) 614 to the flash controller 615. The flash controller 615 performs access to flash devices in the flash array 616 and performs reading of data from and writing of data to the flash devices in the flash array 616.

The Fetching module 600, independent of the descriptor processing of the DMA engine 605, continuously retrieves the descriptors, and monitors and fills up the buffer 601 via the Fetching Module Interface 604 until the buffer 601 is full. Inside the Buffer 601, the descriptor queue groups are segregated according to priority. For example, the descriptor queue groups G1, G2, G3, G4, and G5 are segregated or included in the descriptor link 618 with Priority 1. The descriptor queue groups G7 and G8 are segregated or included in the descriptor link 619 with Priority 2. The descriptor queue groups Gm-1, Gm-2, and Gm-3 are segregated or included in the descriptor link 620 with Priority n wherein n is an integer. Therefore, each of the descriptor links in the buffer 601 has a different corresponding priority value.

Based on the Group Link information (e.g., group link information 303 in FIG. 3), G1 to G5 are fetched 621, G7 to G8 are fetched 622, and Gm-3 to Gm-1 are fetched 623, with these fetched Descriptor Queue Groups forming atomic links together to perform a series of DMA Operations. Typically the group link information is meta data or control data that will permit at least one DQG to be linked to another DQG or to be linked to a plurality of DQGs. The descriptor groups are atomically interlinked as shown by the different linked descriptor queue groups 621, 622, and 623 to allow fetching without any intervention from the processor. A CPU Intervention including abort or suspend commands may stop the fetching between Descriptor Links only.

Based on the sequence information (e.g., sequence information 302 in FIG. 3) in each descriptor queue group (DQG), each set of descriptor queue groups is categorized to Descriptor Link Priority 1 (link 618), Descriptor Link Priority 2 (link 619), and up to Descriptor Link Priority n (line 620), wherein n is an integer, in order to determine which atomic Descriptor link will be serviced first by a DMA Engine. Therefore, each of the descriptor links 618, 619, and 620 have priority values 1, 2, and n, respectively, wherein the respective priority values of the descriptor links differ and wherein the highest to lowest priority are priority 1, priority 2, and priority n, so that the DMA engine 605 will service the descriptor link first, and then will service descriptor link 619 and then will service descriptor link 620. Like the group link information, the sequence information and descriptor group tag number (e.g., descriptor group tag number 301) are each meta data or control data.

FIG. 6b is a system 650 illustrating the activation of the DMA Engine 605 and Descriptor Queue Group dissection and processing. The DMA Engine 605, which when activated via the DMA-CPU interface 603 or via the DMA-Buff interface 604, starts two major sections to perform major roles in the DMA engine 605. These sections are: (1) the sequencer 606 which has the capability to retrieve the Descriptor Queue Groups in the Buffer 601 via the DMA-Buff interface 617, monitors any processor intervention via The DMA-CPU interface 625, extracts the Descriptor Queues in the Descriptor Queue Groups and re-arranges the descriptor queues as the sequence before the execution (processing) of the descriptor queues in the respective channels 607˜610, and performs hardware abort and/or suspend or priority re-arrangement; and (2) The control section 611 which is responsible for the execution of the Descriptor Queues, and for manipulating the control signals to the Flash Controller 615.

In FIG. 6b, the DMA engine 625 is subdivided into X channels 607˜610 wherein X is an integer. These channels are formulated for concurrent processing of the Descriptor Queues (DQs) to perform striping and interleaving of the Flash devices as discussed, for example, in commonly-owned and commonly-assigned U.S. patent application Ser. No. 14/217,249 which is entitled SCATTER-GATHER APPROACH FOR PARALLEL DATA TRANSFER IN A MASS STORAGE SYSTEM and in commonly-owned and commonly-assigned U.S. Patent Application No. 61/980,628 which is entitled SCATTER-GATHER APPROACH FOR PARALLEL DATA TRANSFER IN A MASS STORAGE SYSTEM.

In this example as shown in FIG. 6b, Descriptor Queue Group 1 (G1) 626 is the first group of Descriptor Link Priority 1 (link 618 with Priority 1) being serviced in the sequencer 606. The Descriptor Queue Group 1 (G1) 626 comprises Descriptor Queues Q0 to Q10 (descriptor queues 626a˜626k) are extracted, and re-arranged in the respective channels 607˜610 and processed in the DMA engine 605. For example, descriptor queues (QO) 626a, (Q1) 626b, and (Q8) 626i are re-arranged in the channel 607. Descriptor queues (Q2) 626c, (Q4) 626e, and (Q9) 626j are re-arranged in the channel 608. Descriptor queues (Q3) 626d, (Q5) 626f, and (Q10) 626k are re-arranged in the channel 609. Descriptor queues (Q6) 626g and (Q7) 626h are re-arranged in the channel 610. Descriptor queues (Q0) 627a, (Q2) 627b, (Q3) 627c, and (Q6) 627d are decoded and arbitrated in the control section 611 based on the availability of the target flash device (e.g., flash device 655) in a single Flash array 616. For example, the single flash array 616 comprises a plurality of flash devices such as flash devices 655, 656, 657, 658, 659, and 660. The flash devices in a flash array 616 may vary in number. These partly processed DQs 627a˜627d and the unprocessed DQs 626a, 626c, 626d, 626g are represented by the percentage values 628 at the Control Section 611 in their respective channels 607, 608, 609, and 610. The pending DQs 626b, 626e, 626f, 626h, 626i, 626j, and 626k are lined up per channel waiting to be processed and are represented by the percentage values 629 in their respective channels 607, 608, 609, and 610. These pending DQs can be aborted, suspended, and re-prioritized on-the-fly via the CPU interface 625.

FIG. 7 is a flow chart representation diagram of an algorithm 750 of a descriptor flow in the DMA engines according to an embodiment of the invention. This algorithm 750 shows the manipulation of the DQGs from the alteration of the sequence of DQGs to the execution of these descriptors.

Reference is now made to FIGS. 6a and 6b and FIG. 7. At 700, the DMA engine 605 is activated. Once the DMA engine is activated, at 701, the sequencer 606 (of the DMA engine 605) checks if there are Descriptor Queue Groups atomically linked to be fetched in the buffer 601. Therefore, at 701, the sequencer 606 checks the buffer 601 for ready-to-be-processed descriptors.

At 702, the sequencer 606 continuously fetches all the linked Descriptor Queue Groups in the buffer 601 until the sequencer 606 reads an end-of-link information (e.g., end-of-link information 323 in FIG. 3) in a DQG that the sequencer 606 is reading. At 702, the sequencer 606 checks the descriptor queue groups to determine if a given descriptor queue group is ready to be decoded, and the presence of the end-of-link information in the given DQG indicates that the DQG is ready to be decoded and processed. At 702, if no DQG is ready to be decoded, then the sequencer 606 continues to check for ready-to-be-processed descriptors at 701. At 702, if the sequencer 606 determines that a given DQG is ready to be decoded, then the sequencer 606 will start to decode that given DQG at 703.

While the sequencer 606 is fetching the rest of the descriptor group queues within a given descriptor link, at 703, the sequencer 606 starts to decode the sequence information of the descriptor group, and at 704, the sequencer 606 rearranges the sequence of the descriptor queues, and performs filling up of the channels 607˜610 with descriptor queues in preparation for execution of the descriptors by the DMA engine 605.

At 705, the sequencer 606 also monitors any on-the-fly abort or suspend issued by the either software or processor or hardware (e.g., any of processors 139˜141 or any of I/O devices 139˜141). At 705, if an abort or suspend is issued, then at 706, the sequencer 606 performs an abort sequence or suspend sequence, respectively, before de-activation. At 717, the DMA engine 605 is de-activated. At 705, if an abort is not issued and if a suspend is not issued, then at 707, the sequencer 606 checks the priority ranking and concurrence of the descriptor links (by checking the sequence information 302 and group link information 303 in a given DQG 300), and at 708, the sequencer 606 re-arranges the descriptor queues for execution.

At 709, the sequencer 606 checks if the descriptor queues are in order after rearranging the descriptor queues. At 709, if the descriptor queues are not in order, then the sequencer 606 then arranges the sequences of the descriptor queues as performed in the operations at 704 and the sequencer 606 continues to check for any issued abort or suspend at 705. At 709, if the descriptor queues are in order, then at 710, the sequencer 606 checks the validity of bits in the descriptor queues. At 711, if the descriptor queue bits are found invalid (not valid), then at 712, the sequencer 606 will not process the descriptor queue. At 711, if the descriptor queue bits are found valid, then the sequencer 606 will perform the operations at 719 and 720 as discussed below.

At 712, after the sequencer 606 scraps the descriptor queue, then at 713, the sequencer 606 checks if the descriptor queue is critical. At 713, if the descriptor queue is critical, then at 714, the sequencer 606 informs the processor by sending an error interrupt to the processor before de-activating the DMA engine. At 713, if the descriptor queue is non-critical, then at 719, the sequencer 606 performs a re-order of the Valid Descriptor Queues and processes the valid descriptor queues in order to perform DMA operations. At 720, the sequencer 606 converts the descriptors (in the descriptor queues) to signals that are sent via DMA-flash interface 612 (FIG. 6b) to permit DMA operations.

At 715, the sequencer 606 continues to perform validity checking of bits in the descriptor queues as performed at 710 and processing of the descriptors until the whole process of executing the descriptors is done. At 715, if the process of executing the descriptors is not yet done, then the sequencer 606 continues to perform validity checking of bits in the descriptor queues as performed at 710 and processing of the descriptors until the whole process of executing the descriptors is done. At 715, if the process of executing the descriptors is done, then at 716, the sequencer 606 then checks for the availability of the next set of linked queue descriptor groups, and performs the sequencing and processing procedure at 701 and subsequent operations in the method 750 as discussed above, until there are no more descriptor queues to be fetched from the buffer 601 and no more descriptor Queues to process. At 716, if there are no more descriptor queues to be fetched from the buffer 601 and to be processed, then at 717, the DMA Engine 605 then de-activates and waits for the next activation signal to activate the DMA engine 605.

FIG. 8 is a block diagram illustrating a linking mechanism according to an embodiment of the invention. This linking mechanism in system 850 is a type of atomic linking 800 for multiple DMA engines 803 (e.g., DMA engines 803a˜803d) via the sequencers 802a˜802d. There can be an X number of DMA engines 803 wherein X is an integer. The Sequence Link Information based on FIG. 3 (see, e.g., sequence link information 307, 312, or 317) of each descriptor queue 801 can be across different DMA engines 803. As discussed with reference to FIG. 3 above, a sequence link information in a descriptor queue will link a descriptor to another descriptor or to a plurality of descriptors. This type of link capability establishes a communication link and synchronization between multiple DMA Engine operations. Command dependencies between pluralities of DMA engines could then be implemented as an application to the aforementioned link capability. Atomic linking 800 comprising descriptor 7 in 802a, descriptor 4 in 802b, descriptor 6 in 802c and descriptor 10 in 802d may mean any of the ff. depending on the configuration (only to illustrate atomic linking 800, should not be limited to the scenarios below):

1. The above mentioned descriptors are started/ended concurrently, in sequence, or in other predefined manner.

For example, CONCURRENT START Mode. the DMA engine associated with descriptor 7 of 802a will only start execution if the DMA engines associated with descriptor 4 in 802b, descriptor 6 in 802c and descriptor 10 in 802d are also ready to start executing those aforementioned descriptors.

For example, CONCURRENT END Mode. The DMA engine executing descriptor 7 of 802a will only declare DONE if the DMA engines associated with descriptor 4 in 802b, descriptor 6 in 802c and descriptor 10 in 802d are also ready to declare DONE executing those aforementioned descriptors.

For example, SEQUENTIAL Mode. Start and finish execution of descriptor 7 of 802a, then start and finish execution of descriptor 4 in 802b, then start and finish execution of descriptor 6 in 802c and lastly start and finish execution of descriptor 10 in 802d.

Descriptor 8 in 802a, descriptor 5 in 802b, descriptor 7 in 802c will not be able to start execution unless all the descriptors in Atomic link 800 has finished execution.

Once any of the descriptors within the atomic link 800 start executing, no descriptor not belonging to the atomic link 800 will be allowed to execute until all descriptors under atomic link 800 have _started_— executing, regardless of the DMA engine.

Once any of the descriptors within the atomic link 800 start executing, no descriptor not belonging to the atomic link 800 will be allowed to execute until all descriptors under atomic link 800 have _ended_— executing, regardless of the DMA engine.

Descriptor sequence per DMA engine may or may not be rearranged to prioritize the descriptors belonging to atomic linking 800.

Foregoing described embodiments of the invention are provided as illustrations and descriptions. They are not intended to limit the invention to precise form described. In particular, it is contemplated that functional implementation of invention described herein may be implemented equivalently in hardware, software, firmware, and/or other available functional components or building blocks, and that networks may be wired, wireless, or a combination of wired and wireless.

It is also within the scope of the present invention to implement a program or code that can be stored in a non-transient machine-readable (or non-transient computer-readable medium) having stored thereon instructions that permit a method (or that permit a computer) to perform any of the inventive techniques described above, or a program or code that can be stored in an article of manufacture that includes a non-transient computer readable medium on which computer-readable instructions for carrying out embodiments of the inventive techniques are stored. Other variations and modifications of the above-described embodiments and methods are possible in light of the teaching discussed herein.

The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

1. A method, comprising: fetching, by a fetching module, a first set of descriptors from a memory device and writing, by the fetching module, the first set of descriptors to a buffer;retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation;checking, by the fetching module, if space is available in the buffer; andif space is available in the buffer, fetching, by the fetching module, a second set of descriptors from the memory device and writing, by the fetching module, the second set of descriptors to the buffer during or after the processing of the first set of descriptors;wherein the first set of descriptors are fetched from the memory device until an end-of-the-link information is detected in the first set.

2. The method of claim 1, further comprising: writing the first set and second set of descriptors into the memory device prior to fetching the first set and the second set from the memory device.

3. The method of claim 1, further comprising: segregating descriptor queue groups into a plurality of descriptor links in the buffer and wherein each of the descriptor links has a different corresponding priority value;wherein each descriptor queue group comprises a plurality of descriptor queues and wherein each descriptor queue comprises a plurality of descriptors.

4. The method of claim 1, further comprising: using a group link information to link a plurality of descriptor queue groups.

5. The method of claim 1, further comprising: using a sequence information to categorize a plurality of descriptor queue groups into a plurality of descriptor links, wherein each descriptor link has a different corresponding priority value.

6. The method of claim 1, further comprising: extracting descriptor queues in a plurality of descriptor queue groups and re-arranging the descriptor queues as a sequence before execution of the descriptor queues in respective channels.

7. The method of claim 1, further comprising: processing at least one of the descriptors in a plurality of Direct Memory Access (DMA) engines.

8. The method of claim 1, comprising: using a sequence link information in a descriptor queue group to link a plurality of descriptors.

9. An apparatus, comprising: a fetching module configured to fetch a first set of descriptors from a memory device and to write the first set of descriptors to a buffer;a sequencer configured to retrieve the first set of descriptors from the buffer and to process the first set of descriptors to permit a Direct Memory Access (DMA) operation;wherein the fetching module is configured to check if space is available in the buffer; andwherein if space is available in the buffer, the fetching module is configured to fetch a second set of descriptors from the memory device and to write the second set of descriptors to the buffer during or after the processing of the first set of descriptors;wherein the fetching module is configured to fetch the first set of descriptors from the memory device until an end-of-the-link information is detected in the first set.

10. The apparatus of claim 9, further comprising: a processor configured to write the first set and second set of descriptors into the memory device prior to the fetching module fetching the first set and the second set from the memory device.

11. The apparatus of claim 9, wherein the sequencer is configured to segregate descriptor queue groups into a plurality of descriptor links in the buffer and wherein each of the descriptor links has a different corresponding priority value; wherein each descriptor queue group comprises a plurality of descriptor queues and wherein each descriptor queue comprises a plurality of descriptors.

12. The apparatus of claim 9 wherein the sequencer is configured to use a group link information to link a plurality of descriptor queue groups.

13. The apparatus of claim 9, wherein the sequencer is configured to use a sequence information to categorize a plurality of descriptor queue groups into a plurality of descriptor links, wherein each descriptor link has a different corresponding priority value.

14. The apparatus of claim 9, wherein the sequencer is configured to extract descriptor queues in a plurality of descriptor queue groups and to re-arrange the descriptor queues as a sequence before execution of the descriptor queues in respective channels.

15. The apparatus of claim 9, wherein the sequencer comprises a plurality of sequencers, wherein each sequencer is in a different respective Direct Memory Access (DMA) engine, wherein each of the plurality of sequencers is configured to process at least one of the descriptors.

16. The apparatus of claim 9, wherein the sequencer comprises a plurality of sequencers, wherein the plurality of sequencers are configured to use a sequence link information in a descriptor queue group to link a plurality of descriptors.

17. An article of manufacture, comprising: a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising:fetching, by a fetching module, a first set of descriptors from a memory device and writing, by the fetching module, the first set of descriptors to a buffer;retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation;checking, by the fetching module, if space is available in the buffer; andif space is available in the buffer, fetching, by the fetching module, a second set of descriptors from the memory device and writing, by the fetching module, the second set of descriptors to the buffer during or after the processing of the first set of descriptors;segregating descriptor queue groups into a plurality of descriptor links in the buffer and wherein each of the descriptor links has a different corresponding priority value;wherein each descriptor queue groups comprises a plurality of descriptor queues and wherein each descriptor queue comprises a plurality of descriptors.