Patent Grant
9442501
1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to a low dropout voltage regulator.
2. Related Art
Recent years have seen tremendous advancements in the field of electronic circuits. One such advancement is in the area of providing a supply voltage used to operate electronic circuits. The supply voltage may vary due to various factors such as changes in the load of the circuit to which the voltage is being supplied, temperature variations, aging, and so forth. Variation of the supply voltage can affect the operation of the electronic circuit. Thus, a voltage regulator is used to maintain the output of the supply voltage at a predetermined value. Over the years, a few different types of regulators have been developed, such as a standard regulator, a linear drop-out (LDO) regulator, and a quasi-LDO regulator, with LDO regulators being the most widely used.
A conventional LDO regulator includes an error amplifier, a pass-transistor, a capacitor, and resistance network. The error amplifier is connected to the gate of the pass-transistor. The source of the pass-transistor is connected to a voltage supply VDD and the drain of the pass-transistor comprises the output terminal of the LDO regulator. The capacitor is typically connected to the output of LDO regulator external to the device in which the LDO is implemented. The resistance network also is connected to the output of the LDO regulator and in parallel with the capacitor. A node between the resistors is connected to an input terminal of the error amplifier and provides a scaled-down version of the output voltage to the error amplifier. The error amplifier also receives a reference voltage signal that is generated by an external voltage reference circuit. The error amplifier compares the reference voltage signal and the scaled down version of the output voltage signal to generate an error amplified signal, which is provided to the gate terminal of the pass-transistor. The error amplified signal is used to maintain the output of the LDO regulator at a predetermined voltage.
The LDO regulator generates a constant output voltage to the load (not shown) by providing the required load current. If the magnitude of the load current increases due to variations in the load, there is a corresponding drop in the magnitude of the output voltage. The drop in the output voltage leads to an increase in the magnitude of the error amplified signal generated by the error amplifier. The increase in the error amplified signal in turn increases the magnitude of the source-gate voltage of the pass-transistor, causing a corresponding increase in the magnitude of the drain current of the pass-transistor, and the increase in the drain current pulls up the output voltage. Thus, the magnitude of the output voltage signal is maintained at the predetermined voltage. The capacitor connected to the output terminal improves the transient response of the LDO regulator.
During steady-state operation, the magnitude of the output voltage signal is maintained at the predetermined value and the output capacitor is charged to the magnitude of the output voltage signal. If the current of the load circuit changes abruptly and the main regulation loop, formed by the error amplifier, pass-transistor and resistor network, may not respond quickly because it has a bandwidth limitation, the capacitor provides the extra charge required by the load. As a result, the magnitude of the output voltage decreases or increases from the predetermined voltage value.
The magnitude of output voltage drop or rise can be improved by either increasing the bandwidth/speed of the main regulation loop or by increasing the value of the capacitor. However, such changes have associated constraints such as power consumption, silicon area, and overall cost of the system. To increase the bandwidth or speed of the main regulation loop, the DC current should be increased, which results in higher power consumption of the system and also increased die area. The external capacitor increases cost while an internal capacitor cannot be made very large because that would require significant additional die area. Thus, there is a need for a circuit that improves the transient response of the LDO regulator yet avoids the above-mentioned constraints.
The present disclosure is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Embodiments of systems and methods for a multi-path low drop out (LDO) voltage regulator are disclosed herein that can include a single substrate having circuitry to implement a first amplifier stage (204, 208) operable to provide a first gain level at a first bandwidth and a second amplifier stage (202) coupled to the first amplifier stage. The second amplifier stage can provide a second gain level at a second bandwidth. The first gain level is higher than the second gain level, and the second bandwidth is higher than the first bandwidth. A dynamic compensation circuit (206) coupled to the second amplifier stage can provide a varying level of compensation proportional to a current level associated with a load to the second amplifier stage. A current compensation circuit (212) coupled to an output of a third amplifier or driver stage (104) can allow a minimum current level at the third amplifier stage. The driver stage can be coupled to the first and second amplifier stages. The LDO voltage regulator reduces cost and the number of external components required to implement the LDO voltage regulator over known LDO regulators. The proposed regulator can supply one or more processing cores without requiring discrete external capacitors, regulating current load, for example, up to 350 milliAmperes (mA). Furthermore pins dedicated to a low core voltage are no longer required, reducing pad-ring limitations and increasing the number of functional pins available on the device.
An output voltage (OTA) of amplifier stage 102 is provided as an input to driver stage 104. In the embodiment shown, driver stage 104 includes P-channel transistors 106, 108, 110 with gate electrodes coupled to the output of amplifier stage 102. Drain electrodes of transistors 106, 108, 110 are coupled to one another. Drain electrode of transistor 106 is coupled to provide regulator output voltage (REG_OUT) to amplifier stage 102. Drain electrode of transistor 108 is coupled to provide a high current feedback signal (IFB_HI) to amplifier stage 102. Drain electrode of transistor 110 is coupled to provide regulator a low current feedback signal (IFB_LOW) to amplifier stage 102. The regulator output voltage (REG_OUT) can also be provided to drive an external load (not shown).
Amplifiers 202 and 204 each include a first input coupled to a feedback voltage VFBand the regulator output signal (REG_OUT). A reference voltage (VREF) is provided a second input of each of amplifiers 202 and 204. An output of amplifier 204 is coupled to an input of amplifier 208 and to a first terminal of capacitor 216. A second input to amplifier 208 is coupled to the reference voltage (VREF) and a second terminal of capacitor 216 is coupled to the output of driver stage 104. The outputs of amplifier 202 and amplifier 208 are coupled at the input to driver stage 104, and can be referred to a multi-path input to driver stage 104. High current feedback (IFB_HI) and low current feedback signal (IFB_LOW) are coupled to dynamic compensation circuit 206 and MCC circuit 212.
MCC circuit 212 is shown as a variable resistive element having a first terminal coupled to the output of driver stage 104 and a second terminal coupled to ground.
Load 214 is represented as resistive element 222 coupled in parallel with capacitor 224. First terminals of resistive element 222 and capacitor 224 are coupled to one another at the output of driver stage 104 and second terminals of resistive element 222 and capacitor 224 are coupled to one another at ground. Load 214 can be implemented on the same substrate as regulator 100. For example, regulator 100 can be implemented as part of a system on a chip (SoC) that includes one or more processors, memory, sensors, and/or other components. Additionally, since regulator 100 does not require an external capacitor, the output of regulator 100 can share a general purpose I/O pin, thus eliminating the need for a dedicated pin for the output of regulator 100.
Amplifier 202 is used as a first gain stage with high transconductance capable of driving a large capacitive load at high frequency but with fairly low gain. Amplifiers 204 and 208 form a second gain stage that provides a DC gain higher than the gain of amplifier 202 required to meet design specifications, such as a gain of 80 dB, even if the cut off frequency of the second gain stage is quite low. The bandwidth of the secondary gain stage (amplifiers 204 and 208) is lower than the bandwidth of the first gain stage (amplifier 202).
Dynamic compensation circuit 206 is used to cancel out a pole and allow for sufficient phase margin since the poles of driver stage 104 and the high frequency stage at amplifier 202 may be too close. Dynamic compensation circuit 206 is coupled to provide a varying level of compensation to the output of amplifier 202. The varying level of compensation is proportional to a current level associated with a load.
When the current in driver 100 is below a specified level, for example, approximately 30 mA, the pole of the driver stage 104 can drop below the allowed range and cause the bandwidth of the regulator 100 to drop below a specified level, such as one MegaHertz (MHz), for example. Accordingly, whenever the load of the regulator drops below the specified current, MCC circuit 212 provides an artificial load that keeps the total driver current at a minimum specified level and preserves the regulator bandwidth. In some embodiments, the artificial load is implemented as a variable resistive element 222 that can be adjusted to achieve the desired bandwidth and provide a constant minimum current level for regulator 100.
In some embodiments, regulator 100 can be configured to drive a DC equivalent load ranging from 2 mA to 500 mA with an equivalent capacitance ranging from 5 nano-Farads (nF) to 1000 nF. The DC gain of regulator can be greater than 40-60 decibels (dB) with a bandwidth of 1-10 MHz and a phase margin of at least 30 degrees
Source electrodes of N-channel transistors 406, 410, 416, 428 are coupled to supply voltage VSS_HV. A gate electrode of P-channel transistor 402 is coupled to a gate electrode of P-channel transistor 420. A gate electrode of P-channel transistor 408 is coupled to input voltage INN and a gate electrode of P-channel transistor 414 is coupled to input voltage INP. Gate electrodes of N-channel transistors 404, 406 are coupled to gate and drain electrodes of diode-connected N-channel transistor 410. Gate electrodes of N-channel transistors 426, 428 are coupled to gate and drain electrodes of diode-connected N-channel transistor 416. The gate electrodes of N-channel transistors 404, 426 are also coupled between the drain electrodes of respective P-channel transistors 408, 414 and the drain electrodes of respective N-channel transistors 410, 416. An output terminal of amplifier 204 is coupled between the drain electrode of P-channel transistor 420 and the drain electrode of N-channel transistor 426 to supply feedback voltage (INT_FE_MST).
Capacitors 422, 424 are coupled in parallel to one another between the gate electrode of P-channel transistor 414 and between the drain electrode of P-channel transistor 420 and the drain electrode of N-channel transistor 426.
During operation, when the actual load on regulator 100 is low, MCC circuit 212 can provide an additional load that keeps the total driver current at a specified level to preserve the bandwidth of regulator 100. The amount of additional load can be varied as function of the equivalent resistive load 222, in order to achieve the desired loop bandwidth.
During operation, since the 0-dB crossing of regulator 100 is load dependent, a constant value resistor would still not provide adequate phase margin over process, temperature, and voltage variations (PTV) and load. Therefore resistive element 220 includes N-channel transistor 704 biased in a linear region. The gate voltage and consequently the equivalent series resistance is modulated by the driver current. Higher driver current will increase the gate voltage and reduce the series resistance, so the compensation zero will track with the 0-dB crossing of regulator 100.
By now it should be appreciated that there has been provided a voltage regulator that can comprise a single substrate including circuitry to implement a first amplifier stage [204, 208] operable to provide a first gain level at a first bandwidth and a second amplifier stage [202] coupled to the first amplifier stage. The second amplifier stage can provide a second gain level at a second bandwidth. The first gain level can be higher than the second gain level, and the second bandwidth can be higher than the first bandwidth. A dynamic compensation circuit [206] can be coupled to the second amplifier stage to provide a varying level of compensation to the second amplifier stage that is proportional to a current level associated with a load. A current compensation circuit [212] can be coupled to an output of a third amplifier stage [104] to allow a minimum current level at the third amplifier stage. The third amplifier stage can be coupled to the first and second amplifier stages.
In another aspect, the minimum current level can be constant.
In another aspect, the minimum current level can be a function of the load.
In another aspect, the dynamic compensation circuit can comprise a transistor
coupled in parallel to a compensation resistor [326]. The transistor can have a gate voltage modulated by a current level associated with the third amplifier stage.
In another aspect, the output of the third amplifier stage can be coupled directly to an output pin of the single substrate.
In another aspect, the load can be formed on the single substrate.
In another aspect, the direct voltage gain of the voltage regulator can be greater than forty decibels.
In another aspect, the voltage regulator can be responsive to a direct current equivalent load within the range of two to five hundred milliamps (2-500 mA).
In another aspect, an equivalent capacitance coupled to an output of the voltage regulator can be within the range of five to one hundred nanofarads (5-100 nF).
In another aspect, the voltage regulator can be operable to provide a phase margin greater than thirty degrees.
In another aspect, the current compensation circuit can comprise a first transistor of the first type [604] having a first current electrode coupled to an input signal and a first electrode of a resistor [606], a control electrode coupled to a bias voltage, and a second current electrode coupled to a first supply voltage, a capacitor [612] coupled in parallel between a second electrode of the resistor and the first supply voltage, and a first transistor of a second type [614] having a first current electrode coupled to an input voltage, a control electrode coupled to the second electrode of the resistor, and a second current electrode coupled to a second supply voltage.
In another aspect, the dynamic compensation circuit can comprise a first transistor of a first type [704] having a first current electrode coupled to an output of the second amplifier stage, a second current electrode coupled to a source voltage, and a second transistor [706] of the first type having a first current electrode coupled to the source voltage, and a second current electrode and a control electrode coupled to: one another, a control electrode of the first transistor of the first type, and an input signal.
In other embodiments, a semiconductor device can comprise a load [214], and a voltage regulator [100] coupled to the load. The voltage regulator can comprise a multipath amplifier stage [102], a driver stage [104] coupled to the multipath amplifier stage, and a dynamic compensation circuit [206] coupled to the multipath amplifier stage. The dynamic compensation circuit can be operable to provide a varying level of compensation to the multipath amplifier stage that is proportional to a current level associated with the load. A current compensation circuit [212] can be coupled to an output of the driver stage to allow a minimum current level at the driver stage.
In another aspect, the load and the voltage regulator can be formed on the same substrate.
In another aspect, an output of the driver stage can be directly coupled to an output pin of the semiconductor device.
In another aspect, the minimum current level can be constant.
In another aspect, the minimum current level can be a function of the load.
In another aspect, the dynamic compensation circuit can comprise a transistor coupled in parallel to a compensation resistor. The transistor can have a gate voltage modulated by a current level associated with the third amplifier stage.
In another aspect, the current compensation circuit can comprise a first transistor of the first type [604] having a first current electrode coupled to an input signal and a first electrode of a resistor [606], a control electrode coupled to a bias voltage, and a second current electrode coupled to a first supply voltage, a capacitor [612] coupled in parallel between a second electrode of the resistor and the first supply voltage, and a first transistor of a second type [614] having a first current electrode coupled to an input voltage, a control electrode coupled to the second electrode of the resistor, and a second current electrode coupled to a second supply voltage.
In another aspect, the dynamic compensation circuit can comprise a first transistor of a first type [704] having a first current electrode coupled to an output of the multipath amplifier stage, a second current electrode coupled to a source voltage, and a second transistor of the first type [706] having a first current electrode coupled to the source voltage, and a second current electrode and a control electrode coupled to: one another, a control electrode of the first transistor of the first type, and an input signal.
Because the apparatus implementing the present disclosure is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present disclosure and in order not to obfuscate or distract from the teachings of the present disclosure.
Although the disclosure has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed.
Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.
Also for example, in one embodiment, the illustrated elements of system 100 are circuitry located on a single integrated circuit or within a same device.
Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.
Although the disclosure is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to disclosures containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
| Number | Name | Date | Kind |
|---|---|---|---|
| 5945819 | Ursino et al. | Aug 1999 | A |
| 6157176 | Pulvirenti et al. | Dec 2000 | A |
| 6388433 | Marty | May 2002 | B2 |
| 6975099 | Wu et al. | Dec 2005 | B2 |
| 7106033 | Liu | Sep 2006 | B1 |
| 7106037 | Ohtake | Sep 2006 | B2 |
| 7180358 | Kwon | Feb 2007 | B2 |
| 7199565 | Demolli | Apr 2007 | B1 |
| 7741823 | Terry et al. | Jun 2010 | B2 |
| 20080180080 | Terry et al. | Jul 2008 | A1 |
| 20080303496 | Schlueter | Dec 2008 | A1 |
| 20140117958 | Price | May 2014 | A1 |
| Entry |
|---|
| Milliken, R.J., et al., “Full On-Chip CMOS Low-Dropout Voltage Regulator”, IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 54, No. 9, Sep. 2007. |
| Number | Date | Country | |
|---|---|---|---|
| 20150346748 A1 | Dec 2015 | US |
