Patent Application
20150378418
I. Field of the Disclosure
The technology of the disclosure relates generally to power conservation over a universal serial bus (USB).
II. Background
Computing devices rely on buses to convey signals between internal components within the computing device and from the computing device to peripheral devices. A common type of bus is the universal serial bus (USB), which has a variety of flavors, each with its own published standard. Currently, super speed USB (SS-USB) and other versions of USB 3.0 and USB 3.1 are prevalent, although numerous legacy USB 2.0 compliant devices remain in the market.
While the various flavors of USB may be used for various devices, such as memory storage devices and memory devices, as well as stationary computing devices like desktop computers, servers, or the like, USB may also be used with mobile computing devices such as smart phones, tablets, cameras, cellular phones, or the like. Mobile computing devices are under considerable pressure to reduce power consumption so that end users have ample time between battery charging events. While battery technology has improved such that the batteries do not have to be charged frequently, further improvements are still desired.
Intel Corporation has defined a physical layer (PHY) interface that is compatible with USB as well as the peripheral component interface (PCI) express (PCIe) and the serial advanced technology attachment (SATA) interface. In particular this PHY interface is set forth in a document entitled PHY Interface for the PCI Express, SATA, and USB 3.0 Architectures, currently in version 4.0 as of 2011. This PHY interface is frequently referred to as the PIPE (PHY Interface for the PciE) (note that the PHY interface is still referred to as PIPE even when the PHY interface is not being used with PCIe (for example, when it is being used with USB, it is still referred to as a PIPE or PIPES interface)). In conventional implementations, the USB interface and the PIPE interface share a common clock having a phase locked loop (PLL).
USB 3.0 does have two low power modes labeled U1 and U2 and one shut down mode labeled U3. When the USB interface shifts into a low power mode, the PIPE interface may also shift into a low power mode such as P1 or P2. While the USB 3.0 standard contemplates turning off the clock in U2, the corresponding low power mode P2 of the PIPE interface requires a clock signal, and thus the conventional approach is to leave the shared clock on during U2. Clocks, and in particular, PLLs of clocks, consume relatively large amounts of power. Thus, further improvements in power conservation for USB 3.0 buses are desirable.
Aspects disclosed in the detailed description include systems and methods for conserving power in a universal serial bus (USB). In particular the systematic methods, address the interaction between a physical layer (PHY) interface and a PHY interface for PCIe (PIPE) interface. In an exemplary aspect, when a USB device enters a low power mode (e.g., U2), a clock associated with the USB device is modified to also enter a low power mode. Since the physical layer (PIPE) interface associated with the USB device still requires a clock signal, the low power clock mode must still be able to provide the PIPE interface with a clock signal (e.g., typically at 125 MHz). However, the clock signal to the PIPE interface does not need to be the same frequency or accuracy as the clock signal used by the USB interface. The modification to the clock changes the clock frequency to a low frequency (e.g. 19.2 MHz) compared to the normal clock frequency (e.g., 125 MHz). The modification may, instead of changing the frequency, keep the same frequency, but reduce the accuracy of the clock and/or increase the jitter associated with the clock. By using a low frequency clock (or a less accurate clock) for the PIPE interface, power is conserved while preserving the functionality of the PIPE interface.
Accordingly, exemplary aspects of the present disclosure provide a multiplexer (MUX) that receives a clock signal generated by a phase locked loop (PLL) internal to the USB interface and a clock signal from an external source. When the USB interface enters a low power mode, the USB interface deactivates the PLL, and the MUX provides the external clock signal to the PIPE interface.
In another exemplary aspect, the clock signal associated with the USB device is modified by deactivating a PLL associated with the clock and replacing the PLL generated clock signal with a frequency locked loop (FLL) clock signal operating at a lower frequency than the PLL generated clock signal. The FLL may be an existing FLL in the PHY, and may, for example, operate at 115.2 MHz.
In another exemplary aspect, the clock associated with the USB device is deactivated and two clocks are activated. The first clock is associated with the PIPE interface, and the second clock is associated with a USB controller. The clock associated with the PIPE interface may operate at a low frequency and asynchronously with a clock associated with the USB controller.
In this regard in one aspect, a method for controlling a USB interface is disclosed. The method comprises at the USB interface entering a low power mode, which further enters a lower power mode at a PIPE interface because the USB entered the low power mode. The method further comprises modifying a clock at the USB interface to reduce power consumption while maintaining a PIPE clock signal to the PIPE interface.
In another aspect, a method providing a PIPE interface a clock signal from a PHY interface in low power modes and high power modes is disclosed. This method comprises in a high power U0 mode, generating high frequency clock signal at the PHY interface using a PLL and providing the high frequency clock signal from the PHY interface to the PIPE interface. The method further comprises in a low power mode modifying operation of the PLL, providing a low frequency clock signal from the PHY interface to the PIPE interface.
In another aspect, a method for controlling a USB device is disclosed. This method comprises in a high power U0 mode generating a high frequency clock signal at a PHY interface using a PLL and providing the high frequency clock signal from the PHY interface to a PIPE interface. The method further comprises on a low power mode, deactivating the PLL. The method also comprises receiving a low frequency external clock signal at the PHY interface and providing the low frequency external clock signal from the PHY interface to PIPE interface.
In another aspect, a method of operation for a PIPE interface within a USB device is defined. This method comprises during a high power state, receiving a clock signal generated by a PLL in a PHY interface. This method also comprises entering a low power state and receiving a substitute clock signal from the PHY interface.
In another aspect, a USB device is disclosed. The USB comprises a PHY interface coupled to a USB, the PHY interface comprising a clock with a PLL. The USB also comprises a controller comprising a PIPE interface, the controller communicating to the PHY interface using a PIPE protocol. Wherein in a high power U0 mode the clock with the PLL is configured to generate a high frequency clock signal at a PHY interface using the PLL and the PHY interface is configured to provide the high frequency clock signal from the PHY interface to the PIPE interface. Wherein a low power mode the PHY interface is configured to deactivate the PLL, receive a low frequency external clock signal and provide the low frequency external clock signal from the PHY interface to the PIPE interface.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed in the detailed description include systems and methods for conserving power in a universal serial bus (USB). In particular the systematic methods, address the interaction between a physical layer (PHY) interface and a PHY interface for PCIe (PIPE) interface. In an exemplary aspect, when a USB device enters a low power mode (e.g., U2), a clock associated with the USB device is modified to also enter a low power mode. Since the physical layer (PIPE) interface associated with the USB device still requires a clock signal, the low power clock mode must still be able to provide the PIPE interface with a clock signal. However, the clock signal to the PIPE interface does not need to be the same frequency as the clock signal used by the USB interface. The modification to the clock changes the clock frequency to a low frequency compared to the normal clock frequency. The modification may, instead of changing the frequency, may keep the same frequency, but reduce the accuracy of the clock and/or increase the jitter associated with the clock. By using a low frequency clock (or a less accurate clock) for the PIPE interface, power is conserved while preserving the functionality of the PIPE interface. It should be appreciated that the USB device may be a USB host, a USB peripheral device, and/or a USB On the Go (OTG) device.
Before addressing particular aspects of the present disclosure, a brief overview of devices that may benefit from aspects of the present disclosure is provided with reference to
While an exemplary aspect of the present disclosure contemplates use in a mobile terminal such as a cellular phone, the present disclosure is not so limited. In this regard,
In addition to computing devices 10, the exemplary aspects of the present disclosure may also be implemented on mobile computing devices. In this regard, an exemplary aspect of a mobile terminal 22 is illustrated in
Generically,
Other devices can be connected to the system bus 38. As illustrated in
The CPU(s) 32 may also be configured to access the display controller(s) 48 over the system bus 38 to control information sent to one or more displays 52. The display controller(s) 48 sends information to the display(s) 52 to be displayed via one or more video processors 54, which processes the information to be displayed into a format suitable for the display(s) 52. The display(s) 52 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), light emitting diode (LED), a plasma display, etc.
As noted above, the system bus 38 may be a USB. Likewise, there may be other buses within the computing device 10 or the mobile terminal 22 that operate according to a USB protocol. Still further, peripheral devices (not shown) may be coupled to the computing device 10 or the mobile terminal 22 through a USB cable or connector. Further, the mobile terminal 22 may be coupled to the computing device 10 through a USB cable or connector. Exemplary aspects of the present disclosure are applicable to any such USB that complies with USB 3.0 or later standards.
The USB protocol defines four modes of operation. U0 is considered normal operation with all sub-components awake and operating to transfer data. U1 is considered a first low power mode that is entered into after a predefined idle period of U0. U2 is another lower power mode that is entered into after a predefined idle period of U1. Note further, that it is possible to move directly from U0 to U2 in certain configurations. U3 is a suspended mode that has many elements deactivated. The USB interface interoperates with the PIPE interface, which has modes P1 and P2 that correspond to U1 and U2. While the USB protocol indicates that the clock for the USB interface may be turned off in U2, in practice, the clock for the USB PIPE interface remains on because the clock is shared with the PIPE interface, which requires a clock signal during its corresponding P2 mode.
Because the clock for the USB PIPE interface is not turned off in U2 or U1, the power savings achieved by a convention U1 is relatively modest. Likewise, the power savings for U2 is also substantially less than is possible. In this regard,
With continued reference to
An exemplary aspect of the clock modification of the present disclosure is provided in
To provide the required clock signal to the PIPE interface 95 in the USB controller 94, the MUX 106 selects the reference clock and passes the reference clock to the PIPE interface 95 in the USB controller 94. The glitch free nature of the MUX 106 allows the PIPE interface 95 to remain synched to the new PIPE clock (i.e. the reference clock) as required. In an exemplary aspect the clock signal 104 is 125 MHz and the reference clock signal 102 is 19.2 MHz. While 125 MHz is specifically contemplated, other high frequency signals (e.g., over 100 MHz) may also be used without departing from the present disclosure; likewise, while 19.2 MHz is specifically contemplated, other low frequency signals (e.g., under 100 MHz) may also be used without departing from the present disclosure. The slower clock frequency of the reference clock signal 102 is still sufficient to satisfy the PIPE interface 95, but the lower frequency consumes less power since there are fewer transitions in a given time period.
In a second exemplary aspect, an auxiliary clock signal 108 is provided to the MUX 106. The MUX 106 selects the clock signal 104 when the USB device 90 is in U0 and selects the auxiliary clock signal 108 when the USB device 90 is in a low power mode. When in a low power mode, the PLL 100 is turned off. The auxiliary clock signal 108 is also of a lower frequency than the clock signal USB 104. The lower frequency and the deactivated PLL 100 save power. Note that the standard currently allows approximately 250 microseconds for the transition from U2 to U0. When the PLL 100 remains on, the transition takes about 50 microseconds. With the PLL 100 off as set forth in exemplary aspects, turning on the PLL 100 during the transition to U0 may take approximately 100 microseconds, which is still well within the tolerances of the standard. If exit latency is higher than 100 microseconds, the exit time parameter of U1 can be increased in software. Such software increases are supported in the standard.
While turning off the PLL 100 provides the most power savings, power savings can be achieved through alternate mechanisms. In this regard, in an exemplary aspect,
In an alternate aspect, the FLL used for the alternate clock source may already be in existence within the PHY for other reasons, such as to support U3/P3 mode. This aspect is illustrated in
Note that in either FLL aspect there may be different requirements that may be accommodated. For example, in U1, both detection and transmission of a PING.LFPS should be supported. In U2, there may not be a need to detect the PING.LFPS, but still differentiate a PING.LFPS signal from a wake up signal that can be either U1 exit LFPS or U2 exit LFPS. Detection of the U1 exit or U2 exit can be done with a lower frequency clock than the one required for U1 PING.LFPS.
In another exemplary aspect, instead of modifying the PLL 112 to operate as an FLL (
Note that in various aspects of the present disclosure, an ENABLE_MODE signal may be provided from the USB controller 94 to the SS PHY 98, 98′, or 122 that causes the mode of the SS PHY 98, 98′ or 122 to change between different states, such as RX.DETECT, U1, U2, and so forth. Note that in RX.DETECT state, the PLL will still be needed even if the SS PHY is otherwise in P2 mode. Likewise, P2 can be used for the SS.INACTIVE mode.
As noted above, power savings may also be achieved not by lowering the frequency, but by lowering the accuracy of the clock signal. Such less accurate clock signals may have high jitter, but reduced power consumption.
A method 140 for operating a USB device 90, 110, 120 is provided with reference to
In a further aspect of the present disclosure, a process 160 for entering low power U1 and/or U2 modes is presented with reference to
In a further aspect of the present disclosure, a process 180 for exiting a low power mode is presented with reference to
With continued reference to
The systems and methods for conserving power in a USB according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player.
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flow chart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
