Patent Grant
11723128
Certain embodiments of the present invention are directed to circuits. More particularly, some embodiments of the invention provide systems and methods for controlling currents. Merely by way of example, some embodiments of the invention have been applied to light emitting diodes (LEDs). But it would be recognized that the invention has a much broader range of applicability.
With development in the light-emitting diode (LED) lighting market, many LED manufacturers have placed LED lighting products at an important position in market development. The LEDs often provide high brightness, high efficiency, and long lifetime. The LED lighting products usually need dimmer technology to provide consumers with a unique visual experience. Since Triode for Alternating Current (TRIAC) dimmers have been widely used in other lighting systems such as incandescent lighting systems, the TRIAC dimmers are also increasingly being used in LED lighting systems.
Conventionally, the TRIAC dimmers usually are designed primarily for incandescent lights with pure resistive loads and low luminous efficiency. Such characteristics of incandescent lights often help to meet the requirements of TRIAC dimmers in holding currents. Therefore, the TRIAC dimmers usually are suitable for light dimming when used with incandescent lights. However, when the TRIAC dimmers are used with more efficient LEDs, it is often difficult to meet the requirements of TRIAC dimmers in holding currents due to the reduced input power needed to achieve equivalent illumination to that of incandescent lights. Therefore, conventional LED lighting systems often utilize bleeder units to provide compensation in order to satisfy the requirements of TRIAC dimmers in holding currents.
Additionally, certain TRIAC dimmers have a threshold voltage for current conduction in one direction and another threshold voltage for current conduction in another direction, with these threshold voltages being different in magnitude. The different threshold voltages can cause the TRIAC dimmers to process differently positive and negative values in the AC input signal and thus generate positive and negative waveforms of different sizes. Such difference in waveform size can cause flickering of the LEDs.
The TRIAC 110 includes three terminals, one terminal of which is configured to receive the alternating current (AC) input voltage 180 (e.g., VAC) through the terminal 102, another terminal of which is connected to a terminal of the rectifier 150 through the terminal 104, and yet another terminal of which is connected to a terminal of the DIAC 120. The capacitor 140 (e.g., capacitor Ct) includes two terminals, one terminal of which is connected to the terminal of the TRIAC 110 and another terminal of which is connected to one terminal of the variable resistor 130 (e.g., variable resistor Rt). Another terminal of the variable resistor 130 (e.g., variable resistor Rt) is configured to receive the AC input voltage 180 (e.g., VAC) through the terminal 102. The DIAC 120 includes two terminals, one terminal of which is connected to the terminal of the TRIAC 110 and another terminal of which is connected to both the terminal of the variable resistor 130 (e.g., variable resistor Rt) and the terminal of the capacitor 140 (e.g., capacitor Ct).
When the AC input voltage 180 (e.g., VAC) is in the positive half cycle during which the AC input voltage 180 (e.g., VAC) is larger than zero, the voltage at the node T1 is higher than the voltage at the node T2 so that the RC charging circuit that includes the variable resistor 130 (e.g., variable resistor Rt) and the capacitor 140 (e.g., capacitor CO charges the capacitor 140 (e.g., capacitor Ct). The voltage drop between two terminals of the capacitor 140 (e.g., capacitor Ct) is equal to the voltage at the node G minus the voltage at the node T2. If the voltage drop between two terminals of the capacitor 140 (e.g., capacitor Ct) becomes larger than a predetermined positive-direction voltage that is equal to a positive-direction threshold voltage (e.g., VBD), the DIAC 120 becomes turned on and the TRIAC 110 is also turned on, so the voltage at the node T1 and the voltage at the node T2 become equal, causing the capacitor 140 (e.g., capacitor Ct) to discharge through the variable resistor 130 (e.g., variable resistor Rt). The positive-direction threshold voltage (e.g., VBD) is larger than zero volts (e.g., being equal to about 30 volts).
When the AC input voltage 180 (e.g., VAC) is in the negative half cycle during which the AC input voltage 180 (e.g., VAC) is smaller than zero, the voltage at the node T1 is lower than the voltage at the node T2 so that the RC charging circuit that includes the variable resistor 130 (e.g., variable resistor Rt) and the capacitor 140 (e.g., capacitor Ct) charges the capacitor 140 (e.g., capacitor Ct). The voltage drop between two terminals of the capacitor 140 (e.g., capacitor Ct) is equal to the voltage at the node G minus the voltage at the node T2. If the voltage drop between two terminals of the capacitor 140 (e.g., capacitor Ct) becomes less than a predetermined negative-direction voltage that is equal to a negative-direction threshold voltage (e.g., VRD) multiplied by −1, the DIAC 120 becomes turned on and the TRIAC 110 is also turned on, so the voltage at the node T1 and the voltage at the node T2 become equal, causing the capacitor 140 (e.g., capacitor Ct) to discharge through the variable resistor 130 (e.g., variable resistor Rt). The negative-direction threshold voltage (e.g., VRD) is larger than zero.
If the current that flows though the TRIAC 110 is larger than a holding current of the TRIAC 110, the TRIAC 110 remains turned on, and if the current that flows though the TRIAC 110 is smaller than the holding current of the TRIAC 110, the TRIAC 110 becomes turned off. Additionally, the variable resistor 130 (e.g., variable resistor Rt) is adjusted to change the time duration that is needed to charge or discharge the capacitor 140 (e.g., capacitor Ct), thus also changing the phase range within which the waveform of the AC input voltage 180 (e.g., VAC) is clipped by the TRIAC dimmer 100.
As shown in
As an example, the positive-direction threshold voltage VBD is not equal to the negative-direction threshold voltage VRD, so given the same resistance value for the variable resistor Rt, the phase range within which the waveform of the AC input voltage VAC is clipped by the TRIAC dimmer 100 during the positive half cycle of the AC input voltage VAC is not equal to the phase range within which the waveform of the AC input voltage VAC is clipped by the TRIAC dimmer 100 during the negative half cycle of the AC input voltage VAC. For example, if the positive-direction threshold voltage VBD is significantly different from the negative-direction threshold voltage VRD, the TRIAC dimmer 100 generates a waveform during the positive half cycle of the AC input voltage VAC and a waveform during the negative half cycle of the AC input voltage VAC, wherein the sizes of these two waveforms are significantly different, causing flickering of the one or more LEDs 190.
Hence it is highly desirable to improve the techniques related to LED lighting systems.
Certain embodiments of the present invention are directed to circuits. More particularly, some embodiments of the invention provide systems and methods for controlling currents. Merely by way of example, some embodiments of the invention have been applied to light emitting diodes (LEDs). But it would be recognized that the invention has a much broader range of applicability.
According to some embodiments, a system for controlling one or more light emitting diodes includes: a phase detector configured to process information associated with a rectified voltage generated by a rectifier and related to a TRIAC dimmer, the rectified voltage corresponding to a first waveform during a first half cycle of an AC voltage and corresponding to a second waveform during a second half cycle of the AC voltage, the phase detector being further configured to generate a phase detection signal representing a first time duration during which the first waveform indicates that the rectified voltage is larger than a predetermined threshold and representing a second time duration during which the second waveform indicates that the rectified voltage is larger than the predetermined threshold; a mode detector configured to process information associated with the rectified voltage, determine whether the TRIAC dimmer is a leading-edge TRIAC dimmer or a trailing-edge TRIAC dimmer based on at least information associated with the rectified voltage, and generate a mode detection signal that indicates whether the TRIAC dimmer is the leading-edge TRIAC dimmer or the trailing-edge TRIAC dimmer; a modified signal generator configured to receive the phase detection signal from the phase detector and the mode detection signal from the mode detector, modify the phase detection signal based at least in part on the mode detection signal, and generate a modified signal representing a third time duration corresponding to the first half cycle of the AC voltage and a fourth time duration corresponding to the second half cycle of the AC voltage; and a current controller configured to receive the modified signal, the current controller being further configured to control, based at least in part of the modified signal, a first current flowing through one or more light emitting diodes configured to receive the rectified voltage; wherein: the first time duration and the second time duration are different in magnitude; and the third time duration and the fourth time duration are the same in magnitude.
According to certain embodiments, a system for controlling one or more light emitting diodes includes: a phase detector configured to process information associated with a rectified voltage generated by a rectifier and related to a TRIAC dimmer, the rectified voltage corresponding to a first waveform during a first half cycle of an AC voltage and corresponding to a second waveform during a second half cycle of the AC voltage, the signal detector being further configured to generate a phase detection signal representing a first time duration during which the first waveform indicates that the rectified voltage is larger than a predetermined threshold and representing a second time duration during which the second waveform indicates that the rectified voltage is larger than the predetermined threshold; a mode detector configured to process information associated with the rectified voltage, determine whether the TRIAC dimmer is a leading-edge TRIAC dimmer or a trailing-edge TRIAC dimmer based on at least information associated with the rectified voltage, and generate a mode detection signal that indicates whether the TRIAC dimmer is the leading-edge TRIAC dimmer or the trailing-edge TRIAC dimmer; and a modified signal generator configured to receive the phase detection signal from the phase detector and the mode detection signal from the mode detector, the modified signal generator being further configured to generate, based at least in part on the phase detection signal and the mode detection signal, a modified signal representing a third time duration corresponding to the first half cycle of the AC voltage and a fourth time duration corresponding to the second half cycle of the AC voltage; wherein: the first time duration is smaller than the second time duration in magnitude; the third time duration is equal to the first time duration in magnitude; the fourth time duration is smaller than the second duration in magnitude; and the third time duration and the fourth time duration are equal in magnitude.
According to some embodiments, a method for controlling one or more light emitting diodes includes: processing information associated with a rectified voltage related to a TRIAC dimmer, the rectified voltage corresponding to a first waveform during a first half cycle of an AC voltage and corresponding to a second waveform during a second half cycle of the AC voltage; generating a phase detection signal representing a first time duration during which the first waveform indicates that the rectified voltage is larger than a predetermined threshold and representing a second time duration during which the second waveform indicates that the rectified voltage is larger than the predetermined threshold; determining whether the TRIAC dimmer is a leading-edge TRIAC dimmer or a trailing-edge TRIAC dimmer based on at least information associated with the rectified voltage; generating a mode detection signal that indicates whether the TRIAC dimmer is the leading-edge TRIAC dimmer or the trailing-edge TRIAC dimmer; receiving the phase detection signal and the mode detection signal; modifying the phase detection signal based at least in part on the mode detection signal; generating a modified signal representing a third time duration corresponding to the first half cycle of the AC voltage and a fourth time duration corresponding to the second half cycle of the AC voltage; receiving the modified signal; and controlling, based at least in part of the modified signal, a first current flowing through one or more light emitting diodes configured to receive the rectified voltage; wherein: the first time duration and the second time duration are different in magnitude; and the third time duration and the fourth time duration are the same in magnitude.
According to certain embodiments, a method for controlling one or more light emitting diodes includes: processing information associated with a rectified voltage related to a TRIAC dimmer, the rectified voltage corresponding to a first waveform during a first half cycle of an AC voltage and corresponding to a second waveform during a second half cycle of the AC voltage; generating a phase detection signal representing a first time duration during which the first waveform indicates that the rectified voltage is larger than a predetermined threshold and representing a second time duration during which the second waveform indicates that the rectified voltage is larger than the predetermined threshold; determining whether the TRIAC dimmer is a leading-edge TRIAC dimmer or a trailing-edge TRIAC dimmer based on at least information associated with the rectified voltage; generating a mode detection signal that indicates whether the TRIAC dimmer is the leading-edge TRIAC dimmer or the trailing-edge TRIAC dimmer; receiving the phase detection signal and the mode detection signal; and generating, based at least in part on the phase detection signal and the mode detection signal, a modified signal representing a third time duration corresponding to the first half cycle of the AC voltage and a fourth time duration corresponding to the second half cycle of the AC voltage; wherein: the first time duration is smaller than the second time duration in magnitude; the third time duration is equal to the first time duration in magnitude; the fourth time duration is smaller than the second duration in magnitude; and the third time duration and the fourth time duration are equal in magnitude.
Depending upon embodiment, one or more benefits may be achieved. These benefits and various additional objects, features and advantages of the present invention can be fully appreciated with reference to the detailed description and accompanying drawings that follow.
Certain embodiments of the present invention are directed to circuits. More particularly, some embodiments of the invention provide systems and methods for controlling currents. Merely by way of example, some embodiments of the invention have been applied to light emitting diodes (LEDs). But it would be recognized that the invention has a much broader range of applicability.
As shown by the waveforms 310 and 320, if the rectified voltage VIN is larger than a threshold voltage Vx, the logic signal Dim_on is at a logic high level, and if the rectified voltage VIN is smaller than the threshold voltage Vx, the logic signal Dim_on is at a logic low level according to certain embodiments. As an example, the threshold voltage Vx is equal to a predetermined voltage value that is selected from a range from 10 volts to 30 volts. For example, during a positive half cycle of the AC input voltage VAC, the logic signal Dim_on remains at the logic high level during a time duration that corresponds to a phase range ϕ1. As an example, during a negative half cycle of the AC input voltage VAC, the logic signal Dim_on remains at the logic high level during a time duration that corresponds to a phase range ϕ2. As shown in
As shown by the waveforms 310 and 330, if the rectified voltage VIN is larger than a threshold voltage Vo, the output current (e.g., Iled) is at a high current level 332, and if the rectified voltage VIN is smaller than the threshold voltage Vo, the output current (e.g., Iled) is at a low current level 334 (e.g., zero) according to some embodiments. As an example, the threshold voltage Vo is higher than the threshold voltage Vx. For example, in the positive half cycle of the AC input voltage VAC, the time duration during which the output current (e.g., Iled) is at the current level 332 can be determined by the time duration during which the logic signal Dim_on is at the logic high level, so the time duration during which the logic signal Dim_on is at the logic high level is used to represent the time duration during which the output current (e.g., Iled) is at the current level 332. As an example, in the negative half cycle of the AC input voltage VAC, the time duration during which the output current (e.g., Iled) is at the current level 332 can be determined by the time duration during which the logic signal Dim_on is at the logic high level, so the time duration during which the logic signal Dim_on is at the logic high level is used to represent the time duration during which the output current (e.g., Iled) is at the current level 332.
In some examples, the phase range ϕ1 and the phase range ϕ2 are not equal, so the time duration during which the output current (e.g., Iled) is at the current level 332 in the positive half cycle of the AC input voltage VAC and the time duration during which the output current (e.g., Iled) is at the current level 332 in the negative half cycle of the AC input voltage VAC are also different, causing the average of the output current (e.g., Iled) in the positive half cycle of the AC input voltage VAC and the average of the output current (e.g., Iled) in the negative half cycle of the AC input voltage VAC to be different. In certain examples, if the average of the output current (e.g., Iled) in the positive half cycle of the AC input voltage VAC and the average of the output current (e.g., Iled) in the negative half cycle of the AC input voltage VAC are significantly different, human eyes can perceive flickering of the one or more LEDs.
In some embodiments, after the system 400 is powered on, an alternating current (AC) input voltage 472 (e.g., VAC) is received by the TRIAC dimmer 470 and rectified by the rectifier 480 (e.g., BD1) to generate a rectified voltage 483 (e.g., VIN). For example, the rectified voltage 483 (e.g., VIN) is used to control an output current 491 that flows through the one or more LEDs 490. In certain embodiments, the rectified voltage 483 (e.g., VIN) is received by the voltage detection unit 460, which in response outputs a sensing signal 461 (e.g., LS) to the phase detection unit 410 and the mode detection unit 420. For example, the voltage detection unit 460 includes a resistor 462 (e.g., R1) and a resistor 464 (e.g., R2), and the resistors 462 and 464 form a voltage divider. As an example, the resistor 462 (e.g., R1) and the resistor 464 (e.g., R2) are in series and are biased between the rectified voltage 483 (e.g., VIN) and a ground voltage.
According to certain embodiments, the mode detection unit 420 receives the sensing signal 461 (e.g., LS), determines whether the TRIAC dimmer 470 is a leading-edge TRIAC dimmer or a trailing-edge TRIAC dimmer based at least in part on the sensing signal 461 (e.g., LS), generates a mode signal 421 that indicates whether the TRIAC dimmer 470 is a leading-edge TRIAC dimmer or a trailing-edge TRIAC dimmer, and output the mode signal 421 to the bleeder current control and generation unit 450 and the waveform adjustment unit 430. For example, the mode detection unit 420 generates the mode signal 421 based at least in part on the sensing signal 461 (e.g., LS). According to some embodiments, the bleeder current control and generation unit 450 receives the mode signal 421 and generates a bleeder current 451 based at least in part on the mode signal 421. As an example, the bleeder current 451 is used to ensure that the current flowing through the TRIAC dimmer 470 does not fall below a holding current of the TRIAC dimmer 470 in order to maintain normal operation of the TRIAC dimmer 470.
In some embodiments, the phase detection unit 410 receives the sensing signal 461 (e.g., LS), generates a logic signal 411 (e.g., Dim_on) based at least in part on the sensing signal 461 (e.g., LS), and outputs the logic signal 411 (e.g., Dim_on) to the waveform adjustment unit 430. For example, if the sensing signal 461 (e.g., LS) is larger than a threshold signal, the logic signal 411 (e.g., Dim_on) is at a logic high level. As an example, if the sensing signal 461 (e.g., LS) is smaller than the threshold signal, the logic signal 411 (e.g., Dim_on) is at a logic low level.
In certain embodiments, the waveform adjustment unit 430 receives the logic signal 411 (e.g., Dim_on) and the mode signal 421, generates a logic signal 432 (e.g., Dim_on′) by modifying the logic signal 411 (e.g., Dim_on) based at least in part on the mode signal 421, and outputs the logic signal 432 (e.g., Dim_on′) to the control unit 440 for LED output current. For example, the logic signal 411 (e.g., Dim_on) is modified based at least in part on the mode signal 421 in order to eliminate the effect of different sizes of the waveforms of the rectified voltage 483 (e.g., VIN) during the positive half cycle of the AC input voltage 472 (e.g., VAC) and during the negative half cycle of the AC input voltage 472 (e.g., VAC).
According to certain embodiments, the control unit 440 for LED output current receives the logic signal 432 (e.g., Dim_on′) and uses the logic signal 432 (e.g., Dim_on′) to control the output current 491 that flows through the one or more LEDs 490. For example, the control unit 440 for LED output current includes three terminals, one terminal of which is configured to receive the logic signal 432 (e.g., Dim_on′), another terminal of which is biased to the ground voltage, and yet another terminal of which is connected to one terminal of the one or more LEDs 490. As an example, the one or more LEDs 490 includes another terminal configured to receive the rectified voltage 483 (e.g., VIN).
In certain embodiments, the edge detection unit 510 receives the logic signal 411 (e.g., Dim_on), detects a rising edge or a falling edge of the logic signal 411 (e.g., Dim_on), generate a detection signal 511 indicating the occurrence of the rising edge or the falling edge of the logic signal 411 (e.g., Dim_on), and output the detection signal 511 to the signal processing unit 520. For example, if the edge detection unit 510 detects a rising edge of the logic signal 411 (e.g., Dim_on), the edge detection unit 510 generates the detection signal 511 to indicate the occurrence of the rising edge of the logic signal 411 (e.g., Dim_on). As an example, if the edge detection unit 510 detects a falling edge of the logic signal 411 (e.g., Dim_on), the edge detection unit 510 generates the detection signal 511 to indicate the occurrence of the falling edge of the logic signal 411 (e.g., Dim_on). In some examples, the detection signal 511 indicates whether a change of the logic signal 411 (e.g., Dim_on) has occurred and also indicates whether the change of the logic signal 411 (e.g., Dim_on) corresponds to a rising edge of the logic signal 411 (e.g., Dim_on) or a falling edge of the logic signal 411 (e.g., Dim_on).
In some embodiments, the signal processing unit 520 receives the detection signal 511, the mode signal 421, and the logic signal 411 (e.g., Dim_on), generates a control signal 521 based at least in part on the detection signal 511, the mode signal 421, and the logic signal 411 (e.g., Dim_on), and outputs the control signal 521 to the signal outputting unit 530. For example, the signal processing unit 520 includes the delay sub-unit 522 and the control sub-unit 524.
According to certain embodiments, the delay sub-unit 522 receives the detection signal 511 and the mode signal 421, generates a delayed signal 523 (e.g., Dim_on_T) based at least in part on the detection signal 511 and the mode signal 421, and outputs the delayed signal 523 to the control sub-unit 524. In some examples, if the mode signal 421 indicates that the TRIAC dimmer 470 is a leading-edge TRIAC dimmer, the delay sub-unit 522 generates the delayed signal 523 (e.g., Dim_on_T) by delaying, by a predetermined delay of time, the rising edge of the logic signal 411 (e.g., Dim_on) as indicated by the detection signal 511. In certain examples, if the mode signal 421 indicates that the TRIAC dimmer 470 is a trailing-edge TRIAC dimmer, the delay sub-unit 522 generates the delayed signal 523 (e.g., Dim_on_T) by delaying, by the predetermined delay of time, the falling edge of the logic signal 411 (e.g., Dim_on) as indicated by the detection signal 511. For example, the predetermined delay of time is equal to a half cycle of the AC input voltage 472 (e.g., VAC) in time duration.
According to some embodiments, the control sub-unit 524 receives the delayed signal 523 and the logic signal 411 (e.g., Dim_on), generates the control signal 521 based at least in part on the delayed signal 523 and the logic signal 411 (e.g., Dim_on), and outputs the control signal 521 to the signal outputting unit 530. In certain examples, the control signal 521 is the same as the delayed signal 523, except that during the first half cycle of the AC input voltage 472 (e.g., VAC), the control signal 521 is the same as the logic signal 411 (e.g., Dim_on). For example, the first half cycle of the AC input voltage 472 (e.g., VAC) is either a positive half cycle or a negative half cycle of the AC input voltage 472 (e.g., VAC). As an example, the first half cycle of the AC input voltage 472 (e.g., VAC) occurs immediately after the system 400 is powered on.
In certain embodiments, the signal outputting unit 530 receives the control signal 521 and the logic signal 411 (e.g., Dim_on), generates the logic signal 432 (e.g., Dim_on′) based at least in part on the control signal 521 and the logic signal 411 (e.g., Dim_on), and outputs the logic signal 432 (e.g., Dim_on′) to the control unit 440 for LED output current. For example, the signal outputting unit 530 includes an AND gate 532. As an example, the AND gate 532 receives the control signal 521 and the logic signal 411 (e.g., Dim_on) and generates the logic signal 432 (e.g., Dim_on′).
As discussed above and further emphasized here,
In some embodiments, the control signal generator 610 receives the logic signal 432 (e.g., Dim_on′), generates a control signal 612 based at least in part on the logic signal 432 (e.g., Dim_on′), and outputs the control signal 612 to a gate terminal of the transistor 620. In certain examples, the transistor 620 includes the gate terminal, a drain terminal, and a source terminal. For example, the drain terminal of the transistor 620 is connected to one terminal of the one or more LEDs 490. As an example, the source terminal of the transistor 620 is connected to a terminal of the resistor 640, which also includes another terminal biased to the ground voltage. In certain embodiments, the gate terminal of the transistor 620 is also connected to a terminal of the switch 630, which also includes another terminal biased to the ground voltage. In some examples, the switch 630 receives the logic signal 432 (e.g., Dim_on′). For example, if the logic signal 432 (e.g., Dim_on′) is at the logic high level, the switch 630 is open. As an example, if the logic signal 432 (e.g., Dim_on′) is at the logic low level, the switch 630 is closed.
According to some embodiments, if the logic signal 432 (e.g., Dim_on′) is at the logic low level, the switch 630 is closed, so that the gate terminal of the transistor 620 is biased to the ground voltage. For example, if the gate terminal of the transistor 620 is biased to the ground voltage, the transistor 620 is turned off so that the output current 491 that flows through the one or more LEDs 490 is not allowed to be generated (e.g., the output current 491 being equal to zero).
According to certain embodiments, if the logic signal 432 (e.g., Dim_on′) is at the logic high level, the switch 630 is open, so that the voltage of the gate terminal of the transistor 620 is controlled by the control signal 612. For example, the control signal 612 is generated by the control signal generator 610 based at least in part on the logic signal 432 (e.g., Dim_on′). As an example, the control signal 612 is generated at a constant voltage level, and the constant voltage level of the control signal 612 is used by the transistor 620 to generate the output current 491 at a constant current level for a time duration during which the rectified voltage 483 (e.g., VIN) exceeds a threshold voltage that is needed to provide the forward bias voltage for the one or more LEDs 490.
In some embodiments, the control signal generator 710 receives the logic signal 432 (e.g., Dim_on′), generates a control signal 712 (e.g., a drive signal) based at least in part on the logic signal 432 (e.g., Dim_on′), and outputs the control signal 712 to a gate terminal of the transistor 720. In certain examples, the transistor 720 includes the gate terminal, a drain terminal, and a source terminal. For example, the drain terminal of the transistor 720 is connected to one terminal of the one or more LEDs 490. As an example, the source terminal of the transistor 620 is connected to a terminal of the resistor 740, which also includes another terminal biased to the ground voltage. In certain embodiments, the gate terminal of the transistor 720 is also connected to a terminal of the switch 730, which also includes another terminal biased to the ground voltage. In some examples, the switch 730 receives an operation signal 752. For example, if the operation signal 752 is at the logic high level, the switch 730 is open. As an example, if the operation signal 752 is at the logic low level, the switch 730 is closed.
According to certain embodiments, the operation signal generator 750 receives the logic signal 432 (e.g., Dim_on′), generates the operation signal 752 based at least in part on the logic signal 432 (e.g., Dim_on′), and outputs the operation signal 752 to the switch 730. In some examples, the operation signal generator 750 includes a buffer. In certain examples, when the logic signal 432 (e.g., Dim_on′) changes from the logic low level to the logic high level, the operation signal 752 also changes from the logic low level to the logic high level. For example, before the logic signal 432 (e.g., Dim_on′) changes from the logic high level to the logic low level, the operation signal 752 changes from the logic high level to the logic low level. As an example, when the logic signal 432 (e.g., Dim_on′) changes from the logic high level to the logic low level, the operation signal 752 changes from the logic high level to the logic low level. For example, after the logic signal 432 (e.g., Dim_on′) changes from the logic high level to the logic low level, the operation signal 752 changes from the logic high level to the logic low level.
In some embodiments, if the operation signal 752 is at the logic low level, the switch 730 is closed, so that the gate terminal of the transistor 720 is biased to the ground voltage. For example, if the gate terminal of the transistor 720 is biased to the ground voltage, the transistor 720 is turned off so that the output current 491 that flows through the one or more LEDs 490 is not allowed to be generated (e.g., the output current 491 being equal to zero). In certain embodiments, if the operation signal 752 is at the logic high level, the switch 730 is open, so that the voltage of the gate terminal of the transistor 720 is controlled by the control signal 712. For example, the control signal 712 is generated by the control signal generator 710 based at least in part on the logic signal 432 (e.g., Dim_on′). As an example, the control signal 712 is generated at a constant voltage level, and the constant voltage level of the control signal 712 is used by the transistor 720 to generate the output current 491 at a constant current level. For example, the constant current level of the output current 491 is determined at least in part by the constant voltage level of the control signal 712.
As shown by the waveforms 883 and 811, if the rectified voltage 483 (e.g., VIN) is larger than a threshold voltage Vx, the logic signal 411 (e.g., Dim_on) is at a logic high level, and if the rectified voltage 483 (e.g., VIN) is smaller than the threshold voltage Vx, the logic signal 411 (e.g., Dim_on) is at a logic low level according to certain embodiments. As an example, the threshold voltage Vx is equal to a predetermined voltage value that is selected from a range from 10 volts to 30 volts. For example, during a negative half cycle of the AC input voltage 472 (e.g., VAC), the logic signal 411 (e.g., Dim_on) remains at the logic high level during a time duration that corresponds to a phase range ϕ1. As an example, during a positive half cycle of the AC input voltage 472 (e.g., VAC), the logic signal 411 (e.g., Dim_on) remains at the logic high level during a time duration that corresponds to a phase range ϕ2. As shown in
As shown by the waveforms 811 and 823, if the mode signal 421 indicates that the TRIAC dimmer 470 is a leading-edge TRIAC dimmer, the delayed signal 523 (e.g., Dim_on_T) is generated by delaying, by a predetermined delay of time (e.g., Td, a rising edge of the logic signal 411 (e.g., Dim_on) according to some embodiments. For example, the predetermined delay of time (e.g., Td) is equal to a half cycle of the AC input voltage 472 (e.g., VAC) in time duration. As an example, the phase range ϕ2 is larger than the phase range ϕ1, and the phase range ϕ2 minus the phase range ϕ1 is equal to Δϕ. As shown by the waveforms 811, 823 and 821, the control signal 521 is the same as the delayed signal 523, except that during the first half cycle of the AC input voltage 472 (e.g., VAC), the control signal 521 is the same as the logic signal 411 (e.g., Dim_on), according to certain embodiments.
As shown by the waveforms 811, 821 and 832, if the logic signal 411 (e.g., Dim_on) or the control signal 521 is at the logic low level, the logic signal 432 (e.g., Dim_on′) is at the logic low level, and if the logic signal 411 (e.g., Dim_on) and the control signal 521 both are at the logic high level, the logic signal 432 (e.g., Dim_on′) is at the logic high level, according to some embodiments. For example, if the logic signal 411 (e.g., Dim_on) and the control signal 521 both are at the logic low level, the logic signal 432 (e.g., Dim_on′) is at the logic low level. In certain examples, the pulse width of the logic signal 432 (e.g., Dim_on′) during a negative half cycle of the AC input voltage 472 (e.g., VAC) is equal to the pulse width of the logic signal 432 (e.g., Dim_on′) during a positive half cycle of the AC input voltage 472 (e.g., VAC). As an example, during the negative half cycle of the AC input voltage 472 (e.g., VAC), the pulse width of the logic signal 432 (e.g., Dim_on′) corresponds to the phase range ϕ1, and during the positive half cycle of the AC input voltage 472 (e.g., VAC), the pulse width of the logic signal 432 (e.g., Dim_on′) also corresponds to the phase range ϕ1.
As shown by the waveforms 832 and 891, the logic signal 432 (e.g., Dim_on′) is used to generate the output current 491 (e.g., Iled) according to certain embodiments. In some examples, the output current 491 (e.g., Iled) alternates between a high current level 893 and a low current level 895 (e.g. zero) to form one or more pulses at which the output current 491 (e.g., Iled) remains at the high current level 893. For example, when the logic signal 432 (e.g., Dim_on′) changes from the logic low level to the logic high level, the output current 491 (e.g., Iled) changes from the low current level 895 (e.g. zero) to the high current level 893. As an example, a predetermined period of time before the logic signal 432 (e.g., Dim_on′) changes from the logic high level to the logic low level, the output current 491 (e.g., Iled) changes from the high current level 893 to the low current level 895 (e.g. zero). For example, the output current 491 (e.g., Iled) changes from the high current level 893 to the low current level 895 (e.g. zero) when the rectified voltage 483 (e.g., VIN) changes from being larger than a threshold voltage Vo to being smaller than the threshold voltage Vo. As an example, the threshold voltage Vo is higher than the threshold voltage Vx. In certain examples, the pulse width of the output current 491 (e.g., Iled) during a negative half cycle of the AC input voltage 472 (e.g., VAC) is equal to the pulse width of the output current 491 (e.g., Iled) during a positive half cycle of the AC input voltage 472 (e.g., VAC). For example, the time duration during which the output current 491 (e.g., Iled) is at the current level 893 in the negative half cycle of the AC input voltage 472 (e.g., VAC) and the time duration during which the output current 491 (e.g., Iled) is at the current level 893 in the positive half cycle of the AC input voltage 472 (e.g., VAC) are the same. As an example, the average of the output current 491 (e.g., Iled) in the negative half cycle of the AC input voltage 472 (e.g., VAC) and the average of the output current 491 (e.g., Iled) in the positive half cycle of the AC input voltage 472 (e.g., VAC) are equal, preventing flickering of the one or more LEDs 490.
As shown by the waveforms 983 and 911, if the rectified voltage 483 (e.g., VIN) is larger than a threshold voltage Vx, the logic signal 411 (e.g., Dim_on) is at a logic high level, and if the rectified voltage 483 (e.g., VIN) is smaller than the threshold voltage Vx, the logic signal 411 (e.g., Dim_on) is at a logic low level according to certain embodiments. As an example, the threshold voltage Vx is equal to a predetermined voltage value that is selected from a range from 10 volts to 30 volts. For example, during a negative half cycle of the AC input voltage 472 (e.g., VAC), the logic signal 411 (e.g., Dim_on) remains at the logic high level during a time duration that corresponds to a phase range ϕ1. As an example, during a positive half cycle of the AC input voltage 472 (e.g., VAC), the logic signal 411 (e.g., Dim_on) remains at the logic high level during a time duration that corresponds to a phase range ϕ2. As shown in
As shown by the waveforms 911 and 923, if the mode signal 421 indicates that the TRIAC dimmer 470 is a trailing-edge TRIAC dimmer, the delayed signal 523 (e.g., Dim_on_T) is generated by delaying, by a predetermined delay of time (e.g., Td), a falling edge of the logic signal 411 (e.g., Dim_on) according to some embodiments. For example, the predetermined delay of time (e.g., Td) is equal to a half cycle of the AC input voltage 472 (e.g., VAC) in time duration. As an example, the phase range ϕ2 is larger than the phase range ϕ1, and the phase range ϕ2 minus the phase range ϕ1 is equal to Δϕ. As shown by the waveforms 911, 923 and 921, the control signal 521 is the same as the delayed signal 523, except that during the first half cycle of the AC input voltage 472 (e.g., VAC), the control signal 521 is the same as the logic signal 411 (e.g., Dim_on), according to certain embodiments.
As shown by the waveforms 911, 921 and 932, if the logic signal 411 (e.g., Dim_on) or the control signal 521 is at the logic low level, the logic signal 432 (e.g., Dim_on′) is at the logic low level, and if the logic signal 411 (e.g., Dim_on) and the control signal 521 both are at the logic high level, the logic signal 432 (e.g., Dim_on′) is at the logic high level, according to some embodiments. For example, if the logic signal 411 (e.g., Dim_on) and the control signal 521 both are at the logic low level, the logic signal 432 (e.g., Dim_on′) is at the logic low level. In certain examples, the pulse width of the logic signal 432 (e.g., Dim_on′) during a negative half cycle of the AC input voltage 472 (e.g., VAC) is equal to the pulse width of the logic signal 432 (e.g., Dim_on′) during a positive half cycle of the AC input voltage 472 (e.g., VAC). As an example, during the negative half cycle of the AC input voltage 472 (e.g., VAC), the pulse width of the logic signal 432 (e.g., Dim_on′) corresponds to the phase range ϕ1, and during the positive half cycle of the AC input voltage 472 (e.g., VAC), the pulse width of the logic signal 432 (e.g., Dim_on′) also corresponds to the phase range ϕ1.
As shown by the waveforms 932 and 991, the logic signal 432 (e.g., Dim_on′) is used to generate the output current 491 (e.g., bed) according to certain embodiments. In some examples, the output current 491 (e.g., Iled) alternates between a high current level 993 and a low current level 995 (e.g. zero) to form one or more pulses at which the output current 491 (e.g., Iled) remains at the high current level 993. For example, a predetermined period of time after the logic signal 432 (e.g., Dim_on′) changes from the logic low level to the logic high level, the output current 491 (e.g., Iled) changes from the low current level 995 (e.g. zero) to the high current level 993. As an example, the output current 491 (e.g., Iled) changes from the low current level 995 (e.g. zero) to the high current level 993 when the rectified voltage 483 (e.g., VIN) changes from being smaller than a threshold voltage Vo to being larger than the threshold voltage Vo. As an example, the threshold voltage Vo is higher than the threshold voltage Vx. For example, when the logic signal 432 (e.g., Dim_on′) changes from the logic high level to the logic low level, the output current 491 (e.g., Iled) changes from the high current level 993 to the low current level 995 (e.g. zero). In certain examples, the pulse width of the output current 491 (e.g., Iled) during a negative half cycle of the AC input voltage 472 (e.g., VAC) is equal to the pulse width of the output current 491 (e.g., Iled) during a positive half cycle of the AC input voltage 472 (e.g., VAC). For example, the time duration during which the output current 491 (e.g., Iled) is at the current level 993 in the negative half cycle of the AC input voltage 472 (e.g., VAC) and the time duration during which the output current 491 (e.g., Iled) is at the current level 993 in the positive half cycle of the AC input voltage 472 (e.g., VAC) are the same. As an example, the average of the output current 491 (e.g., Iled) in the negative half cycle of the AC input voltage 472 (e.g., VAC) and the average of the output current 491 (e.g., Iled) in the positive half cycle of the AC input voltage 472 (e.g., VAC) are equal, preventing flickering of the one or more LEDs 490.
As shown by the waveforms 1083 and 1011, if the rectified voltage 483 (e.g., VIN) is larger than a threshold voltage Vx, the logic signal 411 (e.g., Dim_on) is at a logic high level, and if the rectified voltage 483 (e.g., VIN) is smaller than the threshold voltage Vx, the logic signal 411 (e.g., Dim_on) is at a logic low level according to certain embodiments. As an example, the threshold voltage Vx is equal to a predetermined voltage value that is selected from a range from 10 volts to 30 volts. For example, during a negative half cycle of the AC input voltage 472 (e.g., VAC), the logic signal 411 (e.g., Dim_on) remains at the logic high level during a time duration that corresponds to a phase range ϕ1. As an example, during a positive half cycle of the AC input voltage 472 (e.g., VAC), the logic signal 411 (e.g., Dim_on) remains at the logic high level during a time duration that corresponds to a phase range ϕ2. As shown in
As shown by the waveforms 1011 and 1023, if the mode signal 421 indicates that the TRIAC dimmer 470 is a leading-edge TRIAC dimmer, the delayed signal 523 (e.g., Dim_on_T) is generated by delaying, by a predetermined delay of time (e.g., Td), a rising edge of the logic signal 411 (e.g., Dim_on) according to some embodiments. For example, the predetermined delay of time (e.g., Td) is equal to a half cycle of the AC input voltage 472 (e.g., VAC) in time duration. As an example, the phase range ϕ2 is larger than the phase range ϕ1, and the phase range ϕ2 minus the phase range ϕ1 is equal to Δϕ. As shown by the waveforms 1011, 1023 and 1021, the control signal 521 is the same as the delayed signal 523, except that during the first half cycle of the AC input voltage 472 (e.g., VAC), the control signal 521 is the same as the logic signal 411 (e.g., Dim_on), according to certain embodiments.
As shown by the waveforms 1011, 1021 and 1032, if the logic signal 411 (e.g., Dim_on) or the control signal 521 is at the logic low level, the logic signal 432 (e.g., Dim_on′) is at the logic low level, and if the logic signal 411 (e.g., Dim_on) and the control signal 521 both are at the logic high level, the logic signal 432 (e.g., Dim_on′) is at the logic high level, according to some embodiments. For example, if the logic signal 411 (e.g., Dim_on) and the control signal 521 both are at the logic low level, the logic signal 432 (e.g., Dim_on′) is at the logic low level. In certain examples, the pulse width of the logic signal 432 (e.g., Dim_on′) during a negative half cycle of the AC input voltage 472 (e.g., VAC) is equal to the pulse width of the logic signal 432 (e.g., Dim_on′) during a positive half cycle of the AC input voltage 472 (e.g., VAC). As an example, during the negative half cycle of the AC input voltage 472 (e.g., VAC), the pulse width of the logic signal 432 (e.g., Dim_on′) corresponds to the phase range ϕ1, and during the positive half cycle of the AC input voltage 472 (e.g., VAC), the pulse width of the logic signal 432 (e.g., Dim_on′) also corresponds to the phase range ϕ1.
As shown by the waveforms 1032 and 1052, the operation signal 752 is generated based at least in part on the logic signal 432 (e.g., Dim_on′) according to certain embodiments. In some examples, when the logic signal 432 (e.g., Dim_on′) changes from the logic low level to the logic high level, the operation signal 752 also changes from the logic low level to the logic high level. In certain examples, before, when, or after the logic signal 432 (e.g., Dim_on′) changes from the logic high level to the logic low level, the operation signal 752 changes from the logic high level to the logic low level. As an example, when the logic signal 432 (e.g., Dim_on′) changes from the logic high level to the logic low level, the operation signal 752 also changes from the logic high level to the logic low level.
As shown by the waveforms 1052 and 1091, the operation signal 752 is used to generate the output current 491 (e.g., Iled) according to some embodiments. In some examples, the output current 491 (e.g., Iled) alternates between a high current level 1093 and a low current level 1095 (e.g. zero) to form one or more pulses at which the output current 491 (e.g., Iled) remains at the high current level 1093. For example, when the operation signal 752 changes from the logic low level to the logic high level, the output current 491 (e.g., Iled) changes from the low current level 1095 (e.g. zero) to the high current level 1093. As an example, a predetermined period of time before the operation signal 752 changes from the logic high level to the logic low level, the output current 491 (e.g., Iled) changes from the high current level 1093 to the low current level 1095 (e.g. zero). For example, the output current 491 (e.g., Iled) changes from the high current level 1093 to the low current level 1095 (e.g. zero) when the rectified voltage 483 (e.g., VIN) changes from being larger than a threshold voltage Vo to being smaller than the threshold voltage Vo. As an example, the threshold voltage Vo is higher than the threshold voltage Vx. In certain examples, the pulse width of the output current 491 (e.g., Iled) during a negative half cycle of the AC input voltage 472 (e.g., VAC) is equal to the pulse width of the output current 491 (e.g., Iled) during a positive half cycle of the AC input voltage 472 (e.g., VAC). For example, the time duration during which the output current 491 (e.g., Iled) is at the current level 1093 in the negative half cycle of the AC input voltage 472 (e.g., VAC) and the time duration during which the output current 491 (e.g., bed) is at the current level 1093 in the positive half cycle of the AC input voltage 472 (e.g., VAC) are the same. As an example, the average of the output current 491 (e.g., Iled) in the negative half cycle of the AC input voltage 472 (e.g., VAC) and the average of the output current 491 (e.g., Iled) in the positive half cycle of the AC input voltage 472 (e.g., VAC) are equal, preventing flickering of the one or more LEDs 490.
As shown by the waveforms 1183 and 1111, if the rectified voltage 483 (e.g., VIN) is larger than a threshold voltage Vx, the logic signal 411 (e.g., Dim_on) is at a logic high level, and if the rectified voltage 483 (e.g., VIN) is smaller than the threshold voltage Vx, the logic signal 411 (e.g., Dim_on) is at a logic low level according to certain embodiments. As an example, the threshold voltage Vx is equal to a predetermined voltage value that is selected from a range from 10 volts to 30 volts. For example, during a negative half cycle of the AC input voltage 472 (e.g., VAC), the logic signal 411 (e.g., Dim_on) remains at the logic high level during a time duration that corresponds to a phase range ϕ1. As an example, during a positive half cycle of the AC input voltage 472 (e.g., VAC), the logic signal 411 (e.g., Dim_on) remains at the logic high level during a time duration that corresponds to a phase range ϕ2. As shown in
As shown by the waveforms 1111 and 1123, if the mode signal 421 indicates that the TRIAC dimmer 470 is a trailing-edge TRIAC dimmer, the delayed signal 523 (e.g., Dim_on_T) is generated by delaying, by a predetermined delay of time (e.g., Td), a falling edge of the logic signal 411 (e.g., Dim_on) according to some embodiments. For example, the predetermined delay of time (e.g., Td) is equal to a half cycle of the AC input voltage 472 (e.g., VAC) in time duration. As an example, the phase range ϕ2 is larger than the phase range ϕ1, and the phase range ϕ2 minus the phase range ϕ1 is equal to Δϕ. As shown by the waveforms 1111, 1123 and 1121, the control signal 521 is the same as the delayed signal 523, except that during the first half cycle of the AC input voltage 472 (e.g., VAC), the control signal 521 is the same as the logic signal 411 (e.g., Dim_on), according to certain embodiments.
As shown by the waveforms 1111, 1121 and 1132, if the logic signal 411 (e.g., Dim_on) or the control signal 521 is at the logic low level, the logic signal 432 (e.g., Dim_on′) is at the logic low level, and if the logic signal 411 (e.g., Dim_on) and the control signal 521 both are at the logic high level, the logic signal 432 (e.g., Dim_on′) is at the logic high level, according to some embodiments. For example, if the logic signal 411 (e.g., Dim_on) and the control signal 521 both are at the logic low level, the logic signal 432 (e.g., Dim_on′) is at the logic low level. In certain examples, the pulse width of the logic signal 432 (e.g., Dim_on′) during a negative half cycle of the AC input voltage 472 (e.g., VAC) is equal to the pulse width of the logic signal 432 (e.g., Dim_on′) during a positive half cycle of the AC input voltage 472 (e.g., VAC). As an example, during the negative half cycle of the AC input voltage 472 (e.g., VAC), the pulse width of the logic signal 432 (e.g., Dim_on′) corresponds to the phase range ϕ1, and during the positive half cycle of the AC input voltage 472 (e.g., VAC), the pulse width of the logic signal 432 (e.g., Dim_on′) also corresponds to the phase range ϕ1.
As shown by the waveforms 1132 and 1152, the operation signal 752 is generated based at least in part on the logic signal 432 (e.g., Dim_on′) according to certain embodiments. In some examples, when the logic signal 432 (e.g., Dim_on′) changes from the logic low level to the logic high level, the operation signal 752 also changes from the logic low level to the logic high level. In certain examples, before, when, or after the logic signal 432 (e.g., Dim_on′) changes from the logic high level to the logic low level, the operation signal 752 changes from the logic high level to the logic low level. As an example, when the logic signal 432 (e.g., Dim_on′) changes from the logic high level to the logic low level, the operation signal 752 also changes from the logic high level to the logic low level.
As shown by the waveforms 1152 and 1191, the operation signal 752 is used to generate the output current 491 (e.g., Iled) according to some embodiments. In some examples, the output current 491 (e.g., Iled) alternates between a high current level 1193 and a low current level 1195 (e.g. zero) to form one or more pulses at which the output current 491 (e.g., Iled) remains at the high current level 1193. For example, when the operation signal 752 changes from the logic high level to the logic low level, the output current 491 (e.g., Iled) changes from the high current level 1193 to the low current level 1195 (e.g. zero). As an example, a predetermined period of time after the operation signal 752 changes from the logic low level to the logic high level, the output current 491 (e.g., Iled) changes from the low current level 1195 (e.g. zero) to the high current level 1193. For example, the output current 491 (e.g., Iled) changes from the low current level 1195 (e.g. zero) to the high current level 1193 when the rectified voltage 483 (e.g., VIN) changes from being smaller than a threshold voltage Vo to being larger than the threshold voltage Vo. As an example, the threshold voltage Vo is higher than the threshold voltage Vx. In certain examples, the pulse width of the output current 491 (e.g., Iled) during a negative half cycle of the AC input voltage 472 (e.g., VAC) is equal to the pulse width of the output current 491 (e.g., Iled) during a positive half cycle of the AC input voltage 472 (e.g., VAC). For example, the time duration during which the output current 491 (e.g., Iled) is at the current level 1193 in the negative half cycle of the AC input voltage 472 (e.g., VAC) and the time duration during which the output current 491 (e.g., Iled) is at the current level 1193 in the positive half cycle of the AC input voltage 472 (e.g., VAC) are the same. As an example, the average of the output current 491 (e.g., Iled) in the negative half cycle of the AC input voltage 472 (e.g., VAC) and the average of the output current 491 (e.g., Iled) in the positive half cycle of the AC input voltage 472 (e.g., VAC) are equal, preventing flickering of the one or more LEDs 490.
At the process 1210, the logic signal 411 (e.g., Dim_on) is generated based at least in part on the sensing signal 461 (e.g., LS) according to certain embodiments. At the process 1220, the mode signal 421 is generated based at least in part on the sensing signal 461 (e.g., LS) to indicate whether the TRIAC dimmer 470 is a leading-edge TRIAC dimmer or a trailing-edge TRIAC dimmer according to some embodiments.
At the process 1230, the logic signal 432 (e.g., Dim_on′) is generated based at least in part on the logic signal 411 (e.g., Dim_on) and the mode signal 421 according to certain embodiments. In some examples, a rising edge and/or a falling edge of the logic signal 411 (e.g., Dim_on) is detected. In certain examples, using the mode signal 421 and the logic signal 411 (e.g., Dim_on), the control signal 521 is generated based at least in part on the detected rising edge of the logic signal 411 (e.g., Dim_on) or the detected falling edge of the logic signal 411 (e.g., Dim_on).
In some embodiments, using the mode signal 421, the delayed signal 523 (e.g., Dim_on_T) is generated based at least in part on the detected rising edge of the logic signal 411 (e.g., Dim_on) or the detected falling edge of the logic signal 411 (e.g., Dim_on). For example, if the mode signal 421 indicates that the TRIAC dimmer 470 is a leading-edge TRIAC dimmer, the delay sub-unit 522 generates the delayed signal 523 (e.g., Dim_on_T) by delaying, by a predetermined delay of time, the detected rising edge of the logic signal 411 (e.g., Dim_on). As an example, if the mode signal 421 indicates that the TRIAC dimmer 470 is a trailing-edge TRIAC dimmer, the delay sub-unit 522 generates the delayed signal 523 (e.g., Dim_on_T) by delaying, by the predetermined delay of time, the detected falling edge of the logic signal 411 (e.g., Dim_on).
In certain embodiments, the control signal 521 is generated based at least in part on the delayed signal 523 and the logic signal 411 (e.g., Dim_on). In some examples, the control signal 521 is the same as the delayed signal 523, except that during the first half cycle of the AC input voltage 472 (e.g., VAC), the control signal 521 is the same as the logic signal 411 (e.g., Dim_on). For example, the first half cycle of the AC input voltage 472 (e.g., VAC) is either a positive half cycle or a negative half cycle of the AC input voltage 472 (e.g., VAC). As an example, the first half cycle of the AC input voltage 472 (e.g., VAC) occurs immediately after the system 400 is powered on.
At the process 1240, the output current 491 that flows through the one or more LEDs 490 is controlled based at least in part on the logic signal 432 (e.g., Dim_on′) according to some embodiments. For example, if the output current 491 that flows through the one or more LEDs 490 is not allowed to be generated, the output current 491 is equal to zero in magnitude.
At the process 1310, the sensing signal 461 (e.g., LS) that represents the rectified voltage 483 (e.g., VIN) is generated according to some embodiments. At the process 1320, whether the TRIAC dimmer 470 is a leading-edge TRIAC dimmer or a trailing-edge TRIAC dimmer is determined based at least in part on the sensing signal 461 (e.g., LS) in order to generate the mode signal 421 according to certain embodiments. In some examples, if the TRIAC dimmer 470 is determined to be a leading-edge TRIAC dimmer, the processes 1330, 1332, and 1350 are performed. In certain examples, if the TRIAC dimmer 470 is determined to be a trailing-edge TRIAC dimmer, the processes 1340, 1342, and 1350 are performed.
At the process 1330, the delayed signal 523 (e.g., Dim_on_T) is generated by delaying, by a predetermined delay of time (e.g., Td), the rising edge of the logic signal 411 (e.g., Dim_on) according to some embodiments. For example, the predetermined delay of time (e.g., Td) is equal to a half cycle of the AC input voltage 472 (e.g., VAC) in time duration. At the process 1332, the output current 491 is not allowed to be generated from at least the falling edge of the logic signal 411 (e.g., Dim_on) until the delayed rising edge of the logic signal 411 (e.g., Dim_on) according to certain embodiments. As an example, if the output current 491 that flows through the one or more LEDs 490 is not allowed to be generated, the output current 491 is equal to zero in magnitude.
At the process 1340, the delayed signal 523 (e.g., Dim_on_T) is generated by delaying, by a predetermined delay of time (e.g., Td), the falling edge of the logic signal 411 (e.g., Dim_on) according to some embodiments. For example, the predetermined delay of time (e.g., Td) is equal to a half cycle of the AC input voltage 472 (e.g., VAC) in time duration. At the process 1342, the output current 491 is not allowed to be generated from the delayed falling edge of the logic signal 411 (e.g., Dim_on) until at least the rising edge of the logic signal 411 (e.g., Dim_on) according to certain embodiments. As an example, if the output current 491 that flows through the one or more LEDs 490 is not allowed to be generated, the output current 491 is equal to zero in magnitude.
At the process 1350, the LED lighting system 400 operates without flickering of the one or more LEDs 490. For example, the size of the waveform during the negative half cycle of the AC input voltage 472 (e.g., VAC) and the size of the waveform during the positive half cycle of the AC input voltage 472 (e.g., VAC) are different. As an example, the average of the output current 491 in the negative half cycle of the AC input voltage 472 (e.g., VAC) and the average of the output current 491 in the positive half cycle of the AC input voltage 472 (e.g., VAC) are equal, preventing flickering of the one or more LEDs 490.
Certain embodiments of the present invention prevent flickering of the one or more LEDs even if the waveform during the positive half cycle of the AC input voltage and the waveform during the negative half cycle of the AC input voltage are significantly different. Some embodiments of the present invention improve effect of the dimming control and also improve compatibility of the TRIAC dimmer, without increasing bill of materials (BOM) for the components that are external to the chip.
According to some embodiments, a system for controlling one or more light emitting diodes includes: a phase detector configured to process information associated with a rectified voltage generated by a rectifier and related to a TRIAC dimmer, the rectified voltage corresponding to a first waveform during a first half cycle of an AC voltage and corresponding to a second waveform during a second half cycle of the AC voltage, the phase detector being further configured to generate a phase detection signal representing a first time duration during which the first waveform indicates that the rectified voltage is larger than a predetermined threshold and representing a second time duration during which the second waveform indicates that the rectified voltage is larger than the predetermined threshold; a mode detector configured to process information associated with the rectified voltage, determine whether the TRIAC dimmer is a leading-edge TRIAC dimmer or a trailing-edge TRIAC dimmer based on at least information associated with the rectified voltage, and generate a mode detection signal that indicates whether the TRIAC dimmer is the leading-edge TRIAC dimmer or the trailing-edge TRIAC dimmer; a modified signal generator configured to receive the phase detection signal from the phase detector and the mode detection signal from the mode detector, modify the phase detection signal based at least in part on the mode detection signal, and generate a modified signal representing a third time duration corresponding to the first half cycle of the AC voltage and a fourth time duration corresponding to the second half cycle of the AC voltage; and a current controller configured to receive the modified signal, the current controller being further configured to control, based at least in part of the modified signal, a first current flowing through one or more light emitting diodes configured to receive the rectified voltage; wherein: the first time duration and the second time duration are different in magnitude; and the third time duration and the fourth time duration are the same in magnitude. For example, the system for controlling one or more light emitting diodes is implemented according to at least
In certain examples, a first average of the first current corresponding to the first half cycle of the AC voltage and a second average of the first current corresponding to the second half cycle of the AC voltage are equal in magnitude. In some examples, the first time duration is smaller than the second time duration in magnitude; the third time duration is equal to the first time duration in magnitude; and the fourth time duration is smaller than the second duration in magnitude. In certain examples, the first time duration is larger than the second time duration in magnitude; the third time duration is smaller than the first time duration in magnitude; and the fourth time duration is equal to the second duration in magnitude.
In some examples, the modified signal generator includes a control signal generator configured to: process information associated with the phase detection signal; delay, by a predetermined delay of time, one or more rising edges of the phase detection signal or one or more falling edges of the phase detection signal based at least in part on the mode detection signal; and generate a control signal based at least in part on the one or more delayed rising edges or the one or more delayed falling edges. In certain examples, the control signal generator is further configured to: delay, by the predetermined delay of time, the one or more rising edges of the phase detection signal if the mode detection signal indicates that the TRIAC dimmer is the leading-edge TRIAC dimmer; and delay, by the predetermined delay of time, the one or more falling edges of the phase detection signal if the mode detection signal indicates that the TRIAC dimmer is the trailing-edge TRIAC dimmer. In some examples, the control signal generator is further configured to generate the control signal based at least in part on the one or more delayed rising edges or the one or more delayed falling edges and also based at least in part on the phase detection signal.
In certain examples, wherein the control signal generator includes a delayed signal generator configured to: receive the mode detection signal; delay, by the predetermined delay of time, the one or more rising edges of the phase detection signal or the one or more falling edges of the phase detection signal based at least in part on the mode detection signal; and generate a delayed signal based at least in part on the one or more delayed rising edges or the one or more delayed falling edges. In some examples, the control signal generator further includes a signal controller configured to receive the delayed signal and the phase detection signal and generate the control signal based at least in part on the delayed signal and the phase detection signal. In certain examples, the control signal generator is further configured to generate the control signal that is the same as the delayed signal, except that during the first half cycle of the AC input voltage, the control signal is the same as the phase detection signal.
In some examples, the modified signal generator further includes an output signal generator configured to receive the control signal and the phase detection signal and generate the modified signal based at least in part on the control signal and the phase detection signal. In certain examples, the output signal generator includes an AND gate, the AND gate being configured to receive the control signal and the phase detection signal and generate the modified signal based at least in part on the control signal and the phase detection signal. In some examples, the predetermined delay of time is equal to the first half cycle of the AC voltage in duration; and the predetermined delay of time is equal to the second half cycle of the AC voltage in duration.
In certain examples, the current controller includes: a control signal generator configured to receive the modified signal and generate a drive signal based at least in part on the modified signal; a switch configured to receive the modified signal and become closed or open based at least in part on the modified signal; and a transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, the first transistor terminal being coupled to the control signal generator and the switch, the second transistor terminal being coupled to the one or more light emitting diodes. In some examples, the switch is further configured to be: open if the modified signal is at a first logic level; and closed if the modified signal is at a second logic level; wherein the first logic level and the second logic level are different. In certain examples, the modified signal is at the first logic level during the third time duration within the first half cycle of the AC voltage; and the modified signal is at the second logic level outside the third time duration within the first half cycle of the AC voltage. In some examples, the modified signal is at the first logic level during the fourth time duration within the second half cycle of the AC voltage; and the modified signal is at the second logic level outside the fourth time duration within the second half cycle of the AC voltage. In certain examples, the first logic level is a logic high level; and the second logic level is a logic low level. In some examples, if the switch is closed, the first current flowing through the one or more light emitting diodes is equal to zero in magnitude; and if the switch is open, the first current flowing through the one or more light emitting diodes is equal to a predetermined value in magnitude based at least in part on the drive signal; wherein the predetermined value is larger than zero.
In certain examples, the current controller further includes a resistor including a first resistor terminal and a second resistor terminal; and the switch including a first switch terminal and a second switch terminal; wherein: the first resistor terminal is connected to the third transistor terminal; the second resistor terminal is biased to a ground voltage; the first switch terminal is connected to the first transistor terminal; and the second switch terminal is biased to the ground voltage.
In some examples, the current controller includes: a control signal generator configured to receive the modified signal and generate a drive signal based at least in part on the modified signal; an operation signal generator configured to receive the modified signal and generate an operation signal based at least in part on the modified signal; a switch configured to receive the operation signal and become closed or open based at least in part on the operation signal; and a transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, the first transistor terminal being coupled to the control signal generator and the switch, the second transistor terminal being coupled to the one or more light emitting diodes. In certain examples, the switch is further configured to be: open if the operation signal is at a first logic level; and closed if the operation signal is at a second logic level; wherein the first logic level and the second logic level are different. In some examples, the operation signal generator is further configured to: change the operation signal from the second logic level to the first logic level at a same time as the modified signal; and change the operation signal from the first logic level to the second logic level at a different time from the modified signal. In certain examples, the operation signal generator is further configured to: change the operation signal from the second logic level to the first logic level at a same time as the modified signal; and change the operation signal from the first logic level to the second logic level at a same time from the modified signal.
In some examples, the system for controlling one or more light emitting diodes further includes: a bleeder current controller and generator configured to receive the mode detection signal and generate a bleeder current based at least in part on the mode selection signal to ensure that a second current flowing through the TRIAC dimmer does not fall below a holding current of the TRIAC dimmer. In certain examples, the system for controlling one or more light emitting diodes further includes: a voltage detector configured to receive the rectified voltage and generate a sensing signal based at least in part on the rectified voltage; wherein the phase detector is further configured to: receive the sensing signal; and generate the phase detection signal based at least in part on the sensing signal; wherein the mode detector is further configured to: receive the sensing signal; and generate the mode detection signal based at last in part on the sensing signal. In some examples, the voltage detector includes a voltage divider including a first resistor and a second resistor.
According to certain embodiments, a system for controlling one or more light emitting diodes includes: a phase detector configured to process information associated with a rectified voltage generated by a rectifier and related to a TRIAC dimmer, the rectified voltage corresponding to a first waveform during a first half cycle of an AC voltage and corresponding to a second waveform during a second half cycle of the AC voltage, the signal detector being further configured to generate a phase detection signal representing a first time duration during which the first waveform indicates that the rectified voltage is larger than a predetermined threshold and representing a second time duration during which the second waveform indicates that the rectified voltage is larger than the predetermined threshold; a mode detector configured to process information associated with the rectified voltage, determine whether the TRIAC dimmer is a leading-edge TRIAC dimmer or a trailing-edge TRIAC dimmer based on at least information associated with the rectified voltage, and generate a mode detection signal that indicates whether the TRIAC dimmer is the leading-edge TRIAC dimmer or the trailing-edge TRIAC dimmer; and a modified signal generator configured to receive the phase detection signal from the phase detector and the mode detection signal from the mode detector, the modified signal generator being further configured to generate, based at least in part on the phase detection signal and the mode detection signal, a modified signal representing a third time duration corresponding to the first half cycle of the AC voltage and a fourth time duration corresponding to the second half cycle of the AC voltage; wherein: the first time duration is smaller than the second time duration in magnitude; the third time duration is equal to the first time duration in magnitude; the fourth time duration is smaller than the second duration in magnitude; and the third time duration and the fourth time duration are equal in magnitude. For example, the system for controlling one or more light emitting diodes is implemented according to at least
According to some embodiments, a method for controlling one or more light emitting diodes includes: processing information associated with a rectified voltage related to a TRIAC dimmer, the rectified voltage corresponding to a first waveform during a first half cycle of an AC voltage and corresponding to a second waveform during a second half cycle of the AC voltage; generating a phase detection signal representing a first time duration during which the first waveform indicates that the rectified voltage is larger than a predetermined threshold and representing a second time duration during which the second waveform indicates that the rectified voltage is larger than the predetermined threshold; determining whether the TRIAC dimmer is a leading-edge TRIAC dimmer or a trailing-edge TRIAC dimmer based on at least information associated with the rectified voltage; generating a mode detection signal that indicates whether the TRIAC dimmer is the leading-edge TRIAC dimmer or the trailing-edge TRIAC dimmer; receiving the phase detection signal and the mode detection signal; modifying the phase detection signal based at least in part on the mode detection signal; generating a modified signal representing a third time duration corresponding to the first half cycle of the AC voltage and a fourth time duration corresponding to the second half cycle of the AC voltage; receiving the modified signal; and controlling, based at least in part of the modified signal, a first current flowing through one or more light emitting diodes configured to receive the rectified voltage; wherein: the first time duration and the second time duration are different in magnitude; and the third time duration and the fourth time duration are the same in magnitude. For example, the method for controlling one or more light emitting diodes is implemented according to at least
According to certain embodiments, a method for controlling one or more light emitting diodes includes: processing information associated with a rectified voltage related to a TRIAC dimmer, the rectified voltage corresponding to a first waveform during a first half cycle of an AC voltage and corresponding to a second waveform during a second half cycle of the AC voltage; generating a phase detection signal representing a first time duration during which the first waveform indicates that the rectified voltage is larger than a predetermined threshold and representing a second time duration during which the second waveform indicates that the rectified voltage is larger than the predetermined threshold; determining whether the TRIAC dimmer is a leading-edge TRIAC dimmer or a trailing-edge TRIAC dimmer based on at least information associated with the rectified voltage; generating a mode detection signal that indicates whether the TRIAC dimmer is the leading-edge TRIAC dimmer or the trailing-edge TRIAC dimmer; receiving the phase detection signal and the mode detection signal; and generating, based at least in part on the phase detection signal and the mode detection signal, a modified signal representing a third time duration corresponding to the first half cycle of the AC voltage and a fourth time duration corresponding to the second half cycle of the AC voltage; wherein: the first time duration is smaller than the second time duration in magnitude; the third time duration is equal to the first time duration in magnitude; the fourth time duration is smaller than the second duration in magnitude; and the third time duration and the fourth time duration are equal in magnitude. For example, the method for controlling one or more light emitting diodes is implemented according to at least
For example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. As an example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. For example, various embodiments and/or examples of the present invention can be combined.
Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201911371960.8 | Dec 2019 | CN | national |
This application is a continuation of U.S. patent application Ser. No. 17/127,711, filed Dec. 18, 2020, which claims priority to Chinese Patent Application No. 201911371960.8, filed Dec. 27, 2019, both applications being incorporated by reference herein for all purposes.
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| Number | Date | Country | |
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| Child | 17554306 | US |
