Aspects of some embodiments according to the present disclosure relate to systems and methods for data management in storage devices using a data placement manager.
In the field of computer storage, a system may include a host and one or more storage devices connected to (e.g., communicably coupled to) the host. Such computer storage systems have become increasingly popular, in part, for allowing many different users to share the computing resources of the system. Storage requirements have increased over time as the number of users of such systems and the number and complexity of applications running on such systems have increased.
The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure, and therefore, it may contain information that does not constitute prior art.
One or more embodiments of the present disclosure are directed to computer storage systems, and may provide improvements to data placement in storage devices.
According to some embodiments of the present disclosure, there is provided a method for data storage, the method including receiving a first request at a storage device, the first request being associated with a first protocol that is a memory protocol, converting address information associated with the first request to logical block address (LBA) information, determining, by the storage device, a first group of contiguous physical block addresses associated with the first request and associated with a first application, based on a data placement configuration of the storage device, and performing a first memory operation at the first group, based on the first request.
The determining may include checking a field of the first request, checking a bit of the first request, or checking a configuration of the storage device.
The first group may be associated with a first area, and the storage device may include a second group associated with a second area of contiguous physical block addresses that are separated from the first group and associated with a second application.
The method may further include receiving a configuration request at the storage device, and dividing physical block addresses of the storage device into one or more groups of contiguous physical block addresses, the one or more groups including the first group.
The method may further include performing the first memory operation based on the LBA information, and receiving a second request associated with a second protocol that is different from the first protocol at the storage device, the second request including information identifying a second group of contiguous physical block addresses associated with the second request and associated with a second application.
The first protocol may be a cache-coherent protocol, and the second protocol may be a storage protocol.
The storage device may be configured to track grouping parameters associated with the data placement configuration, receive requests in accordance with the first protocol and in accordance with a second protocol that is different from the first protocol, and receive configuration requests for dividing the storage device in accordance with the data placement configuration.
According to some other embodiments of the present disclosure, there is provided a storage device including a non-volatile memory and being configured to receive a first request associated with a first protocol that is a memory protocol, convert address information associated with the first request to logical block address (LBA) information, determine a first group of contiguous physical block addresses associated with the first request and associated with a first application, based on a data placement configuration, and perform a first memory operation at the first group, based on the first request.
The determining may include checking a field of the first request, checking a bit of the first request, or checking a configuration of the storage device.
The first group may be associated with a first area, and the storage device may include a second group associated with a second area of contiguous physical block addresses that are separated from the first group and associated with a second application.
The storage device may be configured to receive a configuration request at the storage device, and divide physical block addresses of the storage device into one or more groups of contiguous physical block addresses, the one or more groups including the first group.
The storage device may be configured to perform the first memory operation based on the LBA information, and receive a second request associated with a second protocol that is different from the first protocol at the storage device, the second request including information identifying a second group of contiguous physical block addresses associated with the second request and associated with a second application.
The first protocol may be a cache-coherent protocol, and the second protocol may be a storage protocol.
The storage device may be configured to track grouping parameters associated with the data placement configuration, receive requests in accordance with the first protocol and in accordance with a second protocol that is different from the first protocol, and receive configuration requests for dividing the storage device in accordance with the data placement configuration.
According to some other embodiments of the present disclosure, there is provided a system for data storage, the system including a processor, and memory storing instructions, which, based on being executed by the processor, cause the processor to perform receiving a first request, the first request being associated with a first protocol that is a memory protocol, converting address information associated with the first request to logical block address (LBA) information, determining a first group of contiguous physical block addresses associated with the first request and associated with a first application, based on a data placement configuration of a storage device, and performing a first memory operation at the first group, based on the first request.
The determining may include checking a field of the first request, checking a bit of the first request, or checking a configuration of the storage device.
The first group may be associated with a first area, and the storage device may include a second group associated with a second area of contiguous physical block addresses that are separated from the first group and associated with a second application.
The instructions, based on being executed by the processor, may cause the processor to perform receiving a configuration request at the storage device, and dividing physical block addresses of the storage device into one or more groups of contiguous physical block addresses, the one or more groups including the first group.
The instructions, based on being executed by the processor, may cause the processor to perform the first memory operation based on the LBA information, and receiving a second request associated with a second protocol that is different from the first protocol at the storage device, the second request including information identifying a second group of contiguous physical block addresses associated with the second request and associated with a second application.
The first protocol may be a cache-coherent protocol, and the second protocol may be a storage protocol.
The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of the illustrative, non-limiting embodiments with reference to the accompanying drawings.
Aspects of the present disclosure and methods of accomplishing the same may be understood more readily by reference to the detailed description of one or more embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. The described embodiments, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of the present disclosure to those skilled in the art. Accordingly, description of processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of the present disclosure may be omitted.
Unless otherwise noted, like reference numerals, characters, or combinations thereof denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof will not be repeated. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity, and have not necessarily been drawn to scale. For example, the dimensions of some of the elements, layers, and regions in the figures may be exaggerated relative to other elements, layers, and regions to help to improve clarity and understanding of various embodiments. Also, common but well-understood elements and parts not related to the description of the embodiments might not be shown to facilitate a less obstructed view of these various embodiments and to make the description clear.
In the detailed description, for the purposes of explanation, numerous specific details are set forth to provide a thorough understanding of various embodiments. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements.
It will be understood that, although the terms “zeroth,” “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present disclosure.
It will be understood that when an element or component is referred to as being “on,” “connected to,” or “coupled to” another element or component, it can be directly on, connected to, or coupled to the other element or component, or one or more intervening elements or components may be present. However, “directly connected/directly coupled” refers to one component directly connecting or coupling another component without an intermediate component. Meanwhile, other expressions describing relationships between components such as “between,” “immediately between” or “adjacent to” and “directly adjacent to” may be construed similarly. In addition, it will also be understood that when an element or component is referred to as being “between” two elements or components, it can be the only element or component between the two elements or components, or one or more intervening elements or components may also be present.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “have,” “having,” “includes,” and “including,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, each of the terms “or” and “and/or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and/or B” denotes A, B, or A and B.
For the purposes of this disclosure, expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of X, Y, or Z,” “at least one of X, Y, and Z,” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ.
As used herein, the term “substantially,” “about,” “approximately,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. “About” or “approximately,” as used herein, is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within +30%, 20%, 10%, 5% of the stated value. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.”
When one or more embodiments may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order.
Any of the components or any combination of the components described (e.g., in any system diagrams included herein) may be used to perform one or more of the operations of any flow chart included herein. Further, (i) the operations are merely examples, and may involve various additional operations not explicitly covered, and (ii) the temporal order of the operations may be varied.
The electronic or electric devices and/or any other relevant devices or components according to embodiments of the present disclosure described herein may be implemented utilizing any suitable hardware, firmware (e.g. an application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one integrated circuit (IC) chip or on separate IC chips. Further, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate.
Further, the various components of these devices may be a process or thread, running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in a memory, which may be implemented in a computing device using a standard memory device, such as, for example, a random-access memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, flash drive, or the like. Also, a person of skill in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of the embodiments of the present disclosure.
Any of the functionalities described herein, including any of the functionalities that may be implemented with a host, a device, and/or the like or a combination thereof, may be implemented with hardware, software, firmware, or any combination thereof including, for example, hardware and/or software combinational logic, sequential logic, timers, counters, registers, state machines, volatile memories such as dynamic RAM (DRAM) and/or static RAM (SRAM), nonvolatile memory including flash memory, persistent memory such as cross-gridded nonvolatile memory, memory with bulk resistance change, phase change memory (PCM), and/or the like and/or any combination thereof, complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), application-specific ICs (ASICs), central processing units (CPUs) including complex instruction set computer (CISC) processors and/or reduced instruction set computer (RISC) processors, graphics processing units (GPUs), neural processing units (NPUs), tensor processing units (TPUs), data processing units (DPUs), and/or the like, executing instructions stored in any type of memory. In some embodiments, one or more components may be implemented as a system-on-a-chip (SoC).
Any host disclosed herein that may implement any of the functionalities described herein relating to intermediary formats and/or languages may be implemented with any component or combination of components including one or more of a client device, a server, a storage node, a CPU, a personal computer, a tablet computer, a smartphone, and/or the like.
Any of the computational devices disclosed herein may be implemented in any form factor, such as 3.5 inch, 2.5 inch, 1.8 inch, M.2, Enterprise and Data Center Standard Form Factor (EDSFF), NF1, and/or the like, using any connector configuration such as Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), U.2, and/or the like. Any of the computational devices disclosed herein may be implemented entirely or partially with, and/or used in connection with, a server chassis, server rack, data room, data center, edge data center, mobile edge data center, and/or any combinations thereof.
Any of the devices disclosed herein that may be implemented as storage devices may be implemented with any type of nonvolatile storage media based on solid-state media, magnetic media, optical media, and/or the like. For example, in some embodiments, a storage device (e.g., a computational storage device) may be implemented as an SSD based on not-AND (NAND) flash memory, persistent memory such as cross-gridded nonvolatile memory, memory with bulk resistance change, PCM, and/or the like, or any combination thereof.
Any of the communication connections and/or communication interfaces disclosed herein may be implemented with one or more interconnects, one or more networks, a network of networks (e.g., the Internet), and/or the like, or a combination thereof, using any type of interface and/or protocol. Examples include Peripheral Component Interconnect Express (PCIe), non-volatile memory express (NVMe), NVMe-over-fabric (NVMe-oF), Ethernet, Transmission Control Protocol/Internet Protocol (TCP/IP), Direct Memory Access (DMA) Remote DMA (RDMA), RDMA over Converged Ethernet (ROCE), FibreChannel, InfiniBand, SATA, SCSI, SAS, Internet Wide Area RDMA Protocol (iWARP), and/or a coherent protocol, such as Compute Express Link (CXL), CXL.mem, CXL.cache, CXL.IO and/or the like, Gen-Z, Open Coherent Accelerator Processor Interface (OpenCAPI), Cache Coherent Interconnect for Accelerators (CCIX), and/or the like, Advanced extensible Interface (AXI), any generation of wireless network including 2G, 3G, 4G, 5G, 6G, and/or the like, any generation of Wi-Fi, Bluetooth, near-field communication (NFC), and/or the like, or any combination thereof.
In some embodiments, a software stack may include a communication layer that may implement one or more communication interfaces, protocols, and/or the like such as PCIe, NVMe, CXL, Ethernet, NVMe-oF, TCP/IP, and/or the like, to enable a host and/or an application running on the host to communicate with a computational device or a storage device.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.
As mentioned above, in the field of computer storage, a system may include a host and one or more storage devices communicably coupled to the host. The storage devices may be configured to store data for applications running on the host. One or more of the storage devices may store the data in a storage and/or in a memory. For example, the storage may be associated with a non-volatile memory (e.g., a persistent memory) used to store one or more files. The files in the non-volatile memory may be available for use after a computer that stores the data is powered down and powered on again. In some embodiments of the present disclosure, the storage may be associated with a non-volatile memory (NVM) protocol (e.g., NVM express (NVMe)). Typically, the memory may be associated with a volatile memory used to store data temporarily for quicker access and quicker processing by the computer. The data in the memory may be unavailable after the computer is powered down. In some embodiments, the memory may be associated with a memory protocol (e.g., Compute Express Link (CXL)). In such embodiments, a CPU of a host may access persistent memory on one or more storage devices using the memory protocol, such that the NVM of the one or more storage devices may be used as memory.
Data centers with hyperscale workloads may experience write-amplification problems due to mixed data placement inside storage devices. Media reads and writes in a storage device having mixed data placement may affect the performance and quality of services (QOS) provided by the storage device. Flash media writes may cause non-host induced media wear. Flexible data placement (FDP) management methods include placing data from different applications together in isolated physical locations inside a storage device. “Flexible data placement,” as used herein, refers to a type of data-placement scheme or configuration (e.g., a physical data-arrangement scheme), where data from different applications are stored in physical locations that are isolated from each other within a non-volatile memory of a storage device, such that data from one application can be erased from physical storage blocks associated with only the one application (i.e., without erasing data from physical storage blocks associated with other applications). FDP management methods can reduce write amplification because data associated with one application can be erased without erasing data associated with other applications.
Some storage systems may include applications that are configured to send requests (also referred to as “commands”) to a storage device for different purposes (e.g., storage or memory) according to different protocols. Some protocols (e.g., storage protocols) may be compatible with FDP, and some protocols (e.g., memory protocols) may not be compatible (e.g., may not be conventionally compatible) with FDP. Various embodiments of the present disclosure provide architectures that may be used in the field of memory and/or computer storage to allow FDP to be used with a variety of memory protocols.
In some embodiments, the storage devices may include solid-state storage devices (SSDs), having non-volatile memory corresponding to one or more dies. Each die may include one or more blocks. Each block may include one or more pages. Each page may correspond to a logical block address (LBA) and a physical block address (PBA). Each LBA may identify a logical location of data associated with a namespace in the non-volatile memory. Each PBA may identify a physical location of the data associated with the namespace in the non-volatile memory. The namespace may be associated with a particular application. LBAs and PBAs may be used by the storage devices to locate and perform operations on the data in the non-volatile memory logically and physically. Two LBAs that are logically adjacent to each other may not be physically adjacent to each other. For example, contiguous PBAs may have mixed data associated with more than one application.
In some systems, data associated with a particular namespace (or application) may be grouped only by LBA, not by PBA. For example, two LBAs that are logically adjacent to each other may not be physically adjacent to each other. For example, contiguous PBAs may have mixed data associated with more than one application. In such systems a first application may have data stored in a first PBA, and a second application may have data stored in a second PBA that is contiguous with the first PBA within a same block of the non-volatile memory. The non-volatile memory in such systems may include one or more blocks with LBAs associated with different applications. In such systems, erasing data associated with one application may involve the storage device erasing each LBA associated with the one application along with the data associated with other applications within the same block. The performance of such systems may be degraded due to write amplification. Write amplification may wear down the non-volatile storage media (e.g., flash media) and waste power consumed in performing additional reads and writes associated with erasing data (e.g., associated with garbage collection).
In some embodiments of the present disclosure, a storage device may be configured for FDP, wherein data associated with a first application may be stored in PBAs that are not mixed in the same block as the data of other applications. In such embodiments, write amplification may be reduced, when compared to systems with mixed blocks (e.g., with mixed data placement inside the storage device as discussed above), by aligning logical block usage with physical storage media.
In some embodiments, the system may include applications that are configured to send requests (also referred to as “commands”) to a storage device for different purposes (e.g., storage or memory) according to different protocols. Some protocols (e.g., storage protocols) may be compatible with FDP, and some protocols (e.g., memory protocols) may not be compatible (e.g., may not be conventionally compatible) with FDP. For example, some protocols (e.g., memory protocols) may involve additional processing steps, compared to other protocols (e.g., storage protocols), to become compatible with FDP. For example, NVMe is a protocol (e.g., a storage protocol) that is compatible with FDP. NVMe is a storage protocol that can use commands that include LBA information and FDP information for implementing and FDP scheme (e.g., an FDP configuration) in a storage device. On the other hand, memory protocols (e.g., CXL memory protocols), which may be cache-coherent protocols, may not be conventionally compatible with FDP. For example, CXL memory protocols do not conventionally use commands that include LBA information and FDP information. As such, in some embodiments, CXL memory address information that is used for cache coherency purposes between the CXL storage devices and one or more CPUs may first be converted to LBA information for a given CXL storage device. Accordingly, various embodiments of the present disclosure may provide architectures that may be used in the field of memory and/or computer storage to allow FDP to be used with a variety of memory protocols.
Currently, FDP is an optional capability of a non-volatile memory (NVM) command set for NVME storage protocols. NVM controllers may support log pages, which indicate the status of FDP, statistics about the FDP operation, and information that a host may use to detect and correct usage patterns that increase write amplification. In FDP, physical media may be grouped based on domains, endurance groups (EGs), and reclaim groups (RGs) to manage and monitor the wear experienced by different areas of physical storage media. A domain may include one or more EGs, each EG may include one or more RGs. As discussed below with reference to
Some storage devices may be capable of working with a variety of protocols. For example, a dual-mode storage device (e.g., a CXL dual-mode SSD) may be designed to work with CXL and NVMe. However, in dual-mode CXL SSD devices, a memory write command (e.g., CXL.mem) may not be capable of maintaining the FDP characteristics of the CXL SSD. Aspects of some embodiments of the present disclosure, provide a storage device architecture to support FDP in dual-mode storage devices.
Referring to
A second interface 20 (e.g., a second channel) associated with the storage device interface IF may be capable of providing communications to and from the applications 111 in accordance with a second protocol (e.g., a storage protocol). The second protocol may be a storage protocol that uses commands including LBA information and FDP information for the storage device 200. For example, the second protocol may be an NVMe protocol. The applications 111 may send NVMe input/output (I/O) commands via the second interface 20.
A third interface 30 (e.g., a third channel) associated with the storage device interface IF may be capable of receiving communications from the host 100 to process FDP configuration requests. In some embodiments, the storage device 200 may be dynamically configured using an NVMe mode and/or a CXL memory load/store (LD/ST) mode. For example, in some embodiments, the storage device 200 may provide an NVMe mode that is capable of performing reads and writes with block I/O granularities of 512B (bytes) and/or 4 KB (kilobytes). In some embodiments, the storage device 200 may provide a CXL memory mode that is capable of performing memory reads and memory writes (e.g., memory load operations or memory store operations) to data with CXL.mem requests using load/store instructions for a byte-addressable 64B cacheline.
In some embodiments, the first interface 10, the second interface 20, and the third interface 30 may be associated with a host interface layer HIL of the storage device 200. The host interface layer HIL may include a variety of components for processing requests from different protocols.
For example, the first interface 10 may be coupled to a conversion component 210 of the host interface layer HIL. The conversion component 210 may handle memory requests that comply with a memory protocol (e.g., a cache-coherent memory protocol), such as CXL. The conversion component 210 may convert address information (e.g., cache-coherent address information) that is associated with maintaining cache coherency across a network of storage devices to local address information (e.g., LBA information) for the storage device 200. For example, the conversion component 210 may convert CXL information associated with the network of storage devices to LBA information for accessing a non-volatile memory 250 of the storage device 200. The storage device 200 may be one storage device of more than one storage devices coupled together (e.g., a storage device pool) by way of the storage device interface IF.
The second interface 20 may be coupled to a command manager 220 of the host interface layer HIL. The command manager 220 may handle data access requests associated with a storage protocol that is capable of providing FDP and LBA information. For example, the command manager 220 may be an NVMe command manager that handles NVMe I/O requests.
The third interface 30 may be coupled to an FDP configuration component 230 of the host interface layer HIL. The FDP configuration component 230 may handle configuration requests from the host 100 to configure the storage device 200 for a desired FDP scheme. In some embodiments, the FDP configuration component 230 may handle configuration requests associated with a memory protocol (e.g., CXL.io configuration requests). In some embodiments, the FDP configuration component 230 may handle configuration requests associated with a protocol that uses commands including LBA information for the storage device 200. For example, the FDP configuration component 230 may handle NVMe administration commands. In some embodiments, the third interface 30 may handle configuration requests associated with both a memory protocol and a protocol that uses commands including LBA information for the storage device 200.
A data placement manager DPM (also referred to as an “FDP manager”) of the host interface layer HIL may process the respective outputs from the conversion component 210, the command manager 220, and the FDP configuration component 230. The data placement manager DPM may track global data placement information associated with the non-volatile memory 250 of the storage device 200. The data placement manager DPM may process configuration requests and data access requests and maintain the FDP characteristics of the non-volatile memory 250 based on the desired FDP parameters. The FDP parameters may include parameters for grouping areas of the non-volatile memory in accordance with a given or desired FDP scheme. For example, the FDP parameters may include reclaim groups RG (e.g., a zeroth reclaim group RG0 through an n-th reclaim group RGn, which are depicted in
For example, the non-volatile memory 250 may include one or more channels CH (for example, a zeroth channel CH0 through an n-th channel CHn). Each channel CH may correspond to one or more dies. Each channel CH may include one or more blocks B. For example, as depicted in
As depicted in
As discussed above, the data placement manager DPM may track global information and maintain the FDP characteristics of the non-volatile memory 250 based on the desired FDP parameters. The data placement manager DPM may be coupled to a flash translation layer FTL and a non-volatile memory interface layer NIL to manage data access at the non-volatile memory 250.
In some embodiments, FDP may be supported in a memory path (e.g., a cache-coherent memory path), such as a CXL.mem path, of a dual-mode storage device (e.g., a dual-mode CXL SSD) by allowing the host 100 to configure the storage device 200 with FDP parameters during an FDP namespace generation operation. The FDP parameters may include reclaim groups RG, reclaim units RU, reclaim unit handles RUH, FDP attributes, and placement identifiers (PIDL) (e.g., default or desired placement identifiers) (reclaim groups RG, reclaim units RU, and reclaim unit handles RUH are depicted in
According to one or more embodiments, the memory path (e.g., the CXL.mem path) may support FDP in three ways: per address (e.g., per CXL.mem address), based on address range, and based on a default PIDL. Using the per address method, a memory command (e.g., a CXL LD/ST command) may include a field with bits indicating FDP information. For example, a first type of memory command 500A (e.g., a memwr command or a memwrptl command) (see
Using the address range method, PIDLs for FDP configuration may be predefined based on address ranges. For example, the host 100 may configure an FDP configuration space using a memory protocol manager (e.g., a FM over a CXL I/O path) and may predefine PIDLs for different address spaces during an FDP namespace generation operation.
Using the default PIDL method, memory requests (e.g., CXL requests) may be handled by the storage device 200 using a default PIDL configured during an FDP namespace generation operation.
FDP may be supported in accordance with a protocol that uses commands comprising LBA information for the storage device 200 (e.g., an NVMe protocol) by way of a directive method and/or by way of a non-directive method. Using the directive method, data may be placed in reclaim groups RG and reclaim units RU according to a PIDL. The PIDL may be provided in a directive field of a write command (e.g., an NVMe I/O command). Using the non-directive method, data may be placed in reclaim groups RG and reclaim units RU according to a default PIDL. For example, the default PIDL may be configured during an FDP namespace generation operation via an administration command (e.g., an NVMe administration command).
Accordingly, a dual-mode storage device may be provided, wherein FDP may be fully implemented with the memory path (e.g., the CXL.mem path) and an NVMe data path managed by a conventional controller (e.g., a conventional NVMe controller). Implementing FDP with the memory path (e.g., the CXL.mem path) may reduce a latency of the memory path. Furthermore, write amplification and overprovisioning may be reduced.
Referring to
Referring to
Referring to
Referring to
In addition to the RSVD bit field F13, the first type of memory command 500A may include a valid field F1, a memo pcode field F2, an snptype field F3, a metafield F4, a metavalue field F5, a tag field F6, an address field F7, a pois on field F8, a BEP field F9, an LD-ID field F10, an SPID field F11, a DPID field F12, and a TC field F14. Each field may have a bit width W, as indicated in
Referring to
Referring to
Accordingly, aspects of some embodiments of the present disclosure may provide improvements to computer storage by providing FDP for a variety of protocols to reduce write amplification and latencies associated with computer storage systems.
Example embodiments of the disclosure may extend to the following statements, without limitation:
Statement 1. An example method includes: receiving a first request at a storage device, the first request being associated with a first protocol that is a memory protocol, converting address information associated with the first request to logical block address (LBA) information, determining, by the storage device, a first group of contiguous physical block addresses associated with the first request and associated with a first application, based on a data placement configuration of the storage device, and performing a first memory operation at the first group, based on the first request.
Statement 2. An example method includes the method of statement 1, wherein the determining includes checking a field of the first request, checking a bit of the first request, or checking a configuration of the storage device.
Statement 3. An example method includes the method of any of statements 1 and 2, wherein the first group is associated with a first area, and the storage device includes a second group associated with a second area of contiguous physical block addresses that are separated from the first group and associated with a second application.
Statement 4. An example method includes the method of any of statements 2 and 3, and further includes receiving a configuration request at the storage device, and dividing physical block addresses of the storage device into one or more groups of contiguous physical block addresses, the one or more groups including the first group.
Statement 5. An example method includes the method of any of statements 2-4, and further includes performing the first memory operation based on the LBA information, and receiving a second request associated with a second protocol that is different from the first protocol at the storage device, the second request including information identifying a second group of contiguous physical block addresses associated with the second request and associated with a second application.
Statement 6. An example method includes the method of any of statements 2-5, wherein the first protocol is a cache-coherent protocol, and the second protocol is a storage protocol.
Statement 7. An example method includes the method of any of statements 2-6, wherein the storage device is configured to track grouping parameters associated with the data placement configuration, receive requests in accordance with the first protocol and in accordance with a second protocol that is different from the first protocol, and receive configuration requests for dividing the storage device in accordance with the data placement configuration.
Statement 8. An example device for performing the method of any of statements 1-7 includes a non-volatile memory.
Statement 9. An example system includes a processor, and memory storing instructions, which, based on being executed by the processor, cause the processor to perform the method of any of statements 1-7.
While embodiments of the present disclosure have been particularly shown and described with reference to the embodiments described herein, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as set forth in the following claims and their equivalents.
This application claims priority to, and benefit of, U.S. Provisional Application Ser. No. 63/471,413, filed on Jun. 6, 2023, entitled “MECHANISM TO SUPPORT FLEXIBLE DATA PLACEMENT FUNCTIONALITY IN CXL SSD,” the entire content of which is incorporated herein by reference.
Number | Date | Country | |
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63471413 | Jun 2023 | US |