Patent Application
20230126379
This application claims priority to Chinese Patent Application No. 202111255368.9, filed Oct. 27, 2021, incorporated by reference herein for all purposes.
Certain embodiments of the present invention are directed to circuits. More particularly, some embodiments of the invention provide systems and methods for detecting currents. Merely by way of example, some embodiments of the invention have been applied to power management systems. But it would be recognized that the invention has a much broader range of applicability.
For a conventional power management system, the input current and/or the output current often needs to be detected in order to regular the input current and/or the output current respectively. For example, the input current usually is determined by detecting the voltage across a resistor connected between an input terminal of the power management system and a terminal that is connected to a power source, and then the determined input current is used by a main feedback loop of the power management system to regulate the input current in order to keep the input current at a constant magnitude. As an example, the output current usually is determined by detecting the voltage across a resistor connected between an output terminal of the power management system and a terminal that is connected to a load device, and then the determined output current is used by a main feedback loop of the power management system to regulate the output current in order to keep the output current at a constant magnitude.
The conventional current detection system is configured to regulate a current 103 that flows out of the power management system 102 at a terminal 104. As part of the power management system 102, the power supply 140 provides a voltage 141 to the power converter 150. In response, the power converter 150 (e.g., a DC-DC converter) generates a voltage 151, which is used by the output inductor 160 and the output capacitor 170 to generate a voltage 105 at the terminal 104. Additionally, the power converter 150 (e.g., a DC-DC converter) also generates a control signal 153. One terminal of the output capacitor 170 is biased to a ground voltage 171.
The terminal 104 is connected to a terminal 112i of the resistor 110i and connected to an input terminal 122i (e.g., an “+” terminal) of the operational amplifier 120i, wherein i is an integer larger than or equal to 1 but smaller than or equal to N. The resistor 110i also includes a terminal 114i, and the operational amplifier 120i also includes an input terminal 124i (e.g., an “−” terminal) and an output terminal 126i. The terminal 114i of the resistor 110i and the input terminal 124i (e.g., an “−” terminal) of the operational amplifier 120i are connected. The terminal 114i of the resistor 110i is also connected to a drain terminal 184i of the transistor 180i, which also includes a gate terminal 182i and a source terminal 186i. The gate terminal 182i of the transistor 180i receives a signal 181i, and the source terminal 186i of the transistor 180i is connected to the terminal 190i (e.g., a port terminal). For example, the control signal 153 includes the signal 181i, which is used to turn on and/or turn off the transistor 180i. As an example, the port terminal 190i is used to charge a load device.
The operational amplifier 120i receives a voltage from the terminal 112i of the resistor 110i and also receives a voltage from the terminal 114i of the resistor 110i and in response generates a detection signal 127i. The detection signal 127i represents a magnitude of a current 115i that flows from the terminal 104 to the terminal 190i through the resistor 110i and the transistor 180i. The signal combiner 130 receives the detection signal 127i and in response generates a combined detection voltage 131. The combined detection voltage 131 represents a sum of the magnitude of the current 115i, the magnitude of the current 1152, . . . , and the magnitude of the current 115N. The sum of the magnitude of the current 1151, the magnitude of the current 1152, . . . , and the magnitude of the current 115N is equal to the magnitude of the current 103 that flows out of the power management system 102 at the terminal 104. The combined detection voltage 131 represents the magnitude of the current 103. The power converter 150 receives the combined detection voltage 131 and uses the combined detection voltage 131 to regulate the magnitude of the current 103 in order to keep the magnitude of the current 103 at a constant level.
The detection signal 127, is a current that represents a magnitude of the current 115, that flows from the terminal 104 to the terminal 190, through the transistor 180i. The signal combiner 130 receives the detection current 12′71, the detection current 1272, . . . , and the detection current 127N and generates a combined detection current that is equal to a sum of the detection current 12′71, the detection current 1272, . . . , and the detection current 127N. As an example, the combined detection current flows through a resistor that is a part of the signal combiner 130 to convert the combined detection current to the combined detection voltage 131.
As discussed above, the conventional current detection system is used to establish a stable magnitude for the current 103 that flows out of the power management system 102 by detecting one or more voltages across the one or more resistors 1101 , 1102 , . . . , and 110N respectively, amplifying the one or more detected voltages to generate the one or more detection voltages 12′71, 1272, . . . , and 127N, combining the one or more detection voltages 1271, 1272, . . . , and 127N to generate the combined detection voltage 131, and providing the combined detection voltage 131 to the main loop in order to regulate the magnitude of the current 103. In some examples, N is equal to 1. For example, the charging system 100 includes the resistor 1101, the operational amplifier 1201, the transistor 1801, and the terminal 1901. As an example, example, i is equal to 1, and i cannot be larger than 1.
Referring to
The use of the one or more resistors 1101, 1102, . . . , and 110N often cause circuit loss and also reduce efficiency of the charging system 100. In order to reduce circuit loss, each resistor of the one or more resistors 1101, 1102, . . . , and 110N has a small resistance value (e.g., 5 mΩ). Also, conventional clock signal generators often use an input clock signal to generate a clock signal at a lower voltage level and then use a level shifter to convert the clock signal at the lower voltage level to another clock signal at a higher voltage level, but the clock signal at the lower voltage level and the clock signal at the higher voltage usually cannot be kept completely synchronized for a wide voltage range.
Hence it is highly desirable to improve the technique for current detection of a charging system.
Certain embodiments of the present invention are directed to circuits. More particularly, some embodiments of the invention provide systems and methods for detecting currents. Merely by way of example, some embodiments of the invention have been applied to power management systems. But it would be recognized that the invention has a much broader range of applicability.
According to some embodiments, a system for detecting one or more currents includes: one or more current sampling units coupled to one or more terminal transistors respectively and configured to sample one or more terminal currents that flow between a system terminal of a power management system and one or more port terminals through the one or more terminal transistors respectively; one or more operational amplifiers coupled to the one or more current sampling units respectively and configured to generate one or more detection currents respectively, the one or more detection currents representing one or more magnitudes of the one or more terminal currents respectively; and a signal combiner configured to receive the one or more detection currents, generate a combined detection voltage representing a sum of the one or more magnitudes of the one or more terminal currents, and output the combined detection voltage to the power management system to regulate the sum of the one or more magnitudes of the one or more terminal currents.
According to certain embodiments, a chopper amplifier includes: a ground voltage generator configured to receive a first ground voltage and a system voltage and generate a second ground voltage based at least in part on the first ground voltage and the system voltage; a clock signal generator configured to receive an input clock signal, the first ground voltage and the second ground voltage and generate a first clock signal and a second clock signal based at least in part on the input clock signal, the first ground voltage and the second ground voltage; and a chopper and amplification unit including a first chopper unit, a second chopper unit coupled to the first chopper unit through multiple transistors, and a third chopper unit coupled to the second chopper unit through multiple transistors; wherein: the second ground voltage is higher than or equal to the first ground voltage; wherein: if the first clock signal is equal to the first ground voltage, the first clock signal is at a logic low level; and if the second clock signal is equal to the second ground voltage, the second clock signal is at the logic low level; wherein: the first chopper unit is configured to receive the second clock signal; the second chopper unit is configured to receive the second clock signal; and the third chopper unit is configured to receive the first clock signal.
According to some embodiments, a method for detecting one or more currents includes: sampling one or more terminal currents that flow between a system terminal of a power management system and one or more port terminals through one or more terminal transistors respectively; generating one or more detection currents representing one or more magnitudes of the one or more terminal currents respectively; receiving the one or more detection currents; generating a combined detection voltage representing a sum of the one or more magnitudes of the one or more terminal currents; and outputting the combined detection voltage to the power management system to regulate the sum of the one or more magnitudes of the one or more terminal currents.
Depending upon embodiment, one or more benefits may be achieved. These benefits and various additional objects, features and advantages of the present invention can be fully appreciated with reference to the detailed description and accompanying drawings that follow.
Certain embodiments of the present invention are directed to circuits. More particularly, some embodiments of the invention provide systems and methods for detecting currents. Merely by way of example, some embodiments of the invention have been applied to power management systems. But it would be recognized that the invention has a much broader range of applicability.
As shown in
According to some embodiments, if the resistance value of each resistor of the one or more resistors 1101, 1102, . . . , and 110N is small, when the magnitude of the current 115i is small, the voltage received by the terminal 122i minus the voltage received by the terminal 124i is also small, reducing signal-to-noise ratio and/or reducing detection accuracy for small currents. For example, when the terminal 190i needs the current 115i to be small, the conventional current detection system as shown in
In certain embodiments, the current detection system is configured to regulate a current 203 that flows out of the power management system 202 at a terminal 204. For example, as part of the power management system 202, the power supply 240 provides a voltage 241 to the power converter 250. As an example, in response, the power converter 250 (e.g., a DC-DC converter) generates a voltage 251, which is used by the output inductor 260 and the output capacitor 270 to generate a voltage 205 at the terminal 204. For example, additionally, the power converter 250 (e.g., a DC-DC converter) also generates a control signal 253. As an example, one terminal of the output capacitor 270 is biased to a ground voltage 271.
In some embodiments, the terminal 204 is connected to a drain terminal 284i of the transistor 280i and an input terminal 212i of the current sampling unit 210i, wherein i is an integer larger than or equal to 1 but smaller than or equal to N. For example, the transistor 280i also includes a gate terminal 282i and a source terminal 286i. As an example, the current sampling unit 210i also includes an input terminal 214i, an output terminal 216i, and an output terminal 218i. In certain examples, the input terminal 214i of the current sampling unit 210i is connected to the source terminal 286i of the transistor 280i and is also connected to the terminal 290i (e.g., a port terminal). For example, the port terminal 290i is used to charge a load device. As an example, the gate terminal 282i of the transistor 280i receives a signal 281i, which is a part of the control signal 253 and is used to turn on and/or turn off the transistor 280i. In some examples, the output terminal 216i of the current sampling unit 210i is connected to an input terminal 222i (e.g., an “+” terminal) of the operational amplifier 220i, and the output terminal 218i of the current sampling unit 210i is connected to an input terminal 224i (e.g., an “−” terminal) of the operational amplifier 220i. For example, the operational amplifier 220i also includes an output terminal 226i.
According to certain embodiments, the operational amplifier 220i generates a detection signal 227i at the output terminal 226i. For example, the detection signal 227i represents a magnitude of a current 215i that flows from the terminal 204 to the terminal 290i through the transistor 280i. In some examples, the signal combiner 230 receives the detection signal 227i and in response generates a combined detection voltage 231. For example, the combined detection voltage 231 represents a sum of the magnitude of the current 215i, the magnitude of the current 2152, . . . , and the magnitude of the current 215N. In certain examples, the sum of the magnitude of the current 2151, the magnitude of the current 2152, . . . , and the magnitude of the current 215N is equal to the magnitude of the current 203 that flows out of the power management system 202 at the terminal 204. For example, the combined detection voltage 231 represents the magnitude of the current 203. As an example, the power converter 250 receives the combined detection voltage 231 and uses the combined detection voltage 231 to regulate the magnitude of the current 203 in order to keep the magnitude of the current 203 at a constant level.
In some examples, the detection signal 227i is a current that represents a magnitude of the current 215i that flows from the terminal 204 to the terminal 290i through the transistor 280i. For example, the signal combiner 230 receives the detection current 2271, the detection current 2272, . . . , and the detection current 227N and generates a combined detection current that is equal to a sum of the detection current 2271, the detection current 2272, . . . , and the detection current 227N. As an example, the combined detection current flows through a resistor that is a part of the signal combiner 230 to convert the combined detection current to the combined detection voltage 231.
According to some embodiments, as shown in
In certain embodiments, the operational amplifier 220i is configured to perform a chopper function and/or amply a current with a predetermined constant ratio. For example, the operational amplifier 220i includes a chopper amplifier that is configured to process high voltages and also includes a digital-to-analog converter (DAC).
As discussed above and further emphasized here,
In certain embodiments, the current sampling unit 210i includes the transistor 310i (e.g., a field-effect transistor) and the transistor 320i. (e.g., a field-effect transistor). For example, a drain terminal of the transistor 310i is connected to the source terminal 286i of the transistor 280i and the terminal 290i, and a drain terminal of the transistor 320i is connected to the drain terminal 284i of the transistor 280i and the terminal 204. As an example, the gate terminal of the transistor 310i and the gate terminal of the transistor 320i are connected to the gate terminal 282i of the transistor 280i. In some examples, the gate terminal of the transistor 310i, the gate terminal of the transistor 320i, and the gate terminal 282i of the transistor 280i all receive the signal 281i. For example, the transistor 310i, the transistor 320i, and the transistor 280i are all turned on if the signal 281i is at a logic high level. As an example, the transistor 310i, the transistor 320i, and the transistor 280i are all turned off if the signal 281i is at a logic low level. In certain examples, the source terminal of the transistor 310i is connected to an inverting input terminal 332i (e.g., the “−” terminal) of the chopper amplifier 330i, and the source terminal of the transistor 320i is connected to a non-inverting input terminal 334i (e.g., the “+” terminal) of the chopper amplifier 330i. For example, the transistor 280i, the transistor 310i and the transistor 320i each are an NMOS transistor. As an example, the size of the transistor 310i and the size of the transistor 320i are the same, equal to the size of the transistor 280i multiplied by a predetermined ratio.
In some embodiments, the chopper amplifier 330i also includes an output terminal 336i. For example, the output terminal 336i of the chopper amplifier 330i is connected to a gate terminal of the transistor 340i, which also includes a drain terminal and a source terminal. As an example, the drain terminal of the transistor 340i is connected to the source terminal of the transistor 320i and the non-inverting input terminal 334i (e.g., the “+” terminal) of the chopper amplifier 330i, and the source terminal of the transistor 340i is connected to a drain terminal and a gate terminal of the transistor 342i. In certain examples, the gate terminal of the transistor 342i is also connected to a terminal 352i of the digital-to-analog converter (DAC) 350i, which also includes a terminal 354i and a terminal 356i. For example, the terminal 356i of the digital-to-analog converter (DAC) 350i and a source terminal of the transistor 342i are biased to the ground voltage 271. As an example, the terminal 354i of the digital-to-analog converter (DAC) 350i are connected to a drain terminal and a gate terminal of the transistor 344i. In some examples, the gate terminal of the transistor 344i is also connected to a gate terminal of the transistor 346i. For example, a source terminal of the transistor 344i and a source terminal of the transistor 346i both are biased to a supply voltage 391. As an example, a drain terminal of the transistor 346i provides a detection signal 227i, which is a current that flows out of the drain terminal of the transistor 346i.
According to certain embodiments, the chopper amplifier 330i operates in a closed loop with transistor 340i so that the inverting input terminal 332i (e.g., the “−” terminal) and the non-inverting input terminal 334i (e.g., the “+” terminal) of the chopper amplifier 330i are at the same voltage level. For example, the non-inverting input terminal 334i (e.g., the “+” terminal) of the chopper amplifier 330i serves as the input terminal 222i (e.g., the “+” terminal) of the operational amplifier 220i. As an example, the inverting input terminal 332i (e.g., the “−” terminal) of the chopper amplifier 330i serves as the input terminal 224i (e.g., the “−” terminal) of the operational amplifier 220i. In some examples, a current 337i that flows through the transistor 340i is equal to the current 215i multiplied by a predetermined constant. For example, the current 337i is a sampling current of the current 215i. In certain examples, the transistor 340i, the transistor 342i, the transistor 344i, and the transistor 346i are parts of a current mirror. For example, the current mirror receives a current 337i and generates the detection current 227i.
According to some embodiments, the detection current 227i is determined as follows:
where I227i represents the detection current 227i, and I215i represents the current 215i. Additionally, Roni represents the on resistance of the transistor 280i, and Rsnsi represents the on resistance of the transistor 310i or the on resistance of the transistor 320i, wherein the on resistance of the transistor 310i and the on resistance of the transistor 320i are equal. Moreover, Ni represents a ratio of the size of the transistor 280i to the size of the transistor 310i or a ratio of the size of the transistor 280i to the size of the transistor 320i, wherein the size of the transistor 310i and the size of the transistor 320i are equal. Also, αi represents the current ratio of the current mirror that includes the transistor 340i, the transistor 342i, the transistor 344i, and the transistor 346i.
In certain examples, the current ratio αi of the current mirror is equal to the detection current 227i divided by the current 337i. For example, the current ratio αi of the current mirror is adjusted by the digital-to-analog converter (DAC) 350i. In some examples, as shown by Equation 1, the detection current 227i depends on the ratio Ni of the size of the transistor 280i to the size of the transistor 310i or of the size of the transistor 280i to the size of the transistor 320i and also depends on the current ratio αi of the current mirror that includes the transistor 340i, the transistor 342i, the transistor 344i, and the transistor 346i.
In some examples, the signal combiner 230 includes the current combiner 360 and the resistor 370. For example, the current combiner 360 receives the one or more detection currents 2271, 2272, . . . , and 227N and generate a combined current 361. As an example, the combined current 361 is determined as follows:
I361=Σi=1NI227i (Equation 2)
where I361 represents the combined current 361, and I227i represents the detection current 227i. For example, N is equal to 1. As an example, N is a positive integer larger than 1.
As shown in
V
231
=I
361
×R
370=(Σhd i=1NI227i)×R370 (Equation 3)
where V231 represents the combined detection voltage 231, and I361 represents the combined current 361. Additionally, R370 represents the resistance of the resistor 370, and I227i represents the detection current 227i. For example, N is equal to 1. As an example, N is a positive integer larger than 1. In certain examples, based on Equation 3,
V
231=(I2271+I2272+ . . . +I227N)×R370 (Equation 4)
where V231 represents the combined detection voltage 231 and R370 represents the resistance of the resistor 370. Additionally, I2271, I2272, . . . , and I227N represent the one or more detection currents 2271, 2272, . . . , and 227N respectively. For example, N is equal to 1. As an example, N is a positive integer larger than 1.
According to some embodiments, the virtual ground voltage generator 430i receives the voltage 205, the ground voltage 271, a control voltage 433i and a reference current 435i and generates a virtual ground voltage 431i based at least in part on the voltage 205 according to some embodiments. For example, if the voltage 205 is lower than a predetermined threshold (e.g., 5 volts), the virtual ground voltage generator 430i generates the virtual ground voltage 431i that is equal to the ground voltage 271. As an example, if the voltage 205 is higher than the predetermined threshold (e.g., 5 volts), the virtual ground voltage generator 430i generates the virtual ground voltage 431i that is equal to the voltage 205 minus a predetermined value (e.g., 5 volts).
According to certain embodiments, the clock signal generator 420i receives the virtual ground voltage 431i, the ground voltage 271, the voltage 205, and a clock signal 421i and generates clock signals 423i, 425i, 427i and 429i based at least in part on the virtual ground voltage 431i, the ground voltage 271, the voltage 205, and the clock signal 421i. For example, if the clock signal 423i is at a logic high level, the clock signal 425i is at a logic low level, and if the clock signal 423i is at the logic low level, the clock signal 425i is at the logic high level. As an example, if the clock signal 427i is at the logic high level, the clock signal 429i is at the logic low level, and if the clock signal 427i is at the logic low level, the clock signal 429i is at the logic high level.
In some examples, the supply voltage 391 minus the ground voltage 271 is equal to 5 volts, and the voltage 205 minus the virtual ground voltage 431i, is also equal to 5 volts. For example, if the clock signal 423i is equal to the supply voltage 391, the clock signal 423i is at the logic high level, and if the clock signal 423i is equal to the ground voltage 271, the clock signal 423i is at the logic low level. As an example, if the clock signal 425i is equal to the supply voltage 391, the clock signal 425i is at the logic high level, and if the clock signal 425i is equal to the ground voltage 271, the clock signal 425i is at the logic low level. For example, if the clock signal 427i is equal to the voltage 205, the clock signal 427i is at the logic high level, and if the clock signal 427i is equal to the virtual ground voltage 431i, the clock signal 427i is at the logic low level. As an example, if the clock signal 429i is equal to the voltage 205, the clock signal 429i is at the logic high level, and if the clock signal 429i is equal to the virtual ground voltage 431i, the clock signal 429i is at the logic low level. In certain examples, each clock signal of the clock signals 423i, 425i, 427i and 429i has a duty cycle that is equal to 50%.
As shown in
In some embodiments, the chopper unit 440i is a high-voltage chopper unit, and the transistors 442i, 444i, 446i, and 448i provide four branches for the high-voltage chopper unit 440i. In certain examples, the transistors 442i, 444i, 446i, and 448i each are a PMOS transistor. For example, a gate terminal of the transistor 442i and a gate terminal of the transistor 448i both receive the clock signal 429i. As an example, a gate terminal of the transistor 444i and a gate terminal of the transistor 446i both receive the clock signal 427i. In some examples, a source terminal of the transistor 442i and a source terminal of the transistor 446i are connected to the source terminal of the transistor 310i, and a source terminal of the transistor 444i and a source terminal of the transistor 448i are connected to the source terminal of the transistor 320i. For example, a drain terminal of the transistor 442i and a drain terminal of the transistor 444i are connected to a source terminal of the transistor 472i. As an example, a drain terminal of the transistor 446i and a drain terminal of the transistor 448i are connected to a source terminal of the transistor 474i.
In certain embodiments, the chopper unit 450i is a high-voltage chopper unit, and the transistors 452i, 454i, 456i, and 458i provide four branches for the high-voltage chopper unit 450i. In certain examples, the transistors 452i, 454i, 456i, and 458i each are a PMOS transistor. For example, a gate terminal of the transistor 452i and a gate terminal of the transistor 458i both receive the clock signal 429i. As an example, a gate terminal of the transistor 454i and a gate terminal of the transistor 456i both receive the clock signal 427i. In some examples, a source terminal of the transistor 452i and a source terminal of the transistor 456i are connected to a drain terminal of the transistor 472i, and a source terminal of the transistor 454i and a source terminal of the transistor 458i are connected to a drain terminal of the transistor 474i. For example, a drain terminal of the transistor 452i and a drain terminal of the transistor 454i are connected to a source terminal of the transistor 476i. As an example, a drain terminal of the transistor 456i and a drain terminal of the transistor 458i are connected to a source terminal of the transistor 478i.
In some embodiments, the chopper unit 460i is a low-voltage chopper unit, and the transistors 452i, 454i, 456i, and 458i provide four branches for the low-voltage chopper unit 460i. In certain examples, the transistors 462i, 464i, 466i, and 468i each are an NMOS transistor. For example, a gate terminal of the transistor 462i and a gate terminal of the transistor 468i both receive the clock signal 423i. As an example, a gate terminal of the transistor 464i and a gate terminal of the transistor 466i both receive the clock signal 425i. In some examples, a drain terminal of the transistor 462i and a drain terminal of the transistor 466i are connected to a source terminal of the transistor 484i, and a drain terminal of the transistor 464i and a drain terminal of the transistor 468i are connected to a source terminal of the transistor 486i. For example, a source terminal of the transistor 462i and a source terminal of the transistor 464i are connected to a drain terminal of the transistor 488i. As an example, a source terminal of the transistor 466i and a source terminal of the transistor 468i are connected to a drain terminal of the transistor 490i.
In certain examples, the transistors 472i and 474i each are a PMOS transistor (e.g., a low-voltage PMOS transistor). For example, a gate terminal of the transistor 472i and a gate terminal of the transistor 474i both receive a control signal 473i. In some examples, the transistors 476i and 478i each are a PMOS transistor (e.g., a high-voltage PMOS transistor). For example, a gate terminal of the transistor 476i and a gate terminal of the transistor 478i both receive a control signal 477i. In certain examples, the transistors 480, and 482, each are an NMOS transistor (e.g., a high-voltage NMOS transistor). For example, a gate terminal of the transistor 480i and a gate terminal of the transistor 482i both receive a control signal 481i. As an example, a drain terminal of the transistor 480i is connected to a drain terminal of the transistor 476i, and a drain terminal of the transistor 482i is connected to a drain terminal of the transistor 478i. In some examples, the transistors 484i and 486i each are an NMOS transistor (e.g., a low-voltage NMOS transistor). For example, a gate terminal of the transistor 484i and a gate terminal of the transistor 486i both receive a control signal 485i. As an example, a drain terminal of the transistor 484i is connected to a source terminal of the transistor 480i, and a drain terminal of the transistor 486i is connected to a source terminal of the transistor 482i. In certain examples, the transistors 488i and 490i each are an NMOS transistor (e.g., a low-voltage NMOS transistor). For example, a gate terminal of the transistor 488i and a gate terminal of the transistor 490i both receive a control signal 489i. As an example, a source terminal of the transistor 488, and a source terminal of the transistor 490i both are biased to the ground voltage 271.
According to certain embodiments, if the clock signal 421i is at the logic high level, the clock signal generator 420i generates the clock signals 423i and 427i at the logic high level and the clock signals 425i and 429i at the logic low level. For example, if the clock signal 421i is at the logic high level, the transistors 442i, 472i, 452i, 476i, 480i, 484i, 462i, and 488i are turned on, allowing a current to flow from the source terminal of the transistor 310i. As an example, if the clock signal 421i is at the logic high level, the transistors 448i, 474i, 458i, 478i, 482i, 486i, 468i, and 490i are also turned on, allowing a current to flow from the source terminal of the transistor 320i.
According to some embodiments, if the clock signal 421i is at the logic low level, the clock signal generator 420i generates the clock signals 423i and 427i at the logic low level and the clock signals 425i and 429i at the logic high level. For example, if the clock signal 421i is at the logic low level, the transistors 446i, 474i, 454i, 476i, 480i, 484i, 466i, and 490i are turned on, allowing a current to flow from the source terminal of the transistor 310i. As an example, if the clock signal 421i is at the logic low level, the transistors 444i, 472i, 456i, 478i, 482i, 486i, 464i, and 488i are also turned on, allowing a current to flow from the source terminal of the transistor 320i.
In certain examples, if the clock signal 421i changes from the logic high level to the logic low level, the transistors 472i and 488i change from receiving the current that flows from the source terminal of the transistor 310i to receiving the current that flows from the source terminal of the transistor 320i, and the transistors 474i and 490i change from receiving the current that flows from the source terminal of the transistor 320i to receiving the current that flows from the source terminal of the transistor 310i. In some examples, if the clock signal 421i changes from the logic low level to the logic high level, the transistors 472i and 488i change from receiving the current that flows from the source terminal of the transistor 320i to receiving the current that flows from the source terminal of the transistor 310i, and the transistors 474i and 490i change from receiving the current that flows from the source terminal of the transistor 310i to receiving the current that flows from the source terminal of the transistor 320i.
In certain embodiments, the transistors 472i, 474i, 488i and 490i are configured to perform amplification as parts of the chopper and amplification unit 410i. In some embodiments, the resistor 412i and the capacitor 414i are configured to perform low-pass filtering as parts of the chopper and amplification unit 410i.
As discussed above and further emphasized here,
The voltage converter 520i includes transistors 540i, 542i, 544i, 546i, 548i, and 550i. For example, i is an integer larger than or equal to 1 but smaller than or equal to N. As an example, N is a positive integer. Although the above has been shown using a selected group of components for the clock signal generator 420i, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.
In some embodiments, the voltage converter 510i is used in order to convert the clock signal 421i to the clock signal 427i. For example, the logic high level of the clock signal 421i corresponds to the supply voltage 391, and the logic low level of the clock signal 421i corresponds to the ground voltage 271. As an example, the logic high level of the clock signal 427i corresponds to the voltage 205, and the logic low level of the clock signal 427i corresponds to the virtual ground voltage 431i. In certain examples, the virtual ground voltage 431i is higher than or equal to the ground voltage 271. For example, the voltage converter 510i is a boost converter (e.g., a step-up converter). In some examples, the clock signal 427i is used to generate the clock signal 429i.
In certain embodiments, the voltage converter 520i is used in order to convert the clock signal 427i to the clock signal 423i. For example, the logic high level of the clock signal 427i corresponds to the voltage 205, and the logic low level of the clock signal 427i corresponds to the virtual ground voltage 431i. As an example, the logic high level of the clock signal 423i corresponds to the supply voltage 391, and the logic low level of the clock signal 423i corresponds to the ground voltage 271. In certain examples, the ground voltage 271 is lower than or equal to the virtual ground voltage 431i. For example, the voltage converter 520i is a buck converter (e.g., a step-down converter). In some examples, the clock signal 423i is used to generate the clock signal 425i.
According to some embodiments, the clock signal 423i changes from the logic low level to the logic high level and the clock signal 427i changes from the logic low level to the logic high at the same time, and the clock signal 423i changes from the logic high level to the logic low level and the clock signal 427i changes from the logic high level to the logic low at the same time.
As shown in
According to some embodiments, the virtual ground voltage generator 430i generates the virtual ground voltage 431i that is equal to the voltage 205 minus R1×Iref+VSG620i, wherein R1 represents the resistance of the resistor 610i, Iref represents the reference current 435i, and VSG620i represents a voltage at a source terminal of the transistor 620i minus a voltage at a gate terminal of the transistor 620i. For example, the transistor 620i includes the source terminal 662i, the gate terminal 664i, and a drain terminal 666i. As an example, VSG620i represents the voltage at the source terminal 662i minus the voltage at the gate terminal 664i.
In some embodiments, a gate terminal of the transistor 624i receives the control voltage 433i. For example, if the voltage 205 is smaller than a predetermined threshold, the control voltage 433i is at a logic high level to turn on the transistor 624i. As an example, if the voltage 205 is larger than the predetermined threshold, the control voltage 433i is at a logic low level to turn off the transistor 624i.
In certain embodiments, the virtual ground voltage generator 430i generates the virtual ground voltage 431i as follows:
if V205>Vth,
V
431i
=V
205−(R1×Iref+VSG620i) (Equation 5)
if V205≤Vth,
V431i=V271 (Equation 6)
where V205 represents the voltage 205, and Vth represents a predetermined threshold. Additionally, V431i represents the virtual ground voltage 431i, and V271 represents the ground voltage 271 that is equal to zero volts. Also, R1 represents the resistance of the resistor 610i, and Iref represents the reference current 435i. Additionally, VSG620i represents the voltage at the source terminal 662i minus the voltage at the gate terminal 664i of the transistor 620i. For example, Vth is equal to 5 volts, and R1×Iref+VSG620i is also equal to 5 volts. As an example, according to Equations 5 and 6, the virtual ground voltage 431i is higher than or equal to the ground voltage 271, which is equal to zero volts.
Certain embodiments of the present invention significantly decrease the number of resistors in a current detection system, therefore significantly reducing circuit loss and improving efficiency of a charging system that includes the current detection system. Some embodiments of the present invention provide a current detection system that includes an operational amplifier with at least one or more high-voltage chopper units and also includes a digital-to-analog converter (DAC) so that the current detection system performs precise current detection for a wide range of input voltage and/or output voltage of the power management system. For example, the input voltage of the power management system ranges from 3 volts to 48 volts. As an example, the output voltage of the power management system ranges from 3 volts to 48 volts. Certain embodiments of the present invention provide a current detection system that includes an operational amplifier with at least a clock signal generator that generates two clock signals at different voltage levels but completely synchronized in order to avoid chopping residue.
According to some embodiments, a system for detecting one or more currents includes: one or more current sampling units coupled to one or more terminal transistors respectively and configured to sample one or more terminal currents that flow between a system terminal of a power management system and one or more port terminals through the one or more terminal transistors respectively; one or more operational amplifiers coupled to the one or more current sampling units respectively and configured to generate one or more detection currents respectively, the one or more detection currents representing one or more magnitudes of the one or more terminal currents respectively; and a signal combiner configured to receive the one or more detection currents, generate a combined detection voltage representing a sum of the one or more magnitudes of the one or more terminal currents, and output the combined detection voltage to the power management system to regulate the sum of the one or more magnitudes of the one or more terminal currents. For example, the system for detecting one or more currents is implemented according to at least
As an example, the one or more current sampling units include a first sampling unit; the one or more terminal transistors include a first terminal transistor; the one or more terminal currents include a first terminal current; the one or more port terminals include a first port terminal; the one or more operational amplifiers include a first operational amplifier; the one or more detection currents include a first detection current; and the one or more magnitudes of the one or more terminal currents include a first magnitude of the first terminal current. For example, the first current sampling unit is coupled to the first terminal transistor and configured to sample the first terminal current that flows between the system terminal of the power management system and the first port terminal through the first terminal transistor; and the first operational amplifier is coupled to the first current sampling unit and configured to generate the first detection current, the first detection current representing the first magnitude of the first terminal current. As an example, the one or more current sampling units include a second sampling unit; the one or more terminal transistors include a second terminal transistor; the one or more terminal currents include a second terminal current; the one or more port terminals include a second port terminal; the one or more operational amplifiers include a second operational amplifier; the one or more detection currents include a second detection current; and the one or more magnitudes of the one or more terminal currents include a second magnitude of the second terminal current. For example, the second current sampling unit is coupled to the second terminal transistor and configured to sample the second terminal current that flows between the system terminal of the power management system and the second port terminal through the second terminal transistor; and the second operational amplifier is coupled to the second current sampling unit and configured to generate the second detection current, the second detection current representing the second magnitude of the second terminal current. As an example, the signal combiner is further configured to receive at least the first detection current and the second detection current, generate the combined detection voltage representing the sum of at least the first magnitude of the first terminal current and the second magnitude of the second terminal current, and output the combined detection voltage to the power management system to regulate the sum of at least the first magnitude of the first terminal current and the second magnitude of the second terminal current.
For example, the first terminal transistor includes a first transistor terminal, a second transistor terminal, and a third transistor terminal; wherein: the second transistor terminal is connected to the system terminal of the power management system; and the third transistor terminal is connected to the first port terminal. As an example, the first sampling unit includes a first sampling transistor and a second sampling transistor; wherein: the first sampling transistor includes a fourth transistor terminal, a fifth transistor terminal, and a sixth transistor terminal; and the second sampling transistor includes a seventh transistor terminal, an eighth transistor terminal, and a ninth transistor terminal. For example, the fourth transistor terminal and the seventh transistor terminal each are connected to the first transistor terminal; the fifth transistor terminal is connected to the third transistor terminal; and the eighth transistor terminal is connected to the second transistor terminal.
As an example, the first operational amplifier includes a first amplifier terminal, a second amplifier terminal, and a third amplifier terminal; wherein: the first amplifier terminal is connected to the sixth transistor terminal of the first sampling transistor; and the second amplifier terminal is connected to the ninth transistor terminal of the second sampling transistor. For example, the first operational amplifier is further configured to generate the first detection current at the third amplifier terminal. As an example, wherein the first operational amplifier further includes: a chopper amplifier; a current mirror coupled to the chopper amplifier; and a digital-to-analog converter coupled to the current mirror. For example, the current mirror of the first operational amplifier is configured to output the first detection current.
According to certain embodiments, a chopper amplifier includes: a ground voltage generator configured to receive a first ground voltage and a system voltage and generate a second ground voltage based at least in part on the first ground voltage and the system voltage; a clock signal generator configured to receive an input clock signal, the first ground voltage and the second ground voltage and generate a first clock signal and a second clock signal based at least in part on the input clock signal, the first ground voltage and the second ground voltage; and a chopper and amplification unit including a first chopper unit, a second chopper unit coupled to the first chopper unit through multiple transistors, and a third chopper unit coupled to the second chopper unit through multiple transistors; wherein: the second ground voltage is higher than or equal to the first ground voltage; wherein: if the first clock signal is equal to the first ground voltage, the first clock signal is at a logic low level; and if the second clock signal is equal to the second ground voltage, the second clock signal is at the logic low level; wherein: the first chopper unit is configured to receive the second clock signal; the second chopper unit is configured to receive the second clock signal; and the third chopper unit is configured to receive the first clock signal. For example, the chopper amplifier is implemented according to at least
As an example, a clock signal generator includes: a first voltage converter configured to, with one or more other components, convert the input clock signal to the second clock signal; and a second voltage converter configured to, with one or more other components, convert the second clock signal to the first clock signal. For example, the ground voltage generator is further configured to: if the system voltage is larger than a predetermined threshold, generate the second ground voltage to be equal to the system voltage minus a predetermined magnitude; and if the system voltage is smaller than the predetermined threshold, generate the second ground voltage to be equal to the first ground voltage.
According to some embodiments, a method for detecting one or more currents includes: sampling one or more terminal currents that flow between a system terminal of a power management system and one or more port terminals through one or more terminal transistors respectively; generating one or more detection currents representing one or more magnitudes of the one or more terminal currents respectively; receiving the one or more detection currents; generating a combined detection voltage representing a sum of the one or more magnitudes of the one or more terminal currents; and outputting the combined detection voltage to the power management system to regulate the sum of the one or more magnitudes of the one or more terminal currents. For example, the method for detecting one or more currents is implemented according to at least
As an example, the one or more terminal transistors include a first terminal transistor; the one or more terminal currents include a first terminal current; the one or more port terminals include a first port terminal; the one or more detection currents include a first detection current; and the one or more magnitudes of the one or more terminal currents include a first magnitude of the first terminal current. For example, the sampling one or more terminal currents that flow between a system terminal of a power management system and one or more port terminals through one or more terminal transistors respectively includes sampling the first terminal current that flows between the system terminal of the power management system and the first port terminal through the first terminal transistor; and the generating one or more detection currents representing one or more magnitudes of the one or more terminal currents respectively includes generating the first detection current representing the first magnitude of the first terminal current. As an example, the receiving the one or more detection currents includes receiving at least the first detection current; and the generating a combined detection voltage representing a sum of the one or more magnitudes of the one or more terminal currents includes generating the combined detection voltage representing the sum of at least the first magnitude of the first terminal current. For example, the sum of the one or more magnitudes of the one or more terminal currents is equal to the first magnitude of the first terminal current.
In certain examples, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. In some examples, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. For example, the one or more current sampling units 2101, 2102, . . . , and 210N each are implemented in one or more circuits. As an example, the chopper and amplification unit 410i is implemented in one or more circuits. For example, the chopper units 440i, 450i and 460i each are implemented in one or more circuits. As an example, various embodiments and/or examples of the present invention can be combined.
Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202111255368.9 | Oct 2021 | CN | national |
