SYSTEMS AND METHODS FOR DIGITAL CONTROL

Abstract

Methods and systems for digital control.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a conventional single phase buck regulator;

FIG. 2 shows a block diagram representation of an embodiment of a digital controller including an oversampling ADC and a compensating filter;

FIG. 3 shows a block diagram representation of an embodiment of a digital controller of these teachings;

FIG. 4 shows a block diagram representation of a detailed embodiment of the digital controller of these teachings;

FIG. 5 shows a block diagram representation of yet another detailed embodiment of the digital controller of these teachings;

FIG. 6 shows a block diagram representation of a further embodiment of the digital controller of these teachings;

FIG. 7 shows a block diagram representation of a conventional second order Sigma Delta modulator;

FIG. 8 depicts a block diagram representation of an embodiment of a component of the digital controller of these teachings;

FIG. 9 depicts a block diagram representation of another embodiment of a component of the digital controller of these teachings;

FIG. 10 depicts a block diagram representation of yet another embodiment of a component of the digital controller of these teachings;

FIG. 11 shows a block diagram representation of another embodiment of a digital controller of these teachings;

FIG. 12 shows a block diagram representation of yet another embodiment of a digital controller of these teachings;

FIGS. 13 a and 13b show a schematic graphical representation of results from simulation of an embodiment of these teachings;

FIG. 14 shows a block diagram representation of an embodiment of a system of these teachings for collecting realtime performance data from a digital power management component;

FIG. 15 shows a block diagram representation of a component of the embodiment shown in FIG. 14;

FIG. 16 shows a block diagram representation of an embodiment of a component of the system shown in FIG. 14;

FIG. 17 shows a schematic graphical representation of timing for data transfer utilizing the embodiment shown in FIG. 16;

FIG. 18 shows a block diagram representation of a further embodiment of a component of the digital controller of these teachings; and

FIG. 19 shows a schematic graphical representation of results from simulation of the embodiment of FIG. 18.

Claims

1. A digital controller comprising: a modulating component capable of receiving an analog signal and providing an oversampled signal;a compensating filter capable of receiving the oversampled signal;a low pass filter capable of receiving an output from said compensating filter and of providing a low pass filter output having substantially reduced amplitude at a frequency greater than a predetermined frequency; anda sub sampling component capable of receiving the low pass filter output and of providing a subsampled output, the subsampled output having a subsampled rate lower than a rate of the oversampled signal.

2. The digital controller of claim 1 further comprising: another compensating filter capable of receiving the subsampled output and of providing a compensator output at the subsampled rate;a filter substantially equivalent to said compensating filter and said another compensating filter at the subsampled rate being a predetermined compensating filter.

3. The digital controller of claim 2 further comprising: a digital pulse width modulator capable of receiving the compensator output at the subsampled rate and of providing a plurality of pulse control pulses.

4. The digital controller of claim 2 wherein said compensating filter is obtained from a numerator of a predetermined compensating filter.

5. The digital controller of claim 4 wherein said another compensating filter is substantially a discrete integrator; and wherein said predetermined compensating filter is substantially a PID compensating filter.

6. The digital controller of claim 1 further comprising: a digital pulse width modulator capable of receiving the compensator output at the subsampled rate and of providing a plurality of pulse control pulses.

7. The controller of claim 1 wherein said compensating filter comprises: a plurality of sub-filters; each one output of each sub-filter from said plurality of sub-filters being multiplied by a value from a plurality of values, each one output of each sub-filter after being multiplied by said value being one weighted outputs from a plurality of weighted outputs; andthe output from said compensating filter being a sum of said plurality of weighted outputs.

8. The digital controller of claim 1 wherein said modulating component is a Sigma Delta modulator.

9. The digital controller of claim 1 wherein said modulating component comprises: a sample and hold component receiving the analog signal;a repeating ramp generator; an output of said repeating ramp generator being subtracted from an output of said sample and hold component; anda comparator receiving a signal resulting from subtracting the output of said repeating ramp generator from the output of said sample and hold component;an output of said comparator being said oversampled signal.

10. The digital controller of claim 9 wherein said repeating ramp generator comprises a voltage controlled oscillator.

11. The digital controller of claim 10 wherein said voltage controlled oscillator is a resettable oscillator.

12. The digital controller of claim 9 wherein said modulating component comprises a resetting component capable of resetting said modulating component to lower resolution.

13. The digital controller of claim 1 wherein said modulating component comprises; a low resolution analog to digital converting component; an output of said low-resolution analog-to-digital converting component being the oversampled signal;a discrete integrator receiving the oversampled signal; anda high. resolution digital to analog converting component; said high-resolution digital to analog converting system receiving an output of said discrete integrator;said low-resolution analog-to-digital converting component receiving a signal comprising a difference between the analog signal and an output of said high-resolution digital to analog converting component.

14. The digital controller of claims 13 wherein said compensating filter and said low pass filter comprise a discrete integrator.

15. The digital controller of claim 1 wherein said modulating component comprises; a low resolution analog to digital converting componenta variable gain component capable of receiving an output of said low-resolution analog to digital converting component and of providing a variable gain component output substantially equal to a variable multiplying factor times the output of said low-resolution analog-to-digital converting component; said variable gain component being also capable of receiving a gain setting signal and of modifying said variable multiplying factor in response to said gain setting signal; said variable gain component output being the oversampled signal;a discrete integrator receiving the variable gain component output; anda high. resolution digital to analog converting system; said high-resolution digital to analog converting system receiving an output of said discrete integrator;said low-resolution analog-to-digital converting system receiving a signal comprising a difference between the analog signal and an output of said high-resolution digital to analog converting system.

16. The digital controller of claim 15 wherein said compensating filter and said low pass filter comprise a discrete integrator.

17. A controller comprising: a dither generating component capable of receiving an input signal having an input time resolution and of providing a dither output signal having a lower time resolution than the input time resolution; an average of the dither output signal being substantially equivalent to the input signal; anda digital pulse width modulator capable of receiving the dither output signal and of providing a plurality of pulse control pulses; said dither output signal determining at least one characteristic of said plurality of pulse control pulses.

18. The controller of claim 17 wherein said dither generating component comprises: a quantizer component capable of generating the dither output signal;a delay component capable of receiving the dither output signal and of providing a delayed dither output signal; anda discrete integrator component capable of receiving a difference between the input signal and the delayed dither output signal and also capable of providing a discrete integrator output to said quantizer.

19. The controller of claim 17 wherein said dither generating component comprises: a quantizer component capable of generating the dither output signal;a delay component capable of receiving the dither output signal and of providing a delayed dither output signal; anda first discrete integrator component capable of receiving a difference between the input signal and the delayed dither output signal and also capable of providing a first discrete integrator output; anda second discrete integrator capable of receiving a difference between the first discrete integrator output and the delayed dither output signal and also capable of providing a second discrete integrator output to said quantizer.

20. The digital controller of claim 1 further comprising: a dither generating component capable of receiving the subsampled signal and of providing a dither output signal having a lower time resolution than the subsampled signal resolution; an average of the dither output signal being substantially equivalent to the subsampled signal; anda digital pulse width modulator capable of receiving the dither output signal and of providing a plurality of pulse control pulses; said dither output signal determining at least one characteristic of said plurality of pulse control pulses.

21. The digital controller of claim 20 wherein said dither generating component comprises: a quantizer component capable of generating the dither output signal;a delay component capable of receiving the dither output signal and of providing a delayed dither output signal; anda discrete integrator component capable of receiving a difference between the subsampled signal and the delayed dither output signal and also capable of providing a discrete integrator output to said quantizer.

22. The digital controller of claim 20 wherein said dither generating component comprises: a quantizer component capable of generating the dither output signal;a delay component capable of receiving the dither output signal and of providing a delayed dither output signal; anda first discrete integrator component capable of receiving a difference between the subsampled signal and the delayed dither output signal and also capable of providing a first discrete integrator output; anda second discrete integrator capable of receiving a difference between the first discrete integrator output and the delayed dither output signal and also capable of providing a second discrete integrator output to said quantizer.

23. A controller comprising: a compensating filter component capable of receiving a digital input signal and of providing a compensated digital signal; said compensating filter component comprising at least one predetermined parameter;an error performance filter capable of receiving the digital input signal and of providing a performance indicative signal; anda perturbation generating component capable of receiving the performance indicative signal and of providing values, to said compensating filter component, for said at least one predetermined parameter;a difference between said values and preceding value of said at least one predetermined parameter being substantially small compared to said preceding value.

24. The controller of claim 23 further comprising: an analog to digital converting component capable of receiving an analog input signal and of providing the digital input signal.

25. The controller of claim 23 wherein said error performance filter comprises a filter providing the performance indicative signal, the performance indicative signal being indicative of an absolute value of an error squared.

26. The controller of claim 23 wherein said error performance filter comprises a filter providing the performance indicative signal, the performance indicative signal being indicative of power dissipation.

27. The controller of claim 23 further comprising: a digital pulse width modulator capable of receiving the compensated digital signal and of providing a plurality of pulse control pulses.

28. The controller of claim 27 wherein said digital pulse width modulator comprises at least one PWM predetermined parameter; and wherein said perturbation generating component is capable of providing, to said digital pulse width modulator, values for said at least one PWM predetermined parameter.

29. The controller of claim 23 wherein said perturbation generating component generates said values utilizing random perturbations

30. The controller of claim 23 wherein said perturbation generating component generates said values utilizing a predetermined algorithm.

31. The controller of claim 30 wherein said predetermined algorithm is a gradient search algorithm.

32. The controller of claim 23 further comprising an error injection component capable of adding an error signal to the compensated digital signal.

33. A method for collecting real-time performance data from a digital power management component, the method comprising the steps of: providing a serial data transfer component capable of receiving/sending real-time data from/to a plurality of locations in the digital power management component;collecting, during operation of the digital power management component, real-time data from at least one location from the plurality of locations in the digital power management component; andproviding, to a controller component, the real-time data collected from the at least one location.

34. The method of claim 33 wherein the step of providing the real-time data comprises the step of synchronizing the controller component to the serial data transfer component utilizing a serial data transfer component clock source as a clock reference.

35. The method of claim 33 further comprising the step of: providing, through the controller component, real-time data to at least one other location from the plurality of locations in the digital power management component.

36. The method of claim 35 wherein the step of providing the real-time data comprises the step of synchronizing the controller component to the serial data transfer component utilizing a serial data transfer component clock source as a clock reference.

37. A system for collecting real-time performance data from a digital power management component, the system comprising: a serial data transfer component capable of receiving/sending real-time data from/to a plurality of locations in the digital power management component; anda controller component operatively connected to said sea of data transfer component, said controller comprising: at least one processor;at least one computer usable medium having computer readable code embodied there in, said computer readable code being capable of causing said at least one processor to: collect during operation of the digital power management component, real-time data from at least one location from said plurality of locations in the digital power management component.

38. The system of claim 37 wherein said computer readable code is also capable of causing said at least one processor to: provide real-time data to at least one other location from said plurality of locations in the digital power management component.

39. The system of claim 37 wherein said serial data transfer component comprises: a shift register; anda state sequencer capable of sequencing loading data into and out of the shift register.

40. The system of claim 39 wherein said state sequencer comprises: a clock terminal; anda data terminal;said state sequencer being capable of synchronizing said controller component to said serial data transfer component utilizing a serial data transfer component clock source as a clock reference.

41. The system of claim 39 wherein said state sequencer comprises: a clock terminal; anda data terminal;said state sequencer being capable of synchronizing said controller component to said serial data transfer component using an internal clock as a clock reference.

42. The digital controller of claim 1 further comprising: a serial data transfer component capable of receiving/sending real-time data from/to a plurality of locations in the digital controller; anda data controller component comprising: at least one processor;at least one computer usable medium having computer readable code embodied there in, said computer readable code being capable of causing said at least one processor to: collect, during operation of the digital controller, real-time data from at least one location from said plurality of locations in the digital controller.

43. The system of claim 42 wherein said computer readable code is also capable of causing said at least one processor to: provide real-time data to at least one other location from said plurality of locations in the digital power management component.

44. The system of claim 42 wherein said serial data transfer component comprises: a shift register; anda state sequencer capable of sequencing loading data into and out of the shift register.

45. The system of claim 42 wherein said state sequencer comprises: a clock terminal; anda data terminal;said state sequencer being capable of synchronizing said controller component to said serial data transfer component utilizing a serial data transfer component clock source as a clock reference.

46. The system of claim 42 wherein said state sequencer comprises: a clock terminal; anda data terminal;said state sequencer being capable of synchronizing said controller component to said serial data transfer component using an internal clock as a clock reference.

47. A method for digital control, the method comprising the steps of: oversampling an analog signal;filtering the oversampled signal with a compensating filter; andlow pass filtering and decimating the oversampled signal after filtering with the compensating filter, the decimating resulting in a decimated signal.

48. The method of claim 47 further comprising the step of: filtering, after decimating, the decimated signal with another compensating filter.

49. An analog to digital converter (ADC) comprising: a modulating component comprising; a low resolution analog to digital converting componenta variable gain component capable of receiving an output of said low-resolution analog to digital converting component and of providing a variable gain component output substantially equal to a variable multiplying factor times the output of said low-resolution analog-to-digital converting component; said variable gain component being also capable of receiving a gain setting signal and of modifying said variable multiplying factor in response to said gain setting signal; said variable gain component output being the oversampled signal;a discrete integrator receiving the variable gain component output; anda high. resolution digital to analog converting system; said high-resolution digital to analog converting system receiving an output of said discrete integrator;said low-resolution analog-to-digital converting system receiving a signal comprising a difference between the analog signal and an output of said high-resolution digital to analog converting system.

50. The ADC of claim 49 further comprising a decimator.