Systems and methods for digital signal synthesis with variable sample rate DAC

Abstract

Systems and methods for digital signal synthesis with variable sample rate digital-to-analog converters (DACs) in accordance with various embodiments of the invention are described. One embodiment includes a digital frequency generator that includes a direct digital frequency synthesizer (DDFS); a digital-to-analog converter (DAC); a frequency/phase estimation circuit; a stable reference clock (REF CLK); a variable frequency sample clock; a frequency control word (FCW); where the DAC is sampled by the variable frequency sample clock; where the DDFS is clocked by the variable frequency sample clock; where the frequency/phase estimation circuit receives as inputs the stable REF CLK and the variable frequency sample clock and estimates a FCW frequency error and adjusts the FCW to the DDFS; where the DDFS receives the FCW and outputs a digital sine codeword at the variable frequency sample clock to the DAC, where the FCW to the DDFS is continuously adjusted to track the variable frequency sample clock.

Description

FIELD OF THE INVENTION

The present invention relates to digital signal synthesis with variable sample rate digital-to-analog converters (DACs).

BACKGROUND

Modern electronic systems process and store information digitally. However, due to the analog nature of the world, conversions between analog and digital domains are needed and performed by data converters. Digital-to-analog converters (DACs) can be used to convert digital codewords into analog signals (e.g., voltage, current, among others).

SUMMARY OF THE INVENTION

Systems and methods in accordance with embodiments of the invention provide for digital signal synthesis using variable sample rate DACs. One embodiment includes a digital frequency generator that includes: a direct digital frequency synthesizer (DDFS); a digital-to-analog converter (DAC); a frequency/phase estimation circuit; a stable reference clock (REF CLK); a variable frequency sample clock; a frequency control word (FCW); where the DAC is sampled by the variable frequency sample clock; where the DDFS is clocked by the variable frequency sample clock; where the frequency/phase estimation circuit receives as inputs the stable REF CLK and the variable frequency sample clock and estimates a FCW frequency error and adjusts the FCW to the DDFS; where the DDFS receives the FCW and outputs a digital sine codeword at the variable frequency sample clock to the DAC, where the FCW to the DDFS is continuously adjusted to track the variable frequency sample clock; and where the DAC converts the sine codeword to an analog waveform.

In a further embodiment, the variable frequency sample clock is at least one variable frequency sample clock selected from the group consisting of a frequency ramp generator, a pseudo random (PN) modulated frequency source, and a frequency modulation source.

In a further embodiment again, the frequency/phase estimation circuit estimates a frequency error by comparing edges of the REF CLK and the variable frequency sample clock, where the frequency error is filtered with a loop filter to generate the FCW for the DDFS.

In yet a further embodiment, the FCW is a ratio of a desired frequency (fc) and the variable frequency sample clock (fs_j) wherein j denotes an index of the sample frequency.

An embodiment includes a broadband modulator including: a stable symbol clock (CLK); a variable frequency sample clock; an OFDM modulator circuit that operates at the stable symbol CLK to generate OFDM symbols; a frequency/phase estimation circuit that receives as inputs the stable symbol CLK and the variable frequency sample clock and estimates a frequency error and a phase error; a variable interpolator/decimator (VID) circuit that uses the frequency error and the phase error to generate a codeword; a digital-to-analog converter (DAC) that receives the codeword from the VID and generates an analog output.

In a further embodiment, the analog output is filtered by a filter to provide a filtered analog output.

In a further embodiment, the VID circuit converts a modulated signal from the stable symbol CLK domain to the variable frequency sample clock domain, where the VID circuit generates a corrected codeword that is provided to the DAC.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates DAC outputs in accordance with an embodiment of the invention.

FIG. 2 illustrates an architecture for digital frequency generation in accordance with an embodiment of the invention.

FIG. 3 illustrates NRZ DAC output spectrum in accordance with an embodiment of the invention.

FIG. 4 illustrate a frequency spectrum filtered output in accordance with an embodiment of the invention.

FIG. 5 illustrates a digital frequency generation architecture with DAC nonlinearity in accordance with an embodiment of the invention.

FIG. 6 illustrates an NRZ DAC output spectrum with IM products in accordance with an embodiment of the invention.

FIG. 7 illustrates a spectrum of a filtered output with IM products in accordance with an embodiment of the invention.

FIG. 8 illustrates an NRZ DAC output spectrum with two sample frequencies in accordance with an embodiment of the invention.

FIG. 9 illustrates an NRZ DAC output spectrum with IM products with variable sample frequency in accordance with an embodiment of the invention.

FIG. 10 illustrates an architecture for digital frequency synthesis with variable sample rate DAC in accordance with an embodiment of the invention.

FIG. 11 illustrates an architecture for frequency/phase estimation in accordance with an embodiment of the invention.

FIG. 12 illustrates a process for digital frequency synthesis with a variable sample rate DAC in accordance with an embodiment of the invention.

FIG. 13 illustrates a digital broadband modulator with a variable sample rate DAC in accordance with an embodiment of the invention.

FIG. 14 illustrates a process for a broadband modulator with a variable sample rate DAC in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

Turning now to the drawings, systems and methods for digital signal synthesis with variable sample rate digital-to-analog converters (DACs) in accordance with various embodiments of the invention are illustrated. Systems in accordance with many embodiments can provide for digital frequency synthesis using a variable sample rate DAC. In many embodiments, a DAC can be sampled by a variable frequency source. In many embodiments, a variable frequency source can be a frequency ramp generator, pseudo random (PN) modulated frequency source, and/or frequency modulation source among others. In many embodiments, a direct digital frequency synthesizer (DDFS) can also be clocked by the same variable frequency source. In many embodiments, given that a sample frequency can be variable, a frequency control word (FCW) to the DDFS may be adjusted continuously to track the variable sample frequency. A frequency/phase estimation circuit can be used to estimate FCW frequency error. The frequency/phase estimation circuit can take both a stable reference clock and a variable sample clock as inputs. Described now are details regarding DAC operation in accordance with several embodiments of the invention.

DAC Operation

A DAC can be a device that converts a fine-precision digital-format number (typically a finite-length binary format number) to an analog electrical quantity (such a voltage, current and/or electric charge). Two basic types of DAC output formats can be used to construct an analog signal, including non-return-to-zero (NRZ) and return-to-zero (RZ). FIG. 1 illustrates DAC outputs for different types of DACs, including a DAC analog output for NRZ, a DAC analog output for RZ, and a filtered DAC output. As illustrated in FIG. 1, for NRZ, the DAC can update its analog output according to a digital input at a fixed time interval of Ts and the DAC can hold the output, where Ts can be referred to as an updating and sampling period. For an RZ type DAC, after updating the output at each time interval Ts, the DAC can hold the output for a certain time (Th), which can then go back to zero. In both types of DACs, a DAC's output can be held for a certain time Th, where 0<Th<=Ts, known as zero-order-hold. An output of a DAC is typically a stepwise or pulsed analog signal and can be low pass filtered to construct the desired analog signal.

DAC Output Spectrum

An architecture of a digital frequency generator using direct digital frequency synthesis (DDFS) and a DAC in accordance with an embodiment of the invention is illustrated in FIG. 2. The DDFS input can be a frequency control word (e.g., FCW=fc/fs) which can be a ratio of a desired frequency (fc) and a sample frequency (fs). The DDFS can output a digital sine codeword at the sample rate (fs). The DAC can convert the sine codeword into an analog waveform.

A raw DAC output (e.g., NRZ and RZ) can have many harmonics other than a desired output frequency. FIG. 3 illustrates an NRZ DAC output spectrum of a single tone with frequency fc with sample frequency at fs. In addition to the desired frequency (fc and −fc), there can also be harmonic frequencies at equation (1) below:n*fs+fc and n*fs−fc where n is an integer from −∞ to ∞  (1)

These harmonics may be away from a desired frequency fc if fs is chosen properly (e.g., fc has been less than fs/2). In many embodiments, a low pass filter can be used to suppress harmonics. FIG. 4 illustrates using a low pass filter so suppress harmonics to a desired level in accordance with an embodiment of the invention.

In many embodiments, if there is a non-linear device (e.g., an amplifier and/or driver) before the low pass filter (as shown in FIG. 5 in accordance with an embodiment), intermodulation (IM) products of these harmonics can show up in-band of fc and they may no longer be filtered out. An example of a spectrum with nonlinearity added to a DAC output in accordance with an embodiment of the invention is illustrated in FIG. 6. A spectrum of a filtered output and the in-band IM products at the filtered output in accordance with an embodiment of the invention is illustrated in FIG. 7. In many embodiments, un-filtered IM products can add noise to a system and degrade the system performance.

IM Product Suppression with Variable Sample Frequency

Systems in accordance with many embodiments can, instead of using a fixed sample frequency fs, use multiple sample frequencies fsj, where j denotes an index of the sample frequency. In many embodiments, a digital frequency control word (FCW) can be adjusted according to the sample frequency fsj, and thus a DAC output can still have a desired frequency. Accordingly, harmonics can be spread into multiple frequency components with lower power.

For example, a desired output frequency is 1000 Hz and 2 sample frequencies 5000 and 5050 can be used. For fs=5000 Hz, FCW=1000/5000=0.2 can be used and the image frequency is at 4000 Hz. For fs=5050 Hz, FCW=1000/5050=0.198 can be used and the image frequency is at 4050 Hz.

An example DAC output spectrum with 2 sample frequencies in accordance with an embodiment of the invention is illustrated in FIG. 8. As illustrated in FIG. 8, harmonics can be split into two components and their powers can be lowered by a certain amount (e.g., by 3 dB). In many embodiments, if N sample frequencies are used, a harmonic power can be lowered by 10*log 10 (N). If the sample frequency varies over a frequency band with bandwidth BW, the harmonic power in dBc/Hz can be lowered by 10*log 10 (BW).

With lower harmonic power, IM products of these harmonics can be lowered with a same non-linear device. An example of variable sampled DAC output spectrum with IM products added in accordance with an embodiment of the invention is illustrated in FIG. 9. As illustrated in FIG. 9, IM products can spread over a wide frequency range and in-band SNR can be improved.

Digital Frequency Synthesis Architectures with Variable Sample Rate DACs

A circuit architecture for digital frequency synthesis with a variable sample rate DAC in accordance with an embodiment of the invention is illustrated in FIG. 10. The DAC 1020 can be sampled by a variable frequency source 1010. In many embodiments, a variable frequency source can be a frequency ramp generator, pseudo random (PN) modulated frequency source, and/or frequency modulation source among others. In many embodiments, DDFS 1015 can also be clocked by the same variable frequency source 1010. Given the sample frequency is variable, FCW 1006 to the DDFS 1015 may need to be adjusted continuously to track the variable sample frequency. A frequency/phase estimation circuit 1005 can be used to estimate FCW frequency error. The frequency/phase estimation circuit 1005 can take both a stable reference clock 1001 and the variable sample clock 1010 as inputs. Although FIG. 10 illustrates a particular circuit architecture for digital frequency synthesis with a variable sample rate DAC, any of a variety of architectures can be utilized as appropriate to the requirements of specific applications in accordance with embodiments of the invention.

A frequency/phase estimation circuit architecture in accordance with an embodiment of the invention is illustrated in FIG. 11. As illustrated in FIG. 11, the phase error can be estimated by comparing edges of a reference clock and a sample clock. This phase error can be filtered with a loop filter to generate a final FCW for a DDFS. Although FIG. 11 illustrates a particular circuit architecture of a frequency/phase estimation circuit, any of a variety of architectures can be utilized as appropriate to the requirements of specific applications in accordance with embodiments of the invention.

A process for frequency generation in accordance with an embodiment of the invention is illustrated FIG. 12. The process 1200 compares (at 1205), using a frequency/phase estimation circuit, a stable reference clock and a variable sample clock to estimate a frequency error. The process adjusts (at 1210) a frequency control word (FCW) value going to a DDFS circuit. The process generates (at 1215) a final codeword for a DAC using a DDFS circuit that takes in the corrected FCW to generate the final codeword for the DAC. The process completes. Although FIG. 12 illustrates a particular process for frequency generation using a frequency/phase estimation circuit to generate a corrected FCW, any of a variety of processes can be utilized as appropriate to the requirements of specific applications in accordance with embodiments of the invention.

Digital Broadband Modulator Architectures with Variable Sample Rate DACs

Variable sample rate DAC architectures in accordance with many embodiments may not be limited to a single frequency generation. Systems in accordance with many embodiments can be used for broad-band signal generation. A circuit architecture of a broadband modulator (OFDM modulator) with a variable sample rate DAC in accordance with an embodiment of the invention is illustrated in FIG. 13. As illustrated, an OFDM modulator 1305 that can operate at a stable symbol CLK can be used to generated OFDM symbols. A frequency/phase estimation circuit 1330 can be used to estimate the frequency and phase error with symbol CLK and variable frequency sample clock. A variable-interpolator-decimator (VID) circuit can be used to convert OFDM symbols from OFDM symbol CLK domain to variable sample clock domain 1340. A variable interpolator/decimator (VID) circuit can use a frequency error and a phase error from the frequency/phase estimation circuit 1330 for the signal processing. A DAC 1315 can receive the signal from the VID and generate an output 1320, which can be filtered by a filter 1325 to provide a filtered output. Although FIG. 13 illustrates a particular variable sample rate DAC architecture, any of a variety of architectures can be utilized as appropriate to the requirements of specific applications in accordance with embodiments of the invention.

A process for broad-band signal generation in accordance with an embodiment of the invention is illustrated in FIG. 14. The process 1400 generates (at 1401) a modulated signal on a stable REF CLK using a broadband modulator circuit. In many embodiments, a broadband modulator circuit can receive a REF CLK, a sync signal, and at least one MOD parameter and the circuit can output MOD symbols. The process compares (at 1405), using a frequency/phase estimation circuit, REF CLK and a variable frequency sample clock to generate a frequency error and a phase error. The process converts (at 1415), using a VID processing circuit, the modulated signal from REF CLK domain to a variable frequency sample clock domain. The process generates, using the VID processing circuit, a corrected codeword that is provided to a DAC. The process completes. Although FIG. 14 illustrates a particular process for broad-band signal generation, any of a variety of processes can be utilized as appropriate to the requirements of specific applications in accordance with embodiments of the invention.

Mathematical Operations

A DAC operation can be modeled by 3 mathematical operations:

1) Normalized frequency scaling. A digital normalized frequency can be scaled by the actual DAC sample frequency to generate the output frequency.

2) Frequency multiplication with multiple tones. The band-limited digital signal can be mixed by multiple tones that are integer multiply of the sample frequency.

3) The broad-band signal can be convolved with a rectangular pulse. For NRZ DAC, the rectangular pulse width can be the same as the sample period. For RZ DAC, the rectangular pulse width can be less than the sample period. For both cases, this convolution can be the same as low pass filtering by a sinc( ) function in frequency domain. The frequency response of the low-pass filter can be determined by the pulse width and the sample frequency.

Given a digital signal x(n)=sin(2π·0.1*n), n=1, 2, . . . and a DAC sampled at 100 MHz can be used to convert this digital signal into analog. The output analog signal has frequencies f_op (0.1*100=10 MHZ) and f_on (−0.1*100=−10 MHZ) and their frequency multiplication products with integer multiples of the sample frequency 100 MHz.f_op(k)=k*100+10 MHZ, k=−∞, . . . ,−1,0,1, . . . ,∞f_on(k)=k*100−10 MHz, k=−∞, . . . ,−1,0,1, . . . ,∞

Each frequency component is weighted by the sinc( ) filter and the filter weight h(f) is given as follows:

$h\left(f\right)=\frac{1}{T_s}\sin c\left(f*T_p\right)$

T_p is the pulse width. For NRZ DAC, T_p=T_s. For RZ DAC, T_p<T_s.

Given a digital signal with normalized frequency component at f_nc and a DAC with sample frequency at f_s, the DAC output can include many frequencies f_op (k) and f_cn(k)f_cp(k)=k*f_s+f_nc*f_s,k=−∞, . . . ,−1,0,1, . . . ,∞f_cn(k)=k*f_s−f_nc*f_s,k=−∞, . . . ,−1,0,1, . . . ,∞

Each frequency component is weighted by w_cp(k) and w_cn(k)

$w_{cp}\left(k\right)=\frac{1}{T_s}\sin c\left(f_{cp}\left(k\right)*T_p\right)$ $w_{cn}\left(k\right)=\frac{1}{T_s}\sin c\left(f_{cn}\left(k\right)*T_p\right)$

For an ideal DAC with perfect linearity and f_nc<0.5, it can be shown that frequency components within {−f_s/2, f_s/2} are f_cp(0) and f_cn(0). A low-pass filter with pass band {−f_s/2, f_s/2} can filter out all other frequencies. The filtered output is a sinewave with frequency at f_nc*f_s.

However, if there is non-linearity in the DAC, intermodulation (IM) products would show up at the DAC output and these IM products can fall within

$\left\{-\frac{f_s}{2},\frac{f_s}{2}\right\}$ band. These in-band IM products cannot be filtered out by the low-pass filter. They become spurs and degrade quality of the generated signal. The general expression of IM products of p-th order (k-th frequency) and q-th order (l-th frequency) is as follows:[f_cp(k)]^p*[f_cp(l)]^q=(k*p+l*q)f_s+(p+q)(f_nc*f_s)[f_cn(k)]^p*[f_cn(l)]^q=(k*p+l*q)f_s−(p+q)(f_nc*f_s)[f_cp(k)]^p*[f_cn(l)]^q=(k*p+l*q)f_s+(p−q)(f_nc*f_s)

Their associated weights are:α(p,q)*[w_cp(k)]^p*[w_cp(l)]^q α(p,q)*[w_cp(k)]^p*[w_cn(l)]^q α(p,q)*[w_cn(k)]^p*[w_cn(l)]^q

• • α(p, q) is a function associated with the DAC non-linearity.

Any IM products with non-zero (k*p+l*q) term may not be desirable since they can be spur right next to the desired frequency. On the other hand, IM products with (k*p+l*q)=0 is an integer harmonic of the desired frequency and the frequency spacing is at least (f_nc*f_s).

Given a digital signal with f_nc=0.199 and f_s=100 MHZ, the desired frequency is 19.9 MHz. With k=1, p=3, l=−2, and q=1, IM products [f_cn(k)]^p*[f_cn(l)]^q has output frequency at 20.4 MHz which is 0.4 MHz away from the desired frequency. This close-in spur may not be desirable and should be reduced as much as possible to improve signal quality. In many embodiments, a way to suppress this spur can be to improve the DAC linearity which means more power and area. In certain embodiments, another way can be to sample the DAC with variable sample frequency f_s(t). f_s(t) can be a random variable that takes value between {f_{s_min}, f_{s_max}}. If the difference between f_{s_min} and f_{s_max} is small compared to

$f_{s\_min}\left(\frac{f_{s\_m\mathrm{ax}}-f_{s\_min}}{f_{s\_min}}\ll 1\right),$ can the above DAC analysis can extend from fixed frequency sampling to variable frequency sampling.

Given a digital signal with normalized frequency component at f_nc (t) and a DAC with variable sample frequency at f_s(t), f_nc (t) tracks the change of f_s(t) such that f_nc (t)*f_s(t)=fc. The DAC output can include many frequencies f_cp(k, t) and f_cn(k, t)f_cp(k,t)=k*f_s(t)+f_c,k=−∞, . . . ,−1,0,1, . . . ,∞f_cn(k,t)=k*f_s(t)−f_c,k=−∞, . . . ,−1,0,1, . . . ,∞

Each frequency component is weighted by w_cp(k, t) and w_cn(k, t)

$w_{cp}\left(k,t\right)=\frac{1}{T_s}\sin c\left(f_{cp}\left(k,t\right)*T_p\left(t\right)\right)$ $w_{cn}\left(k,t\right)=\frac{1}{T_s}\sin c\left(f_{cn}\left(k,t\right)*T_p\left(t\right)\right)$

Added non-linearity, IM products of p-th order (k-th frequency) and q-th order (l-th frequency) is as follows:[f_cp(k,t)]^p*[f_cp(l,t)]^q=(k*p+l*q)f_s(t)+(p+q)f_c [f_cn(k,t)]^p*[f_cn(l,t)]^q=(k*p+l*q)f_s(t)−(p+q)f_c [f_cp(k,t)]^p*[f_cn(l,t)]^q=(k*p+l*q)f_s(t)+(p−q)f_c

Their associated weights are:α(p,q)*[w_cp(k,t)]^p+[w_cp(l,t)]^q α(p,q)*[w_cp(k,t)]^p+[w_cn(l,t)]^q α(p,q)*[w_cn(k,t)]^p*[w_cn(l,t)]^q

Note that any IM products with non-zero (k*p+l*q) term is no longer a single tone. Its frequency spreads over a wide range depending on {f_{s_min}, f_{s_max}}, k, p, l, and q.

To generate a frequency with 19.9 MHz with a variable sample frequency f_s(t) and {f_{s_min}=99.9 MHZ, f_{s_max}=100.1 MHz}, the normalized frequency f_nc (t) should be between 0.1988 and 0.1992 tracking f_s(t). With k=1, p=3, l=−2, and q=1, IM products [f_cn(k)]^p*[f_cn(l)]^q has output frequencies range from 19.9 to 20.9 MHz. Since the IM product is spread over a wide range (1 MHZ), each individual tone in the frequency range is reduced (1/1,000,000 in this case).

While the above descriptions and associated figures have digital signal synthesis with variable sample rate digital-to-analog converters, it should be clear that any of a variety of configurations for digital signal synthesis with variable sample rate digital-to-analog converters can be implemented in accordance with embodiments of the invention. More generally, although the present invention has been described in certain specific aspects, many additional modifications and variations would be apparent to those skilled in the art. It is therefore to be understood that the present invention may be practiced otherwise than specifically described. Thus, embodiments of the present invention should be considered in all respects as illustrative and not restrictive.

Claims

1. A digital frequency generator comprising: a direct digital frequency synthesizer (DDFS);a digital-to-analog converter (DAC);a frequency/phase estimation circuit;a stable reference clock (REF CLK);a variable frequency sample clock; anda frequency control word (FCW);wherein the DAC is sampled by the variable frequency sample clock;wherein the DDFS is clocked by the variable frequency sample clock;wherein the frequency/phase estimation circuit receives as inputs the stable REF CLK and the variable frequency sample clock and estimates a FCW frequency error and adjusts the FCW to the DDFS;wherein the DDFS receives the FCW and outputs a digital sine codeword at the variable frequency sample clock to the DAC, wherein the FCW to the DDFS is continuously adjusted to track the variable frequency sample clock; andwherein the DAC converts the digital sine codeword to an analog waveform.

2. The digital frequency generator of claim 1, wherein the variable frequency sample clock is at least one variable frequency sample clock selected from the group consisting of a frequency ramp generator, a pseudo random (PN) modulated frequency source, and a frequency modulation source.

3. The digital frequency generator of claim 1, wherein the frequency/phase estimation circuit estimates a frequency error by comparing edges of the REF CLK and the variable frequency sample clock, wherein the frequency error is filtered with a loop filter to generate the FCW for the DDFS.

4. The digital frequency generator of claim 1, wherein the FCW is a ratio of a desired frequency (fc) and the variable frequency sample clock (fsj) wherein j denotes an index of the sample frequency.

5. A broadband modulator comprising: a stable symbol clock (CLK);a variable frequency sample clock;an OFDM modulator circuit that operates at the stable symbol CLK to generate OFDM symbols;a frequency/phase estimation circuit that receives as inputs the stable symbol CLK and the variable frequency sample clock and estimates a frequency error and a phase error;a variable interpolator/decimator (VID) circuit that uses the frequency error and the phase error to generate a codeword; anda digital-to-analog converter (DAC) that receives the codeword from the VID and generates an analog output.

6. The broadband modulator of claim 5, wherein the analog output is filtered by a filter to provide a filtered analog output.

7. The broadband modulator of claim 5, wherein the VID circuit converts a modulated signal from the stable symbol CLK domain to the variable frequency sample clock domain, wherein the VID circuit generates a corrected codeword that is provided to the DAC.