Systems and methods for efficient data shuffling in a data processing system

Abstract

Various embodiments of the present invention provide systems and methods for data processing. Such data processing includes data shuffling.

Description

BACKGROUND OF THE INVENTION

The present inventions are related to systems and methods for decoding information, and more particularly to systems and methods for data processing that includes data shuffling.

Various data transfer systems have been developed including storage systems, cellular telephone systems, and radio transmission systems. In each of the systems data is transferred from a sender to a receiver via some medium. For example, in a storage system, data is sent from a sender (i.e., a write function) to a receiver (i.e., a read function) via a storage medium. The effectiveness of any transfer is impacted by any losses in data caused by various factors. In some cases, an encoding/decoding process is used to enhance the ability to detect a data error and to correct such data errors. As an example, a simple data detection and decode may be performed, however, such a simple process often lacks the capability to converge on a corrected data stream. To increase the possibility of convergence, various existing processes utilize two or more detection and decode iterations. Further data may be shuffled to limit the impact of burst errors on an ability to converge on the proper data set. In many cases, the aforementioned systems are inefficient.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for data processing.

BRIEF SUMMARY OF THE INVENTION

The present inventions are related to systems and methods for decoding information, and more particularly to systems and methods for data processing that includes data shuffling.

Various embodiments of the present invention provide methods for data processing that include: receiving a data input having at least a first local chunk and a second local chunk, the data input also being defined as having at least a first global chunk and a second global chunk; rearranging an order of the first local chunk and the second local chunk to yield a locally interleaved data set; storing the locally interleaved data set to a first memory, such that the first global chunk is stored to a first memory space, and the second global chunk is stored to a second memory space; accessing the locally interleaved data set from the first memory; and storing the locally interleaved data set to a second memory. The first global chunk is stored to a third memory space defined at least in part based on the first memory space, and the second global chunk is stored to a fourth memory space defined at least in part based on the second memory space.

In some instances of the aforementioned embodiments, the first memory space is a first column and a first row, and the second memory space is a second column and the first row. In some such instances, the first row is a randomly selected row. In various of such instances, the third memory space is a third column and a second row, and the fourth memory space is a fourth column and a third row. In some such instances, the second row is randomly selected, and the third row is randomly selected. In other such instances, the third column is selected based at least in part on the first column, and the fourth column is selected based at least in part on the second column. In yet other such instances, the third column is the same as the first column, and the fourth column is the same as the second column.

In one or more instances of the aforementioned embodiments, the methods further include: applying a data detection algorithm to a data set to yield the data input; accessing a globally interleaved data set from a fifth memory space in the second memory; and applying a data decode algorithm to the globally interleaved data set. In some such instances, the third memory space is a third column and a second row, the fourth memory space is a fourth column and a third row, and the first memory space is the second row including at least the first global chunk. In various such instances, the data detection algorithm may be, but is not limited to, a maximum a posteriori data detection algorithm, or a Viterbi algorithm data detection algorithm. In some cases, the data decode algorithm is a low density parity check algorithm.

Other embodiments of the present invention provide data processing systems that include: a local interleaver circuit and a column controlled interleaver circuit. The local interleaver circuit is operable to: receive a data input that includes at least a first local chunk and a second local chunk, rearrange an order of the first local chunk and the second local chunk to yield a locally interleaved data set, and write the locally interleaved data set to a first row of a first memory. The locally interleaved data set includes at least a first global chunk stored to a first column of the first memory, and a second global chunk stored to a second column of the first memory. The column controlled interleaver circuit is operable to: access the locally interleaved data set from the first row of the first memory, store the first global chunk to the first column and a second row of a second memory, store the second global chunk to the second column and a third row of the second memory.

In some instances of the aforementioned embodiments, the data processing system is implemented as, but is not limited to, a storage device or a receiving device. In various instances of the aforementioned embodiments, the data processing system is implemented as part of an integrated circuit. In one or more instances of the aforementioned embodiments, the first row of the first memory is randomly selected, the second row of the second memory is randomly selected, and the third row of the second memory is randomly selected. In various instances of the aforementioned embodiments, the first column of the second memory is selected to correspond to the first column of the first memory, and the second column of the second memory is selected to correspond to the second column of the first memory. In some instances of the aforementioned embodiments, the system further includes: a data detector circuit and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield the data input. The data decoder circuit is operable to apply a data decode algorithm to a globally interleaved data set generated by accessing the second row of the second memory including the first global chunk.

This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several figures to refer to similar components. In some instances, a sub-label consisting of a lower case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components.

FIG. 1 shows a data processing circuit including an efficient interleaving/de-interleaving circuit in accordance with one or more embodiments of the present invention;

FIG. 2 shows an example of a detected output that is locally interleaved (i.e., shuffled) to yield an locally interleaved codeword;

FIGS. 3 a and 3b show an example of a two step global interleaving process in accordance with some embodiments of the present invention;

FIG. 4 is a flow diagram showing a method for efficient global interleaving in a data processing circuit in accordance with various embodiments of the present invention;

FIG. 5 shows a data transmission system including a receiver having efficient interleaving circuitry in accordance with some embodiments of the present invention; and

FIG. 6 shows a storage device including a read channel having efficient interleaving circuitry in accordance with one or more embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present inventions are related to systems and methods for decoding information, and more particularly to systems and methods for data processing that includes data shuffling.

Various embodiments of the present invention provide for shuffling data between operations of a data detector circuit and a data decoder circuit. The shuffling process, also referred to herein as “interleaving”, includes both a local interleaving and a global interleaving. As used herein, the phrase “local interleaving” or “local shuffling” is used in its broadest sense to mean rearranging data within a defined codeword. Also, as used herein, the phrase “global interleaving” or “global shuffling” is used in its broadest sense to mean rearranging data across multiple codewords. As used herein, the terms “de-interleaving” and “de-shuffling” are used in their broadest sense to mean reversing the process of interleaving and shuffling. In some of the embodiments discussed herein, a combination of local interleaving and global interleaving are to minimize the effects of burst errors in a given codeword upon the data decoding process. A two step global interleaving and corresponding de-interleaving are used that reduce the amount of circuitry needed when compared with a single step global interleaving.

Turning to FIG. 1, a data processing circuit 100 including an efficient interleaving/de-interleaving circuit 140 is shown in accordance with one or more embodiments of the present invention. Efficient interleaving/de-interleaving circuit 140 implements both local interleaving and global interleaving with the global interleaving being performed as a two step process implemented by a local interleaver circuit 142 and a column controlled interleaver/de-interleaver circuit 160. Data processing circuit 100 includes an analog front end circuit 110 that receives an analog signal 105. Analog front end circuit 110 processes analog signal 105 and provides a processed analog signal 112 to an analog to digital converter circuit 114. Analog front end circuit 110 may include, but is not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog front end circuit 110. In some cases, analog signal 105 is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium (not shown). In other cases, analog signal 105 is derived from a receiver circuit (not shown) that is operable to receive a signal from a transmission medium (not shown). The transmission medium may be wired or wireless. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of source from which analog input 105 may be derived.

Analog to digital converter circuit 114 converts processed analog signal 112 into a corresponding series of digital samples 116. Analog to digital converter circuit 114 may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. Digital samples 116 are provided to an equalizer circuit 120. Equalizer circuit 120 applies an equalization algorithm to digital samples 116 to yield an equalized output 125. In some embodiments of the present invention, equalizer circuit 120 is a digital finite impulse response filter circuit as are known in the art. In some cases, equalizer 120 includes sufficient memory to maintain one or more codewords until a data detector circuit 130 is available for processing.

Equalized output 125 is provided to detector circuit 130 that is operable to apply a data detection algorithm to a received codeword, and in some cases can process two or more codewords in parallel. In some embodiments of the present invention, data detector circuit is a Viterbi algorithm data detector circuit as are known in the art. In other embodiments of the present invention, data detector circuit 130 is a maximum a posteriori data detector circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detector circuits that may be used in relation to different embodiments of the present invention. Data detector circuit 130 is started based upon availability of a codeword from either equalizer 120 or efficient interleaving/de-interleaving circuit 140.

Data detector circuit 130 applies the data detection algorithm to either a codeword received as equalized output 125 or to a codeword received as de-interleaved output 197 from efficient interleaving/de-interleaving circuit 140. The result of applying the data detection algorithm is a detected output 195 that is provided to efficient interleaving/de-interleaving circuit 140. When a detected output 195 is ready, it is stored to a central memory circuit 150 where it awaits processing by a data decoder circuit 170. In some cases, detected output 195 is log likelihood ratio data. Before being stored to central memory circuit 150, detected output 195 is processed through local interleaver circuit 142 that shuffles sub-portions (i.e., local chunks) of the codeword included as detected output 195 and provides an interleaved codeword 146 that is stored to central memory circuit 150. FIG. 2 shows an example of a detected output 195 and a corresponding interleaved codeword 146. As shown, the chunks (referred to herein more specifically as local chunks) in detected output 195 are in a first order. It should be noted that a given codeword represented by detected output 195 may be broken into smaller or larger local chunks.

Subsequent to processing by local interleaver circuit 142, the local chunks are placed in a different order. This rearranging increases the randomness and thereby mitigates the effect of any burst errors. In prior art systems, the write operation of interleaved codeword 146 to central memory circuit 150 involved writing one interleaved codeword 146 after another is done on a row by row basis into central memory circuit 150, and the global interleaving is done when the data is transferred out of central memory circuit 150. In contrast, in efficient interleaving/de-interleaving circuit 140, when writing interleaved codeword 146 to central memory circuit 150, each instance of interleaved codeword 146 is written to a random row location in central memory circuit 150. The random row mapping may be done based upon a random number generator limited to row numbers in central memory circuit 150 that are known to be available. In this way, a random row write does not overwrite needed data, but is rather limited to vacated row locations. In some cases, the row mapping function is programmed to a look up table (not shown). This is the first of a two step global interleaving process. FIG. 3a depicts an example of writing a number of instances of interleaved codeword 146 to a portion 305 of central memory circuit 150. As shown, the row into which a given interleaved codeword is written is random.

A ping/pong memory circuit 165 is used to pull a global interleaved data set 162 from central memory circuit 150 for data decoder circuit 170 by way of column controlled interleaver/de-interleaver circuit 160. Once data decoder circuit 170 is available, a global interleaved codeword 167 is pulled form ping/pong memory circuit 165 and data decoder circuit 170 applies a data decode algorithm to the received codeword. In some embodiments of the present invention, the data decode algorithm is a low density parity check algorithm as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other decode algorithms that may be used in relation to different embodiments of the present invention. As the data decode algorithm completes on a given codeword, the completed codeword is written back as a decoded output 169 to ping/pong memory circuit 165. Once the write back is complete to ping/pong memory circuit 165, a corresponding codeword 164 is transferred to central memory circuit 150 by way of column controlled interleaver/de-interleaver circuit 160.

When a codeword is transferred from central memory circuit 150 as a partially globally interleaved codeword 152, column controlled interleaver/de-interleaver circuit 160 again modifies the row into which a given global chunk is placed. A global chunk may be the same size as the local chunks, while in other cases the global chunks may be different in size from the local chunks. Of note, when transferring data from central memory circuit 150 to ping/pong memory circuit 165, column controlled interleaver/de-interleaver circuit 160 changes the row into which a given global chunk is written, but maintains the column. The row into which a global chunk is placed may be randomly selected or selected based upon a mapping scheme. Thus, a global chunk is written to the same column in ping/pong memory circuit 165 that it was pulled from in central memory circuit 150. By maintaining the columns consistent between a location in ping/pong memory circuit 165, a layer of multiplexers may be eliminated yielding a more efficient global interleaving/de-interleaving with a corresponding reduction in power consumption compared with allowing a global interleaving/de-interleaving with randomly assigned columns. This process of modifying the rows while maintaining consistent column location is shown in FIG. 3b. In particular, FIG. 3b shows the distribution of global chunks across a portion 310 of ping/pong memory circuit 165. In this case, the global chunks are twice as large as two of the local chunks. Each row 321, 322, 323, 324, 325, 326, 327, 328 of portion 310 includes a number of global chunks (e.g., a combination of codeword 1, chunk f and chunk G) distributed across random rows, but maintaining the same column location as in portion 305 discussed above. This process of modifying the row location of global chunks from central memory circuit 150 while maintaining a consistent column location is the second step of the global interleaving process.

When codeword 164 is written from ping/pong memory circuit 165 to central memory circuit 150, column controlled interleaver/de-interleaver circuit 160 reverses the row modification originally applied when the data was originally written from central memory circuit 150 to ping/pong memory circuit 165. This reversal yields a partially globally interleaved codeword 154 that is written to central memory circuit 150. When data detector circuit 130 becomes free, a corresponding partially globally interleaved codeword 148 is provided to data detector circuit 130 as a de-interleaved codeword 197 by a local de-interleaver circuit 144. Local de-interleaver circuit 144 reverses the processes originally applied by local interleaver circuit 142. Once data detector circuit 130 completes application of the detection algorithm to de-interleaved codeword 197, the result is provided as detected output 195.

Where data decoder circuit 170 converges (i.e., results in the originally written data), the resulting decoded data is provided as a hard decision output 172 to a de-interleaver circuit 180. De-interleaver circuit 180 rearranges the data to reverse both the global and local interleaving applied to the data to yield a de-interleaved output 182. De-interleaved output 182 is provided to a hard decision output circuit 190. Hard decision output circuit 190 is operable to re-order codewords that may complete out of order back into their original order. The originally ordered codewords are then provided as a hard decision output 192.

Turning to FIG. 4, a flow diagram 400 shows a method for efficient global interleaving in a data processing circuit in accordance with various embodiments of the present invention. Following flow diagram 400, an analog input signal is received (block 405). The analog input may be derived from, for example, a storage medium or a data transmission channel. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources of the analog input. The analog input is converted to a series of digital samples (block 410). This conversion may be done using an analog to digital converter circuit or system as are known in the art. Of note, any circuit known in the art that is capable of converting an analog signal into a series of digital values representing the received analog signal may be used. The resulting digital samples are equalized to yield an equalized output (block 415). In some embodiments of the present invention, the equalization is done using a digital finite impulse response circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of equalizer circuits that may be used in place of such a digital finite impulse response circuit to perform equalization in accordance with different embodiments of the present invention.

It is determined whether a data detector circuit is available (block 420). Where a data detector circuit is available (block 420), a data detection algorithm is applied to the equalized output guided by a de-interleaved codeword where a such a de-interleaved codeword corresponding to the equalized output is available (i.e., the second and later iterations through the data detector circuit and the data decoder circuit). This process yields a detected output (block 425). In some embodiments of the present invention, data detection algorithm is a Viterbi algorithm as are known in the art. In other embodiments of the present invention, the data detection algorithm is a maximum a posteriori data detector circuit as are known in the art. Local chunks in the detected output are re-arranged or shuffled to yield a locally interleaved data set (block 430). FIG. 2 above shows an example of a detected output 195 and a corresponding locally interleaved codeword 146. As shown, the chunks (referred to herein more specifically as local chunks) in detected output 195 are in a first order, and the same chunks in the locally interleaved codeword are in a second order. It should be noted that a given codeword represented by detected output 195 may be broken into smaller or larger local chunks.

A row of a central memory is randomly selected (block 435), and the locally interleaved data set is stored to the selected row (block 440). The process of writing the locally interleaved data set to a randomly selected row of the central memory completes the first step of a two step global interleaving process. It is then determined whether a partially de-interleaved data set is available for use in the data detection process (block 445). Where a partially de-interleaved data set is available, block 445), the partially de-interleaved data set is accessed from the central memory (block 450) and the partially de-interleaved data set is de-interleaved to yield the de-interleaved data set for use in guiding the detection process (block 455). De-interleaving the partially de-interleaved data set is the reverse of the process described above in relation to FIG. 2.

In parallel to the previously discussed processing, it is determined whether a data decoder circuit is available (block 460). Where the data decoder circuit is available (block 460) a previously stored locally interleaved data set is accessed from the central memory (block 465). A first row in a second memory having an available column location corresponding to the column of a first global chunk of the locally interleaved codeword is selected, and a second row in the second memory having an available column location corresponding to the column of a second global chunk of the locally interleaved codeword is selected (block 470). The first chunk of the locally interleaved data set is written to the previously selected row and column in the second memory, and the second chunk of the locally interleaved data set is written to the previously selected row and column in the second memory (block 475). The process of writing the global chunks to the selected rows and columns of the second memory completes the second step of the two step global interleaving process. An example of this second step is shown in FIG. 3 discussed above. A data decode algorithm is applied to a globally interleaved codeword read as an entire row of the second memory (block 480). In some cases, the data decode algorithm is a low density parity check algorithm as are known in the art. It should be noted that while flow diagram 400 is described in relation to two global chunks, that it may be expanded to include three or more global chunks stored to selected rows with available columns that correspond to the column where the given global chunk is stored in the central memory.

It is determined whether the decode algorithm converged (i.e., the original data set is identified) (block 485). Where the data decode algorithm converged (block 485), the decoded output is provided as a data output (block 499). Otherwise, where the data decode algorithm failed to converge (block 485) the decoded output is partially de-interleaved (block 490). This partial de-interleaving includes reversing the processes discussed above in relation to FIG. 3. The resulting partially de-interleaved data set is stored to the central memory (block 495).

Turning to FIG. 5, a data transmission system 500 including a receiver 520 having efficient interleaving circuitry is shown in accordance with some embodiments of the present invention. Data transmission system 500 includes a transmitter 510 that is operable to transmit encoded information via a transfer medium 530 as is known in the art. The encoded data is received from transfer medium 530 by receiver 520. Receiver 520 incorporates multi-pattern noise predictive filter adaptation circuitry. While processing received data, received data is converted from an analog signal to a series of corresponding digital samples, and the digital samples are equalized to yield an equalized output. The equalized output is then provided to a data processing circuit including both a data detector circuit and a data decoder circuit. Data is passed between the data decoder and data detector circuit via an efficient interleaving/de-interleaving circuit. The efficient interleaving/de-interleaving circuit may be implemented similar to that discussed above in relation to FIG. 1, and/or may operate similar to that discussed in above in relation to FIG. 4.

Turning to FIG. 6, a storage system 600 including a read channel circuit 610 including efficient interleaving circuitry in accordance with one or more embodiments of the present invention. Storage system 600 may be, for example, a hard disk drive. Storage system 600 also includes a preamplifier 670, an interface controller 620, a hard disk controller 666, a motor controller 668, a spindle motor 672, a disk platter 678, and a read/write head assembly 676. Interface controller 620 controls addressing and timing of data to/from disk platter 678. The data on disk platter 678 consists of groups of magnetic signals that may be detected by read/write head assembly 676 when the assembly is properly positioned over disk platter 678. In one embodiment, disk platter 678 includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.

In a typical read operation, read/write head assembly 676 is accurately positioned by motor controller 668 over a desired data track on disk platter 678. Motor controller 668 both positions read/write head assembly 676 in relation to disk platter 678 and drives spindle motor 672 by moving read/write head assembly to the proper data track on disk platter 678 under the direction of hard disk controller 666. Spindle motor 672 spins disk platter 678 at a determined spin rate (RPMs). Once read/write head assembly 678 is positioned adjacent the proper data track, magnetic signals representing data on disk platter 678 are sensed by read/write head assembly 676 as disk platter 678 is rotated by spindle motor 672. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter 678. This minute analog signal is transferred from read/write head assembly 676 to read channel circuit 610 via preamplifier 670. Preamplifier 670 is operable to amplify the minute analog signals accessed from disk platter 678. In turn, read channel circuit 610 decodes and digitizes the received analog signal to recreate the information originally written to disk platter 678. This data is provided as read data 603 to a receiving circuit. A write operation is substantially the opposite of the preceding read operation with write data 601 being provided to read channel circuit 610. This data is then encoded and written to disk platter 678.

During a read operation, data received from preamplifier circuit 670 is converted from an analog signal to a series of corresponding digital samples, and the digital samples are equalized to yield an equalized output. The equalized output is then provided to a data processing circuit including both a data detector circuit and a data decoder circuit. Data is passed between the data decoder and data detector circuit via an efficient interleaving/de-interleaving circuit. The efficient interleaving/de-interleaving circuit may be implemented similar to that discussed above in relation to FIG. 1, and/or may operate similar to that discussed in above in relation to FIG. 4.

It should be noted that storage system 600 may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. It should also be noted that various functions or blocks of storage system 600 may be implemented in either software or firmware, while other functions or blocks are implemented in hardware.

It should be noted that the various blocks discussed in the above application may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or only a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.

In conclusion, the invention provides novel systems, devices, methods and arrangements for data processing. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

1. A data processing system, the data processing system comprising: a local interleaver circuit operable to: receive a data input that includes at least a first local chunk and a second local chunk, rearrange an order of the first local chunk and the second local chunk to yield a locally interleaved data set, and write the locally interleaved data set to a first row of a first memory;wherein the locally interleaved data set includes at least a first global chunk stored to a first column of the first memory, and a second global chunk stored to a second column of the first memory; anda column controlled interleaver circuit operable to: access the locally interleaved data set from the first row of the first memory, store the first global chunk to the first column and a second row of a second memory, store the second global chunk to the second column and a third row of the second memory.

2. The data processing circuit of claim 1, wherein the data processing system is implemented as part of a device selected from a group consisting of: a storage device and a receiving device.

3. The data processing system of claim 1, wherein the data processing system is implemented as part of an integrated circuit.

4. The data processing system of claim 1, wherein the first row of the first memory is randomly selected.

5. The data processing system of claim 1, wherein the second row of the second memory is randomly selected, and wherein the third row of the second memory is randomly selected.

6. The data processing system of claim 1, wherein the first column of the second memory is selected to correspond to the first column of the first memory, and wherein the second column of the second memory is selected to correspond to the second column of the first memory.

7. The data processing system of claim 1, wherein the system further comprises: a data detector circuit operable to apply a data detection algorithm to a data set to yield the data input; anda data decoder circuit operable to apply a data decode algorithm to a globally interleaved data set generated by accessing the second row of the second memory including the first global chunk.

8. The data processing circuit of claim 7, wherein the data detection algorithm is selected from a group consisting of: a maximum a posteriori data detection algorithm, and a Viterbi algorithm data detection algorithm.

9. The data processing circuit of claim 7, wherein the data decode algorithm is a low density parity check algorithm.

10. A storage device, the storage device comprising: a storage medium;a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to information on the storage medium;a read channel circuit including:an analog to digital converter circuit operable to sample an analog signal derived from the sensed signal to yield a series of digital samples;an equalizer circuit operable to equalize the digital samples to yield an equalized output;a data detector circuit operable to apply a data detection algorithm to the equalized output to yield a detected output;a local interleaver circuit operable to: receive a data input that includes at least a first local chunk and a second local chunk, rearrange an order of the first local chunk and the second local chunk to yield a locally interleaved data set, and write the locally interleaved data set to a first row of a first memory;wherein the locally interleaved data set includes at least a first global chunk stored to a first column of the first memory, and a second global chunk stored to a second column of the first memory;a column controlled interleaver circuit operable to: access the locally interleaved data set from the first row of the first memory, store the first global chunk to the first column and a second row of a second memory, store the second global chunk to the second column and a third row of the second memory;wherein the first column of the second memory corresponds to the first column of the first memory, and wherein the second column of the second memory corresponds to the second column of the first memory; anda data decoder circuit operable to apply a data decode algorithm to a globally interleaved data set generated by accessing the second row of the second memory including the first global chunk.