Many high performance MEMS devices, such as gyroscopes and accelerometers, are hermetically packaged in a vacuum or a gaseous environment. Hermetically sealing the substrate components within a MEMS device allows a vacuum or gas atmosphere to remain stable over time. Several MEMS device technologies today hermetically seal MEMS device substrates at the package level, after dicing of a sensing substrate wafer. This sealing typically occurs individually or in small batches during a separate fabrication processing step. A number of package level sealing (PLS) processes are utilized to hermetically seal MEMS devices, including: silicon to glass anodic bonding, silicon to silicon fusion bonding, and wafer to wafer bonding, utilizing various intermediate bonding agents.
PLS can lead to problematic effects such as stiction between a sensing wafer and substrate components during a bonding process and lower production yield of MEMS devices. To eliminate this waste and reduce other undesirable characteristics associated with PLS, several wafer level packaging (WLP) techniques have been implemented. WLP is a wafer-scale packaging technology where the resulting package can be identical in size to the actual die and where all die on a wafer are sealed at the same time. WLP allows for integration of wafer fabrication, packaging (including device interconnection), and testing at the wafer level. Typically, WLP has been implemented in the same substrate layers that form the MEMS device (e.g., amongst the glass and silicon substrate layers of an ordinary multi-layer MEMS gyroscope or accelerometer).
In practice, WLP design is difficult to implement due to higher non-recurring engineering costs, increased unit production costs, and various technological challenges associated with presently available WLP techniques. Also, WLP production quantities are usually not high enough to be economically feasible. Other difficulties associated with this form of WLP include: difficulty achieving a hermetic seal over the wafer topography, difficulty getting signal leads through the seal without creating leaks, difficulty with electrical shorts or parasitic effects, difficulty achieving vacuum during sealing, difficulty installing a getter for vacuum applications, and difficulty maintaining dimensional control of device features such as capacitive gaps.
The present invention provides systems and methods for a hermetically sealed microelectromechanical sensor (MEMS) device. The hermetic sealing takes place at the wafer level during fabrication of the MEMS device. The MEMS device has a specialized hermetic interface chip (HIC) that facilitates a stable sealing process. An example HIC includes a plurality of vias in a substrate layer, a plurality of mesas having etched portions, a seal ring, a plurality of conductive leads connected to a first side of the HIC, and a plurality of conductive leads connected to a second side of the HIC. The plurality of conductive leads on the first side of the HIC feed from the etched portions of the plurality of mesas through the plurality of vias in the substrate layer to the plurality of conductive leads on the second side of the HIC.
In accordance with further aspects of the invention, the HIC includes at least one getter on a surface of the first side of the HIC, for creating ample gettering capacity in a vacuum atmosphere.
In accordance with further aspects of the invention, a MEMS device includes an HIC and a device component. The HIC having at least one via and at least one mesa. The device component having a first substrate layer, a mechanism device layer, and a second substrate layer. The HIC being hermetically sealed to the device component at the first substrate layer with a seal ring.
In accordance with further aspects of the invention, the fabrication of a MEMS device includes creating at least one via in a substrate layer of a hermetic interface chip (HIC), bonding a mesa layer to the substrate layer of the HIC, depositing conductive leads from at least one etched mesa to the at least one via, depositing a seal ring on the substrate layer of the HIC, and sealing the HIC to a device component at the seal ring.
In accordance with yet further aspects of the invention, the MEMS fabrication includes removing excess substrate material from mesa layer after bonding, such that the at least one etched mesa is independently bonded to the substrate layer of the HIC.
In accordance with other aspects of the invention, the fabrication includes aligning the seal ring of the HIC with a wetting film at the periphery of the device component and placing the at least one etched mesa into a hole in a substrate layer of the device component.
As will be readily appreciated from the foregoing summary, the invention provides for fabrication of a robust MEMS device that can be hermetically sealed at the wafer level. The MEMS device includes a HIC that facilitates a hermetic seal which maintains state-of-the-art gap control and increases production yield.
Preferred and alternative embodiments of the present invention are described in detail below with reference to the following drawings. These drawings only depict portions of an HIC and a device component of a MEMS device in accordance with various embodiments of the present invention:
The present invention provides microelectromechanical sensor (MEMS) devices and fabrication processing methods for improving production yield by hermetically sealing a MEMS device with a hermetic interface chip (HIC) at the wafer level. Additionally, the MEMS devices and packaging techniques of the present invention eliminate almost all problems associated with presently available Wafer Level Packaging (WLP) techniques by hermetically sealing a MEMS device with an additional wafer, the HIC.
The HIC 11 facilitates connection of the mechanism device layer 32 of the MEMS device 10 with the external leads 30 outside of the MEMS device during a hermetic sealing process. During fabrication, conductive interconnecting agents 22 are bonded to bond pads 34 to connect leads (not shown) emanating from the mechanism device layer 32 with the internal leads 26 disposed on the surface of the etched substrate mesas 20. The internal leads 26 on the substrate mesas 20 connect to the external leads 30 through a conductive trace included in the feedthrough vias 28. In an embodiment, the external leads 30 are made available for new packaging technologies such as flip-chip construction. Thus, the HIC 11 can act as an interface for additional chips such as analog application specific integrated circuits (ASIC) or digital signal processors (DSP).
In an embodiment, the etched substrate mesas 20 are formed of silicon and are pyramidal in shape. These mesas 20 are designed to fit inside of fabricated holes (e.g., ultrasonically drilled holes) in the upper substrate layer 14 of the device component 15. In one embodiment the upper substrate layer 14 and the lower substrate layer 16 of the device component 15 are formed of glass. In one embodiment, the upper substrate layer 12 of the HIC 11 can be formed of either glass or silicon. The internal leads 26 of the HIC 11 are patterned on the etched substrate mesas 20 to line up with the bond pads 34 on the lower substrate layer 16 of the device component 15. In an embodiment, each internal lead 26 disposed on the surface of an etched substrate mesa 20 terminates with the interconnecting agent 22, which is a solder ball that can be reflowed onto a bond pad 34 during a bonding process. The other end of the internal lead 26 terminates at the feedthrough vias 28.
In an embodiment, the outer seal ring 18 forms a continuous solder seal ring around the etched substrate mesas 20 and the at least one getter component 24. The solder ring hermetically seals around all openings between the upper substrate layer 12 of the HIC 11 and the upper substrate layer 14 of the device component 15. Because the feedthrough vias 28 go from the cavity space between the HIC 11 and the device component 15, through the upper substrate layer 12 of the HIC 11, rather than through the outer seal ring 18, there is no opportunity for electrical shorts or parasitics to occur.
Most of the non-mesa area inside the outer seal ring 18 of the HIC 11 remains unused. With this open chip topography, one or a plurality of getters 24 can be deposited anywhere within the non-mesa area of the HIC 11, thereby providing ample gettering capacity and a stable vacuum seal. A getter 24 is not needed in a gaseous atmosphere. Additionally, this open topography allows for the feedthrough vias 28 to be moved anywhere on the MEMS device 10.
There are multiple options for top side design of the HIC 11. In an embodiment, metal bond pads (not shown) can be patterned onto or near the feedthrough vias 28 on the top side of the upper substrate layer 12 of the HIC 11. These bond pads can be wire bonded to an external board or circuit such as an ASIC or DSP. In another embodiment, bump bonding balls are placed on the external leads 30 for flip chip bonding to an external board or circuit.
In this embodiment, placement of the integrated electronics inside the cavity of the MEMS device 60 could advantageously eliminate another level of external interconnection. The integrated electronics 36 would need to be fabricated on a planar wafer, before bonding with the mesa wafer, or after bonding the mesa wafer but before etching the mesas 20. Aside from these modifications, the process would essentially remain the same as described above (i.e., the MEMS fabrication process where the HIC 11 is formed of a silicon substrate). Integrating electronics into the silicon substrate in this process would put limits on the maximum processing temperature (e.g., 450° C.), but all the HIC process steps can be done at a lower temperature than that.
An example MEMS fabrication process for forming multiple MEMS devices in accordance with an embodiment of the present invention forms the upper substrate layer 12 of a HIC 11 of a silicon substrate which can be hermetically bonded with the upper substrate layer 14 of the device component 15. This process includes the following steps:
Another example of a MEMS fabrication process for forming the upper substrate layer 12 of a HIC 11 of a silicon substrate which can be hermetically bonded with the upper substrate layer 14 of the device component 15. This process includes the following steps:
An example of a MEMS fabrication process for forming multiple MEMS devices in accordance with another embodiment of the present invention includes an HIC formed of a glass substrate that can be hermetically bonded with an upper substrate layer of a device component. This process includes the following steps:
While several embodiments of the present invention have been illustrated and described herein, many changes can be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is not limited by any disclosed embodiment. Instead, the scope of the invention should be determined from the appended claims that follow.