Patent Application
20250068811
The semiconductor industry has experienced rapid growth due to continuous improvement in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size (e.g., shrinking the semiconductor process node towards the sub-nanometer node), which allows more components to be integrated into a given area. As the demand for miniaturization, higher speed, and greater bandwidth, as well as lower power consumption and latency has grown recently, there has grown a need for advanced packaging techniques for semiconductor dies.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over, or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” “top,” “bottom” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In accordance with increasingly advanced technology nodes, the design of integrated circuits seem to no longer begin with a circuit diagram. Typically, a circuit design starts with a high-level description or representation of the logic functions required for a new circuit. These logic function definitions are often described using a hardware description language (“HDL”) (e.g., a System Verilog, Verilog, VHDL, or other register-transfer level (“RTL”) description) or even using an algorithmic description (e.g., a C++, SystemC, or other algorithmic description). This functional description is utilized to generate a lower-level description or representation of the circuit that describes how the desired functionality is to be implemented. This lower-level representation is typically a gate-level netlist, such as a mapped netlist. Furthermore, the mapped netlist may then be placed and routed, thereby generating a placed and routed netlist. The process of generating a lower-level circuit description or representation (such as a gate-level netlist) from a high-level description of logic function (such as an RTL or algorithmic description) is referred to as “synthesis.” Accordingly, a software application used to generate a lower-level circuit description or representation from a high-level description of logic function is referred to as a “synthesis tool.”
A modern semiconductor device may be formed as a semiconductor package that includes a plural number of semiconductor chips, or integrated circuit (IC) chips, operatively and physically coupled to one another. Various technologies are utilized to integrate multiple IC chips into a single semiconductor package. Examples of semiconductor packages include a chip on wafer on substrate (CoWoS) package, an Integrated Fan-Out (InFo) package, a three-dimensional integrated circuit (3D IC) package, or the like. In a semiconductor package, different IC chips (e.g., with logic functionality) are typically coupled to each other through one or more connection structures (e.g., without logic functionality). In the existing technologies, simulating and/or verifying such a semiconductor package typically requires a significant amount of human efforts. For example, after separately synthesizing lower-level circuit descriptions for the different IC chips, physical arrangement and operative connection of the connection structures with respect to the IC chips are manually configured for (e.g., inserted into) the synthesized lower-level circuit description. This manual efforts disadvantageously complicate the design and corresponding verification on a semiconductor package. Thus, the existing technologies to design a semiconductor package have not been entirely satisfactory in some aspects.
The present disclosure provides various embodiments of an integrated circuit design implementation system that can automatically generate a netlist based on the design of a semiconductor package, and methods for operating the same. For example, the integrated circuit design implementation system can include a synthesis tool configured to receive a behavioral description of each of a plural number of IC chips of a semiconductor package, and generate a number of first netlists based on the behavioral descriptions of the IC chips. The synthesis tool can further receive connection information of a plural number of connection structures of the semiconductor package. In some embodiments, the connection information can configure overall physical arrangement and connectivity among the IC chips and the connection structures. Based on the connection information, the synthesis tool can generate a plural number of virtual interfaces each inserted between any two of the IC chips and/or the connection structures. In response, the synthesis tool can automatically convert the IC chip, the connection structures, and the virtual interfaces into first vertices, second vertices, and third vertices, respectively, and connect those vertices with edges, thereby forming a unique graph for this semiconductor package. According to the graph, the synthesis tool can update the first netlists as a second netlist, which can be utilized to simulate and/or verify the designed semiconductor package. In this way, the system, as disclosed herein, can significantly help to reduce time and efforts for designing a semiconductor package.
The bus 130 may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus, or video bus. The CPU 120 may include any type of electronic data processor, and the memory 122 may comprise any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).
The mass storage device 124 may include any type of storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via the bus 130. The mass storage device 124 may include, for example, one or more of a hard disk drive, a magnetic disk drive, an optical disk drive, or the like.
The video adapter 126 and the I/O interface 128 provide interfaces to couple external input and output devices to the processing tool 110. As illustrated in
It should be noted that the processing system 100 may include other components. For example, the processing system 100 may include power supplies, cables, a motherboard, removable storage media, cases, and the like. These other components, although not shown, are considered part of the processing system 100.
In various embodiments of the present disclosure, an electronic design automation (EDA) is program code that is executed by the CPU 120 to automatically generate a netlist based on the design of a semiconductor package (described further below with respect to
For example, the behavioral/functional design 201 can specify the desired behavior or function of the logic chips based upon various signals or stimuli applied to inputs of the overall design, and may be written in a suitable language, such as a hardware description language (HDL). The behavioral/functional design 201 may be uploaded into the processing tool 110 (see
The connection information 203 can specify physical arrangement and connectivity among the logic chips and the non-logic structures, in accordance with various embodiments of the present disclosure. For example, the connection information 203 can include how the logic chips are physically arranges with one another, e.g., side-by-side, on top of one another, or combinations thereof. In another example, the connection information 203 can include how different ones of the logic chips are electrically coupled to each other. Based on the techniques to form the semiconductor package, the non-logic structures can include any of various structures that can provide electrical connection function and/or mechanical support. Examples of the non-logic structures include a physical substrate (e.g., a printed circuit board (PCB), a chip scale package (CSP) substrate), a physical redistribution layer (RDL), and a physical interposer (e.g., a silicon interposer, an organic interposer, etc.). Similar to the behavioral/functional design 201, the connection information 203 may be uploaded into the processing tool 110 (see
The EDA can take the behavioral/functional design 201 and the connection information 203, and perform a synthesis, e.g., by a synthesis tool 210, to generate a netlist, e.g., 211. In a brief overview, the synthesis tool 210 can first form a number of functionally equivalent logic gate-level circuit descriptions (hereinafter “first netlists”) corresponding to the logic chips, respectively, based on the behavioral/functional design 201. It should be noted that such first netlists can each represent a gate-level description for the corresponding individual logic chip. Next, the synthesis tool 210 can transform the first netlists to the netlist 211 (hereinafter “second netlist”), which includes how the logic chips are physically arranged and operatively communicated with each other through the non-logic structures, based on the connection information 203. The synthesis tool 210 can generate the second netlist based on a graph, including a number of vertices connected to one another through corresponding ones of edges, which will be discussed as follows.
According to various embodiments of the present disclosure, while generating the first netlists (for the logic chips), the synthesis tool 210 can convert the logic chips into a number of first vertices, respectively. Next, upon receiving the connection information 203 (specifying the non-logic structures), the synthesis tool 210 can convert the non-logic structures into a number of second vertices, respectively. For example, the synthesis tool 210 may arrange the second vertices and the first vertices according to the physical arrangement specified in the connection information 203. Next, the synthesis tool 210 can generate a number of third vertices, each of which corresponds to a virtual interface between any two of the logic chips and the non-logic structures. Next, the synthesis tool 210 can connect two of the first vertices, second vertices, and/or third vertices through a number of edges. For example, the synthesis tool 210 may generate or otherwise configured such edges according to the connectivity (among the logic chips and the non-logic structures) specified in the connection information 203. As a result, a graph consisting of the first vertices, second vertices, third vertices, and edges can be formed. The synthesis tool 210 can determine this graph uniquely corresponding to the semiconductor package. As a result, the synthesis tool 210 can automatically transform the first netlists as the second netlist 211.
In some embodiments, the synthesis tool 210 can provide the second netlist 211 to a place and route tool 220. Based on the second netlist 211, the place and route tool 220 can create an actual physical design for the overall structure (e.g., the semiconductor package). The place and route tool 220 can form the physical design by taking chosen cells from cell libraries and placing them into cell rows. These cell rows generally have a row height similar to the height of a majority of the individual cells located within that cell row such that the power rails, implants and wells may be aligned between the individual cells. The placement of each individual cell within the cell rows, and the placement of each cell row in relation to other cell rows, may be guided by cost functions in order to minimize wiring lengths and area requirements of the resulting integrated circuit. This placement may be done either automatically by the place and route tool 220, or else may alternatively be performed partly through a manual process, whereby a user may manually insert one or more cells into a row.
Once the placement and route tool 220 finishes generating the actual physical design for the overall structure, a verification tool 230 can provide a physical verification of the semiconductor package. The physical verification generally includes a timing verification, a design rule check (DRC), a layout versus schematic (LVS) analysis, and an electrical rule check (ERC). Once the physical verification is completed with satisfactory results, the design of the semiconductor package can be sent to a manufacturing tool 240 to generate, e.g., photolithographic masks, that may be used in the physical manufacture of the desired design. The design may be sent to the manufacturing tool 240 through that LAN/WAN 116 (
Referring first to the top view of
In the illustrated embodiment of
For example, the chip A is coupled to the chip C through the layer X (
In the illustrated embodiment of
For example, the chip A is coupled to the chip C through the layer Y (
In some embodiments, the synthesis tool 210 (
In
In
In one aspect of the present disclosure, an integrated circuit design implementation system is disclosed. The system includes a synthesis tool configured to: receive a behavioral description of each of a plurality of first components; generate first netlists based on the behavioral descriptions of the first components; receive connection information of a plurality of second components, wherein the connection information comprises physical arrangement and connectivity among the plurality of first components and the plurality of second components; generate a plurality of third components, wherein each of the plurality of third components operatively corresponds to an interface between a pair of one of the first components and one of the second components; and transform the first netlists to a second netlist based on a plurality of first vertices, a plurality of second vertices, a plurality of third vertices, and a plurality of edges. The first vertices correspond to the first components, respectively, the second vertices correspond to the second components, respectively, and the third vertices correspond to the third components, respectively.
In another aspect of the present disclosure, a method for verifying a semiconductor package is disclosed. The method includes receiving a behavioral description of each of a plurality of logic chips; generating first netlists based on the behavioral descriptions of the logic chips; receiving connection information of a plurality of non-logic structures, wherein the connection information comprises overall physical arrangement and connectivity among the plurality of logic chips and the plurality of non-logic structures; generating a plurality of virtual interfaces, wherein each of the plurality of virtual interfaces operatively corresponds to an interface between a pair of one of the logic chips and one of the non-logic structures; generating a graph consisting of a plurality of first vertices, a plurality of second vertices, a plurality of third vertices, and a plurality of edges, wherein the first vertices correspond to the logic chips, respectively, the second vertices correspond to the non-logic structures, respectively, and the third vertices correspond to the virtual interfaces, respectively; and transforming the first netlists to a second netlist based on the graph.
In yet another aspect of the present disclosure, a computer program product comprising a computer-readable program medium code stored thereupon is disclosed. The code, when executed by a processor, causes the processor to implement a method. The method includes receiving a behavioral description of each of a plurality of logic chips; generating first netlists based on the behavioral descriptions of the logic chips; receiving connection information of a plurality of non-logic structures, wherein the connection information comprises overall physical arrangement and connectivity among the plurality of logic chips and the plurality of non-logic structures; generating a plurality of virtual interfaces, wherein each of the plurality of virtual interfaces operatively corresponds to an interface between a pair of one of the logic chips and one of the non-logic structures; generating a graph consisting of a plurality of first vertices, a plurality of second vertices, a plurality of third vertices, and a plurality of edges, wherein the first vertices correspond to the logic chips, respectively, the second vertices correspond to the non-logic structures, respectively, and the third vertices correspond to the virtual interfaces, respectively; and transforming the first netlists to a second netlist based on the graph.
As used herein, the terms “about” and “approximately” generally indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value).
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
