Computing devices comprising at least one processor coupled to a memory are ubiquitous. Computing devices may include personal computing devices (PCDs) such as desktop computers, laptop computers, portable digital assistants (PDAs), portable game consoles, tablet computers, cellular telephones, smart phones, and wearable computers. In order to meet the ever-increasing processing demands of users, PCDs increasingly incorporate multiple processors or cores running instructions or threads in parallel.
However, such use of multiple processors can lead to significant problems if one core or processor becomes “hung” or unable to programmatically make progress on a task because of a hardware issue, such as processor or system deadlock. Existing “processor hang” solutions depend on software detection mechanisms which are ineffectual to detect processor hang that results from a hardware issue. Additionally, existing back-up watchdog methods that may detect processor hang from a hardware issue only come into play after a relatively long period of time, on the order of multiple seconds.
Such a long period of time with a hung processor can result in the other processors or components of a PCD becoming hung themselves, resulting in a catastrophic event for the PCD. Alternatively, a long period of time with a hung processor can result in the other processors or components of a PCD operating unchecked which may lead to other issues, such as the other processors or components staying active and leaking power while waiting on the hung processor, causing thermal issues.
Accordingly, there is a need for improved systems and methods to quickly detect processor hang in a PCD, and/or to better recover from such processor hang, especially where such processor hang is caused by a hardware issue.
Systems, methods, and computer programs are disclosed for implementing processor hang detection in a personal computing device (PCD). An exemplary method includes setting a timer with a hang threshold value for each of a plurality of processors of a system on a chip (SoC). The hang threshold value representing a time in microseconds. A first heartbeat signal from each of the plurality of processors is received at a detection logic hardware of a hang controller, the detection logic hardware coupled to the plurality of processors and to the timer. The timer for each of the plurality of processors is reset if a second heartbeat signal is received from the corresponding one of the plurality of processors before the timer expires. Otherwise, a hang event notification is generated by the hang controller if the second heartbeat signal is not received from the corresponding one of the plurality of processors before the timer expires.
In another embodiment, a computer system for improved processor hang detection in a portable computing device (PCD) is provided. The system comprises a system-on-a-chip (SoC) with a plurality of processors. Each of the plurality of processors is configured to generate a heartbeat signal indicating that the respective one of the plurality of processors is programmatically executing instructions. The system also comprises a hang controller in communication with each of the plurality of processors. The hang controller includes a timer set with a hang threshold value for each of the plurality of processors. The hang threshold value representing a time in microseconds.
The hang controller also includes detection logic hardware in communication with the timer and the plurality of processors. The detection logic hardware is configured to receive a first heartbeat signal from each of the plurality of processors and to: either reset the timer for each of the plurality of processors if a second heartbeat signal is received from the corresponding one of the plurality of processors before the timer expires; or generate a hang event notification if the second heartbeat signal is not received from the corresponding one of the plurality of processors before the timer expires.
In the Figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as “102A” or “102B”, the letter character designations may differentiate two like parts or elements present in the same Figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral to encompass all parts having the same reference numeral in all Figures.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
In this description, the term “application” or “image” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, an “application” referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
The term “content” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, “content” referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
As used in this description, the terms “component,” “database,” “module,” “system,” and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device may be a component. One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components may execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal).
In this description, the term “computing device” is used to mean any device implementing a processor (whether analog or digital) in communication with a memory, such as a desktop computer, gaming console, or server. A “computing device” may also be a “portable computing device” (PCD), such as a laptop computer, handheld computer, or tablet computer. The terms PCD, “communication device,” “wireless device,” “wireless telephone”, “wireless communication device,” and “wireless handset” are used interchangeably herein. With the advent of third generation (“3G”) wireless technology, fourth generation (“4G”), Long-Term Evolution (LTE), etc., greater bandwidth availability has enabled more portable computing devices with a greater variety of wireless capabilities. Therefore, a portable computing device may also include a cellular telephone, a pager, a smartphone, a navigation device, a personal digital assistant (PDA), a portable gaming console, a wearable computer, or any portable computing device with a wireless connection or link.
In order to meet the ever-increasing processing demands placed on PCDs, PCDs increasingly incorporate multiple processors or cores (such as central processing units or “CPUs”) running various threads in parallel. However, these increasing demands, and the use of multiple CPUs can lead to significant problems if one CPU or processor becomes “hung.” “CPU hang” as used herein refers to a situation where the CPU is unable to programmatically make progress for a certain finite period of time because of a hardware issue, such as CPU or system deadlock. CPU hang solutions that depend entirely on software detection mechanisms cannot typically detect CPU hang that results from a hardware issue. Instead, the path on which such software mechanisms rely become inoperative if a CPU hangs because of a hardware issue. Additionally, watchdog methods that may detect CPU hang only act after a relatively long period of time, on the order of multiple seconds.
The system and methods of the present disclosure implement a hardware solution that detects and monitors signals from each CPU of a system on a chip (SoC) that indicate the CPU is still operating (referred to herein at “heartbeat” signals). If a heartbeat signal is not detected by the hardware component for a particular CPU within a pre-established threshold, the CPU is determined to be hung and recovery action is taken. The system and methods allow for significantly quicker detection of CPU hang than is possible with existing solutions, detecting CPU hang in microseconds (μS) rather than seconds.
Such rapid detection of CPU hang provides several benefits not possible with current solutions. For example, the systems and methods of the present disclosure allow for recovery from CPU hang, including reset of the CPU and/or SoC much earlier, and possibly before a user notices the CPU hang, resulting in an improved user experience. Additionally, rapid detection of CPU hang allows for recovery of the hung CPU before the hung CPU causes further issues (such as hanging other components of the PCD), without having to reset the entire PCD. Similarly, rapid detection of CPU hang, and detection at the CPU level, allows for relevant diagnostic information to be captured closer to the point of fault and before the diagnostic information is altered or overwritten by other active system components. Finally, immediate detection of hung CPUs can improve thermal mitigation of the PCD, such as for instance thermal issues caused by not only the hung PCU leaking power, but also the other CPUs or system components burning active power while waiting on the hung CPU.
Although discussed herein in relation to PCDs, the systems and methods herein—and the considerable savings made possible by the systems and methods—are applicable to any computing device.
As illustrated in the embodiment of
Additionally, the SoC 102 may include other on chip components, such as a memory controller 120, a cache 110 memory, and a system memory 112, all interconnected via a SoC bus 116. As will be understood, the SoC 102 of
One of the CPUs, such as CPU0106a may be controlled by or execute an operating system (OS) that causes CPU0106a to operate or execute various applications, programs, or code stored in one or more memory of the computing device. In some embodiments one or more of CPU0106a, CPU1106b, CPU2106c and CPUN 106n may be the same type of processor. In other embodiments, one or more of CPU1106b, CPU2106c, and CPUN 106n may be a digital signal processor (DSP), a graphics processing unit (GPU), an analog processor, or other type of processor different from CPU1106a executing the OS.
The cache 110 memory of
System memory 112 may be a static random access memory (SRAM), a read only memory (ROM) 112, or any other desired memory type, including a removable memory such as an SD card. Memory controller 120 is electrically connected to the SoC bus 116 and also connected to the memory device 130 by a memory access channel 124 which may be a serial channel or a parallel channel in various embodiments. Memory controller 120 manages the data read from and/or stored to the various memories accessed by the SoC 102 during operation of the system 100, including memory device 130 illustrated in
In the illustrated embodiment of
The SoC 102 of the system 100 also includes an interrupt controller 104 in communication with each of CPUs 106a-106n. Interrupt controller 104 provides interrupts to, and receives responses to interrupts from, each of CPUs 106a-106n. In an embodiment, interrupt controller 104 may also provide interrupts to other components of the SoC 102 or processes operating on the SoC 102 (not illustrated), such as interrupts to various drivers used by one or more of CPUs 106a-106n. The SoC 102 may also include various system software 113 in communication with interrupt controller 104. System software 113 may be operated by one or CPUs 106a-106n, or which may be operated on or by a dedicated processor.
System software 113, may in an embodiment include CPU health check software 118, which may be software interrupt based and may provide interrupts to one or more of CPUs 106a-106n though interrupt controller 104 based on detected issues or problems with one or more CPUs. System software 113 may also include thermal mitigation software 115. Thermal mitigation software 115 may implement various thermal mitigation policies for the SoC 102, and may provide interrupts to various drivers through interrupt controller 104.
SoC 102 may also include a watchdog 114 component in communication with the system software 113 and a reset controller 140 that is also in communication with the SoC bus 116. Although not illustrated in
The SoC 102 also includes a core hang controller 150 coupled to each of CPUs 106a-106n, such as through the SoC bus 116 as illustrated in
In an embodiment, the signal received or monitored by core hang controller 150 is a signal from each of CPUs 106a-106n indicating that CPUs 106a-106n are still operating properly and/or a signal from which core hang controller 150 may determine whether any of CPUs 106a-106n are hung (referred to herein as a “heartbeat” signal). Although illustrated as a single component in
Core hang controller 150 is coupled to reset controller 140, such as through SoC bus 116 as illustrated in
In the illustrated embodiment, resource power manager 144 and decision support software 142 as shown as two separate components. In other implementations, the resource power manager 144 and decision support software 142 (or the functionality of these components) may be combined into one component. Similarly, one or both of resource power manager 144 or decision support software 142 may be combined with the reset controller 140 into a single component in some implementations.
In an embodiment, the reset controller 140, resource power manager 144 and decision support software 142 are all coupled to an output of the core hang controller 150 (see
Core hang controller 150 allows for the rapid detection of hangs by any of CPUs 106a-106n resulting from hardware issues. In an embodiment, core hang controller may accomplish this rapid detection by monitoring the heartbeat signals from each of CPUs 106a-106n.
In an embodiment the detection logic 152 is a hardware component electrically coupled to the output of each of CPUs 106a-106n to be monitored for CPU hang. During operation, detection logic 152 receives a periodic heartbeat signal 156a-156n from each of CPUs 106a-106n indicating that each of CPUs 106a-106n are still programmatically executing instructions and therefore not hung. In an embodiment where CPUs 106a-106n are Advanced RISC Machine (ARM) based or complaint processors, the heartbeat signals 156a-156n may be Performance Monitoring Unit (PMU) exported events from CPUs 106a-106n that detection logic 152 is configured to receive and/or understand.
For example, an instruction_retired message generated by ARM-based processors for performance measurement may also be received by detection logic 152 of the core hang controller 150. Such instruction_retired messages may be used by the detection logic 152 as the heartbeat signals 156a-156n to determine that CPUs 106a-106n are still programmatically executing instructions and therefore not hung. Note that other messages or signals, such as from non-ARM-based processors may also be used as the heartbeat signals 156a-156n. It is not necessary that the same type of heartbeat signal 156a-156n be used for all of CPUs 106a-106n. For example the type of message or signal used as heartbeat signal 156a for CPU0106a may be a different signal or message that is used as the heartbeat signal 156b for CPU1106b.
Timer 154 of the core hang controller 150 may be a software component. In operation, timer 154 or a portion of timer 154 is reset for each CPU 106a-106n when a heartbeat signal 156a-156n is received for the respective CPU 106a-106n. As long as the heartbeat signal 156a-156n is received before the timer 154 expires, the core hang controller 150 knows that none of the CPUs 106a-106n are hung. However, if the timer 154 expires for any of CPUs 106a-106n, the core hang controller 150 knows or determines that the CPU(s) 106a-106n for which the timer 154 has expired is hung. In that event core hang controller 150 may sent an hang event notification 155 to resource power manager 144, decision support software 142 and reset controller 140. Although illustrated as a single component of core hang controller 150, timer 154 may instead be implemented as multiple individual timers 154 (not illustrated) each of the multiple timers 154 associated with one of the CPUs 106a-106n.
Timer 154 is programmable with at least a hang threshold value for each CPU 106a-106n to be monitored. The hang threshold value represents a length of time for the timer 154 to count down for each CPU 106a-106n before the core hang controller 150 will deem or determine the CPU 106a-106n to be hung and no longer programmatically executing tasks. The hang threshold value is determined or set at a value or length of time that ensures long latency operations, such as operations that typically take a few hundred processor cycles to complete do not cause the timer 154 to expire while a CPU 106a-106n is still executing the long latency operations. A complex single instruction multiple data (SIMD) floating point operation, or a memory access to a relatively slow peripheral are examples of such long latency operations.
Even accounting for such long latency operations, the hang threshold value will typically be measured in microseconds (μS) or milliseconds (mS), rather than the multiple seconds required for a typical watchdog 114. Thus, the timer 154 in connection with the detection logic 152 hardware allow the core hang controller 150 to detect a processor or CPU hang much quicker than a typical watchdog 114, and to detect processor or CPU hang closer in location to the hardware issue causing the hung condition.
The hang threshold value for each CPU 106a-106n may be different and may depend on the architecture, use to which the CPU 106a-106n may be put, etc. In an embodiment, this threshold value may be set or programmed for each CPU 106a-106n at initialization of the SoC 102. In some embodiments, the threshold value may be re-programmed for one or more CPUs 106a-106n during operation of the SoC 102 if desired. Additionally, in some embodiments the timer 154 for each CPU 106a-106n may have different threshold values for different states or conditions of the CPU 106a-106n.
For example, the timer 154 associated with CPU 106a may have a first threshold value that is applied for a “power up” operating state such as when the CPU 106a is coming out of a low or reduced power mode. The timer 154 associated with CPU 106a may also have a second threshold value that is applied for a “normal” operating state—i.e. when the CPU 106a is operating at a “full” power mode or state. As will be understood, it is possible to have multiple hang threshold values for each CPU 106a-106n and to have a different number of threshold values (and different value programmed for the threshold values) for each of the different CPUs 106a-106n.
In operation of the system 200 of
Continuing with the example, if a subsequent or second heartbeat signal 156a is received by the detection logic 152 before the timer 154 associated with CPU0106a expires, the timer 154 is reset. Similarly, if a subsequent or second heartbeat signal 156b is received by the detection logic 152 before the timer 154 associated with CPU1106b expires, the timer 154 is reset. The timer 154 continues to be reset as long as the heartbeat signals 156a-156n are received before the timer 154 for the CPUs 106a-106n expires.
If the timer 154 expires for any of CPUs 106a-106n before a second or subsequent heartbeat signal 156a-156n is received the core hang controller 150 determines or deems a processor hang for that particular CPU 106a-106n. The core hang controller 150 then generates a hang event notification 155. In an embodiment, the hang event notification 155 is generated by a hardware component of the core hang controller such as detection logic 152. The hang event notification 155 may be a message or signal that identifies at least which CPU 106a-106n is hung. In some embodiments the hang event notification 155 may also provide additional information, such as whether this is the first, second, third, etc., time the particular CPU 106a-106n has hung, of how many times the CPU 106a-106n has hung in a specified time period, etc.
The hang event notification 155 is received by one or more of the resource power manager 144, decision support software 142, and reset controller 140. In an embodiment, the core hang controller 150 may include logic to determine which component(s) to send hang event notification 155 to. In such embodiments, the logic of the core hang controller 150 may base such determination at least in part on the type of desired action in response to the hang event notification 155.
For example, the logic of the core hang controller 150 may determine that an attempt to recover a hung CPU0106a without reset of the CPU0106a or the entire SoC 102 is desirable or warranted under the circumstances. In that event, core hang controller 150 may send the hang event notification 155 to the resource power manager 144. The resource power manager 144 may in turn issue a recovery command 164, such as to the software 113 to attempt to recover the hung CPU0106a.
On the other hand, in the above example the logic of the core hang controller 150 may determine that an attempt to recover a hung CPU0106a is not desirable or warranted. Instead the determination may be that the conditions warrant a reset of the hung CPU0106a or the entire SoC 102. Such a determination may be made, for example when one or more previous attempts to recover the hung CPU0106a have been unsuccessful. Core hang controller 150 may in this situation decide to send the hang event notification 155 to the reset controller 140. Reset controller 140 may in turn generate a reset command 166 for the particular hung CPU0106a, such as by issuing a reset command 166 to software 113 as illustrated in
As will be understood, the decisions and determinations how to respond to a hung CPU, such as CPU0106a in the above example, may instead be made wholly or in part at resource power manager 144, decision support software 142, reset controller 140, or a combination of these components. In such embodiments, the core hang controller 150 may provide the hang event notification 155 with the information about the hung processor, CPU0106a. Based on the information in the hang event notification 155, one or more of resource power manager 144, decision support software 142, reset controller 140, or a combination of these components may determine what action to take. As discussed above, a determination may be made by one or more of the above components, acting alone or in connection with other, to first attempt to recover the hung processor such as CPU0106a, without resetting either the CPU0106a or the SoC 102. In that event, the resource power manager 144 may determine to first issue a recovery command 164, such as to the software 113 to attempt to recover the hung CPU0106a.
Resource power manager 144, decision support software 142 and/or reset controller 140 may, on the other hand, determine that an attempt to recover the hung processor, CPU0106a in the example, is not desirable or warranted. Instead, the determination may be that a reset of the hung CPU0106a or reset of the entire SoC 102 is needed. Such determination may be made when one or more previous attempts to recover the hung CPU0106a have been unsuccessful. In these circumstances reset controller 140 may determine to, or may be caused to, generate a reset command 166 for the particular hung CPU0106a, such as by issuing a reset command 166 to software 113 as illustrated in
The determination whether to reset the hung CPU0106a or the entire SoC 102 may be made in an embodiment based on information in the hang event notification 155. Information included in the hang event notification 155 may include whether this is the first, second, third, etc., time the particular CPU0106a has hung, how many times the CPU0106a has hung in a specified time period, whether/how many attempts to recover the CPU0106a have been made, whether/how many attempts to reset CPU0106a have been made, etc.
In the event that the decision is to reset either the CPU0106a or the entire SoC 102, the present system 200 allows for information near the hung CPU0106a to be captured and preserved for diagnosis/debugging after the CPU0106a or SoC 102 is reset. Since core hang controller 150 allows for rapid detection of processor or CPU hang, and detection of such hang conditions close to the hardware issue, such diagnosis information can be more easily preserved without need for large memory stores and/or without fear that subsequent system 200 activity will overwrite the diagnosis information.
For instance, resource power manager 144 may include a logging logic and/or memory such as buffer 145. When a decision is made to reset the CPU0106a or the SoC 102, current information about the operation of the CPU0106a, instructions the CPU0106a was attempting to perform, a power transition that instructions asked the CPU0106a to make, etc., may be stored in buffer 145. Since this information is near in time and location to the detection of the processor hang at CPU0106a, the buffer 145 may be relatively small and still capture information related to the CPU0106a hang that is useful to diagnosing, debugging, trace backs, etc. after CPU0106a is reset.
As illustrated in
The system 200 may also include a watchdog 114 component in communication with the system software 113 and in communication with the reset controller 140. The watchdog 114 also acts in parallel with the core hang controller 150 and may provide a back-up to the core hang controller 150. Although not illustrated in
Method 300 continues in block 304 where heartbeat signals, such as heartbeat signals 156a-156n of
In block 306 a hang event notification is generated when the heartbeat signal 156a-156n for a respective CPU 106a-106n is not received or detected by the detection logic 152 hardware within the threshold period. Block 306 may be implemented as illustrated in
Returning to block 402, as illustrated in
In block 404 a determination is made whether the countdown timer has expired. This determination may be a determination or recognition by the timer 154 or other component of the core hang controller 150 that timer 154 has reached the threshold value set or programmed for one of CPUs 106a-106n. If the determination in block 404 is that the countdown timer has not expired, method 400 continues to block 406.
A determination is made in block 406 whether a heartbeat signal has been received from the processor or CPU associated with the countdown timer. This heartbeat signal in block 406 may be the heartbeat signal 156a-156n associated with CPUs 106a-106n discussed above for
If the determination in block 406 is that a heartbeat signal has been received for one of CPUs 106a-106n, the method returns to block 402. In block 402, the countdown timer (such as timer 154) associated with the CPU 106a-106n for which the heartbeat signal (such as signals 156a-156n) has been received is re-set. The method 400 then reiterates to block 404 as discussed above. As will be understood, in some embodiments, the order of blocks 404 and 406 may be reversed if desired. In yet other embodiments, blocks 404 and 406 may not be separate steps, but may instead be combined into one determining step or block that checks both the timer 154 (block 404) and whether a heartbeat signal associated with the timer 154 has been received (block 406).
Returning again to block 404, if the determination is that the countdown timer, such as timer 154 for one of CPUs 106a-106n has expired, the method 400 continues to block 408 where a hang detection signal is generated. In an embodiment block 408 may comprise the core hang controller 150, or a component thereof such as detection logic 152 hardware, generating a hang event notification 155 identifying the CPU 106a-106n for which a hang condition has been determined/detected.
In block 410 a determination is made whether the hung CPU 106a-106n may be recovered. In an embodiment the determination in block 410 may be made by the core hang controller 150. In these embodiments, the hang detection signal (hang event notification 155) may include information or instructions to take action in response to the determination in block 410.
In other embodiments, the determination in block 410 may be made by one or more of a resource power manager 144, decision support software 142, or reset controller 140 (or by a combination of these components). In such embodiments, the determination in block 410 may be based at least in part on information contained in the hang detection signal (hang event notification 155) generated in block 408. Information on which the determination in block 410 may be in part based includes, whether this is the first, second, third, etc., time the particular CPU 106a-106n associated with the hang detection signal of block 408 has hung, how many times the CPU 106a-106n has hung in a specified time period, whether/how many attempts to recover the CPU 106a-106n have been made, whether/how many attempts to reset CPU 106a-106n have been made, etc.
If the determination in block 410 is that the CPU 106a-106n is recoverable, or at least that the attempt to recover the CPU 106a-106n should be made, method 400 continues to block 412 where recover of CPU 106a-106n is attempted. In an embodiment, the recover attempt in block 412 may comprise the resource power manager 144 sending a recovery command 164 to cause an interrupt from interrupt controller 104. As illustrated in
Returning to block 410, if the determination is that the CPU 106a-106n is not recoverable, or at least that an attempt or further attempt to recover the CPU 106a-106n should not be made, method 400 continues to block 414. In block 414 diagnostic information is saved, such as in buffer 145 of the resource power manager 144 as discussed above for
Alternatively, the reset in block may comprise resetting the SoC 102, such as with a system reset command 168 from the reset controller 140 as shown in
At other times when the CPU0106a is not currently being monitored to see if it is hung, it may be desirable to begin monitoring CPU0106a at some point. For example, it CPU0106a is in a low power mode of state and is transitioning back into a full power or normal operational mode or state, it is desirable to begin monitoring CPU0106a to see if it is hung, both as CPU0106a is transitioning, and once CPU0106a reaches the normal operational mode or state.
Exemplary method 500 allows a system, such as system 100 of
Method 500 begins in block 502 where a notification of a change in status for CPU0106a is received. The notification may be received at the core hang controller 150 from CPU0106a in an embodiment. The status change may represent in some embodiments a change in power level, such as CPU0106a being placed into a low or reduced power state or mode. The status change may conversely represent the CPU0106a waking up from a low or reduced power state or mode into a normal or fully powered state. Additionally, the status change may represent CPU0106a being placed into a debugging or other state or mode where monitoring CPU0106a for a hang condition is not needed or less important. The state change may also represent CPU0106a returning from such debugging mode or other state or mode into a normal or fully operational mode or state where monitoring is desired.
In block 504 a determination is made whether to enable (or disable) monitoring of CPU0106a based on the received status information. The determination in block 504 may be made in an embodiment by the core hang controller 150 or a component thereof. The determination in block 504 may comprise a determination whether CPU0106a is to be monitored for processor hang at all based on the received status information. The determination in block 504 may also compromise a determination of a hang threshold value (see
Method 500 continues to block 506 where the monitoring of CPU0106a is enabled (or disabled) based on and in accordance with the determination of block 504. In and embodiment, enabling the monitoring of CPU0106a may comprise beginning the method 400 of
Systems 100 (
A display controller 628 and a touch screen controller 630 may be coupled to the CPU 602. In turn, the touch screen display 606 external to the on-chip system 102 may be coupled to the display controller 628 and the touch screen controller 630.
Also, a video port 638 is coupled to the video amplifier 636. As shown in
Further, as shown in
As further illustrated in
Referring to
It should be appreciated that one or more of the method steps described herein may be stored in the memory as computer program instructions. These instructions may be executed by any suitable processor in combination or in concert with the corresponding module to perform the methods described herein.
Certain steps in the processes or process flows described in this specification naturally precede others for the invention to function as described. However, the invention is not limited to the order of the steps or blocks described if such order or sequence does not alter the functionality of the invention. That is, it is recognized that some steps or blocks may performed before, after, or parallel (substantially simultaneously with) other steps or blocks without departing from the scope and spirit of the invention. In some instances, certain steps or blocks may be omitted or not performed without departing from the invention. Further, words such as “thereafter”, “then”, “next”, etc. are not intended to limit the order of the steps. These words are simply used to guide the reader through the description of the exemplary method.
Additionally, one of ordinary skill in programming is able to write computer code or identify appropriate hardware and/or circuits to implement the disclosed invention without difficulty based on the flow charts and associated description in this specification, for example.
Therefore, disclosure of a particular set of program code instructions or detailed hardware devices is not considered necessary for an adequate understanding of how to make and use the invention. The inventive functionality of the claimed computer implemented processes is explained in more detail in the above description and in conjunction with the Figures which may illustrate various process flows.
In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, NAND flash, NOR flash, M-RAM, P-RAM, R-RAM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessed by a computer.
Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (“DSL”), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.
Disk and disc, as used herein, includes compact disc (“CD”), laser disc, optical disc, digital versatile disc (“DVD”), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
Alternative embodiments will become apparent to one of ordinary skill in the art to which the invention pertains without departing from its spirit and scope. Therefore, although selected aspects have been illustrated and described in detail, it will be understood that various substitutions and alterations may be made therein without departing from the spirit and scope of the present invention, as defined by the following claims.