Patent Grant
12087248
In general, an LCoS display uses a liquid crystal layer on top of a silicon backplane. Most LCoS displays include a CMOS chip that controls the voltage associated with each pixel (VPIX). These displays require a certain voltage for the common electrode to each cell. This common voltage for all the pixels is usually supplied by a transparent conductive layer made of indium tin oxide on the cover glass.
Known voltage generation circuits for generating the common electrode voltage (VCOM) employ transistors having a high breakdown voltage. As a result, the die area increases; and thereby, the cost for the circuitry increases. Many of the voltage generation circuits for generating the common electrode voltage employ transistors operating as a linear amplifier that require larger power supply voltages, which increases the power consumption. For example, some voltage generation circuits require a high voltage of approximately 9-10V. Current circuit designers implement these circuits using a large power dissipation linear amplifier, which operates at a high current (approximately 2-3 mA), where the power requirement ranges from 20 mW to 30 mW. Additionally, since conventional circuits have a high breakdown voltage, there is less opportunity for integration with other circuits or functions. Particularly, most known implementations for generating the common electrode voltage employ transistors that are not suitable for high levels of integration.
Embodiments of a system, circuit, and method for implementing a low power common electrode voltage output for spatial light modulators and/or displays (e.g., LCoS displays) having transistors with low to moderate breakdown voltages are provided. It should be appreciated that the embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a device, or a method.
In some embodiments, a display system having circuitry for generating a common electrode voltage is provided. The system may include a first low voltage amplifier configured to generate a predetermined voltage for setting the common electrode voltage (VCOM) in comparison to ground/and or VPIX− and a pixel voltage (VPIX+) associated with the LCoS display. The system also includes a second low voltage amplifier configured to generate the pixel voltage VPIX+. Further, a common electrode circuit may be coupled to the first low voltage amplifier and the second low voltage amplifier to generate a common electrode voltage based upon the predetermined voltage and the pixel voltage. In an embodiment, one or both amplifiers are considered as part of the circuit. In particular, a control circuit may be coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit may selectively control the common electrode circuit to generate a high common electrode voltage based upon a sum of the predetermined voltage and the pixel voltage. In an embodiment, the second phase may occur before the first phase.
In some embodiments, a method for establishing a common electrode drive voltage for an LCoS display, having transistors with lower breakdown voltage is provided. The method may include generating a predetermined voltage for setting the common electrode voltage in comparison to ground and a pixel voltage VPIX associated with the LCoS display. The method may further include charging, intermittently, a first capacitor and a second capacitor during a first phase and a second phase to the predetermined voltage, respectively. During the first phase, the method may further include coupling the second capacitor across a common electrode node and ground to produce a low common electrode voltage less than ground by the predetermined voltage. During a second phase, the method may further include coupling the first capacitor across a pixel voltage node and the common electrode node to produce a high common electrode voltage greater than the pixel voltage by the predetermined voltage.
In an embodiment, a display system for displaying an image comprising: a display panel having a plurality of pixels, each of the plurality of pixels having a pixel electrode voltage (VPEV), and a common electrode voltage (VCOM); and a digital drive device coupled to the display panel comprising: a bit plane memory for providing the VPEV to each of the plurality of pixels; a common electrode circuit coupled to the display panel for providing the VCOM; and at least one first amplifier coupled to the display panel configured to generate a maximum pixel voltage (VPIX+) and a minimum pixel voltage (VPIX−); wherein the VPEV switches from VPIX+ to VPIX− according to a voltage received by at least one of the plurality of pixels from the bit plane memory, wherein the common electrode circuit further comprises at least one second amplifier configured to generate a predetermined voltage VDAC_COM, and wherein a value of VCOM switches between I) VPIX− minus VDAC_COM; and ii) VPIX+ plus VDAC_COM.
In an embodiment, VPIX+ has a value in the range of 1.2V-4V, and VPIX− has a value in the range of 0V to −2.8V. In an embodiment, the display system of claim 1, wherein VDAC_COM has a value in the range of approximately 0-2V In an embodiment, the display system of claim 1, wherein the common electrode voltage VCOM maintains DC voltage balance across the display panel. In an embodiment, the display panel is a liquid crystal display panel.
In an embodiment, the display system further comprises a control circuit coupled to the common electrode circuit for supplying a clocking output CS to the common electrode circuit. In an embodiment, the common electrode circuit further comprises a plurality of switches that receive the clocking output CS. In an embodiment, at least one of the plurality of switches includes a plurality of MOSFET transistors. In an embodiment, the common electrode circuit is located on a separate integrated circuit chip from the display panel. In an embodiment, the common electrode circuit is integrated into the same integrated circuit chip as the display panel.
In an embodiment, VPIX− is zero, and a value of VCOM varies between less than VPIX− (e.g., 0V) and greater than VPIX+. The embodiments herein have the advantage of enabling this VCOM voltage swing at lower cost, lower power, smaller size and higher integration relative to known systems. In an embodiment, a method of generating a common electrode drive voltage VCOM for a display panel having a plurality of pixels with a pixel voltage VPIX, is provided. In an embodiment, the method comprises the steps of: coupling a common electrode circuit having at least one first capacitor and at least one second capacitor to the display panel; selectively controlling the common electrode circuit with the control circuit, during a first phase, to generate a low value of VCOM based upon a negative value of a predetermined voltage VDAC_COM; and selectively controlling the common electrode circuit using the control circuit during a second phase, to generate a high value of VCOM; coupling at least one first amplifier to the display panel configured to generate a maximum pixel voltage (VPIX+) and a minimum pixel voltage (VPIX−); wherein a value of VCOM switches between a) VPIX− minus VDAC_COM; and ii) VPIX+ plus VDAC_COM. In an embodiment, the method further comprises the step of charging the at least one first capacitor and the at least one second capacitor within the common electrode circuit to the predetermined voltage VDAC_COM.
In an embodiment, the method further comprises the step of coupling at least one second amplifier to the common electrode circuit configured to generate the predetermined voltage VDAC_COM. In an embodiment, VPIX+ has a value in the range of 1.2V-4V, and VPIX− has a value in the range of 0V to −2.8V. In an embodiment, VDAC_COM has a value in the range of 0-2V. In an embodiment, a value of VCOM maintains DC voltage balance across the display panel (i.e. 0V). In an embodiment, the display system is an LCoS display system.
Other aspects and advantages of the embodiments will become apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of the described embodiments.
The described embodiments and the advantages thereof may best be understood by reference to the following description taken in conjunction with the accompanying drawings. These drawings in no way limit any changes in form and detail that may be made to the described embodiments by one so skilled in the art without departing from the spirit and scope of the described embodiments.
The following embodiments describe a display system (e.g., LCoS display system), associated circuitry, and method for common electrode voltage generation. It can be appreciated by one skilled in the art, that the embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the embodiments.
In some embodiments, the display system is an LCoS display system and may include a circuit for common electrode voltage VCOM generation having a first low voltage amplifier configured to generate a predetermined voltage to be implemented for setting the common electrode voltage VCOM to a value relative to ground and to the pixel voltage VPIX associated with the LCoS display. The system also includes a second low voltage amplifier configured to generate the pixel voltage VPIX. Further, a common electrode circuit may be coupled to the first low voltage amplifier and the second low voltage amplifier to generate a common electrode voltage based upon the predetermined voltage and the pixel voltage VPIX. In particular, a control circuit may be coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit may selectively control the common electrode circuit to generate a high common electrode voltage based upon a sum of the predetermined voltage and the pixel voltage VPIX. The common electrode voltage VCOM generated according to the embodiments herein maintain a voltage (e.g. DC voltage) balance of approximately 0V across the liquid crystal display panel of the LCoS display systems of the present invention.
The method of generating the common electrode voltage VCOM may include generating the predetermined voltage relative to the pixel voltage VPIX associated with the LCoS display and charging, intermittently, a first capacitor and a second capacitor during a first phase and a second phase to the predetermined voltage, respectively. In particular, during the first phase, the method can include coupling the second capacitor across a common electrode node and ground to produce a low common electrode voltage that is less than ground by the predetermined voltage. During a second phase, the method may further include coupling the first capacitor across a pixel voltage node and the common electrode node to produce a high common electrode voltage that is greater than the pixel voltage VPIX by the predetermined voltage.
Advantageously, the system, circuit, and method of implementing a low power common electrode voltage described herein can be used for the implementation of the common electrode voltage, VCOM, for LCoS imagers/back planes employing transistors having lower breakdown voltage than those that are known and currently utilized within displays (e.g., LCoS displays). The common electrode voltage generation process and/or the common electrode circuit may be implemented on an integrated circuit, by itself, or alternatively as part of another integrated circuit, such as that of a display panel or imager. The embodiments of the present invention reduce the required breakdown voltage of the transistors needed for implementation of the common electrode drive voltage relative to known systems. The common electrode voltage generation circuit and method described herein also lowers the cost of the circuitry implementation due to the reduced die size required. Further, the system and method disclosed herein may increase the level of integration when integrated on the same die as the LCoS backplane/display. In an embodiment the VCOM circuit is integrated on a separate die from the display or integrated with other analog functions (e.g., temperature sensing, optical feedback etc.). As such, the VCOM generation circuit (all or portions of which may be referred to herein as the common electrode circuit) may be integrated with a backplane chip of the LCoS display system or alternatively located on a separate chip that is electrically connected to the backplane chip. Embodiments of a display system (e.g. LCoS display system), in accordance with the present invention, also consume less power, making it more suitable for battery operation, and thereby producing less heat. The smaller supply voltage results in lower power dissipation. In an embodiment of the present invention, the power dissipation is reduced by employing an amplifier that runs from a power supply voltage that is approximately half or less than a value of approximately 9-10V. Prior art circuitry typically dissipates approximately 25 mW, while some embodiments of the present invention have the benefit and advantage of dissipating only approximately 5 mW.
In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The phrase “in one embodiment” located in various places in this description does not necessarily refer to the same embodiment. Like reference numbers signify like elements throughout the description of the figures.
Referring to
In an embodiment of the present invention, the graphics processing device 10 includes a processor 30, or is associated with a processor 30. The processor 30 may be internal or external to the graphics processing device 10. In an embodiment of the present invention, the processor 30 may execute software modules, programs or instructions of the graphics processing device 10. For example, the processor 30 may execute software modules such as a dither module 33, a checkboard module 34, and a command stiffer 37. In execution of the aforementioned modules, the processor 30 may access data stored on one or more look-up tables (LUTs) (e.g., a color LUT 32 and a bit plane LUT 35). While illustrated as separate from the processor in
In an embodiment of the present invention, the spatial and temporal dither module 33, in accordance with the present invention, may be used to perceptually extend bit depth beyond the native display bit depth. The dither module 33 may be utilized, for example, in recovering fast moving scenes by exploiting high speed illumination “dithering” digital light processing (DLP) projectors. The checkerboard 34 module may perform a checkerboarding method in accordance with the present invention. It would be recognized by one of skill in the art that more or fewer modules may be executed by the processor 30 without departing from the scope of the invention.
In an embodiment of the present invention, bit rotation occurs via a bit rotation module 15. The bit rotation module 15 and associated processes may involve extracting a specific bit number, for example the most significant bit (MSB) by a processor (e.g., processor The resulting bit planes are used as the input of the bit plane and/or stored in the Bit Plane LUT(s) 35. In an embodiment of the present invention, the bit plane LUT 35 is accessed from the memory 21 of the graphics processing device 10 and the processor 30 accesses the bit plane LUT 35 (i.e., an instantaneous state of all output binary pixel electrode logic of the spatial light modulator 56, within optical engine 50, given each pixel's digital level value and the time). In an embodiment of the present invention, the processor 30 may execute a module (e.g., bit plane LUTs 35) that generates bit planes. In an embodiment of the present invention, the bit plane LUTs 35 may be located in the graphic processing device 10 as shown in
The digital drive device 40 receives data (e.g., commands 36, 38) from the graphics processing device 10 and arranges (e.g., compresses) the received data prior to communicating image data to the optical engine 50. The digital drive device 40 may include a memory 41 (which may be internal or external to the device and/or shared with another device). The digital drive device 40 may include various programs, for example, a command parser module 44 that, when executed by the processor 30, parses and/or processes data received by the digital drive device 40. The digital drive device 40 may include static and/or dynamic data (e.g., bit plane memory 42, command parser 44, light control source 46, etc.) In an embodiment of the present invention, the command stuffer 37 inserts commands in the video path in areas not seen by the end user. In an embodiment of the present invention, these commands control, for example, light source(s) 52 such as laser(s), drive voltages (e.g., such as VCOM and VPIX) directly, or indirectly via, for example, the Light Source Control module 46 and the VCOM+VPIX Control module 48. In an embodiment of the present invention, the Light Source Control module 46 and VCOM+VPIX Control module 48 may be implemented in hardware and/or software. The digital drive device 40 may be, for example, a component of a computing system, head mounted device, and/or other device utilizing an LCoS display.
In an embodiment, the digital drive device 40 also includes a command parser 44. The command parser 44 parses the commands 38 received from the command stuffer 37. In an embodiment of the present invention, a Light Source Control 46 controls the light source(s) 52 such as lasers or LEDs by controlling analog inputs (e.g., voltages or currents) via DACs, digital enable or disable controls, etc. In an embodiment, the VCOM+VPIX Control module 48 controls the VCOM and VPIX voltages. In an embodiment of the present invention, the optical engine 50 contains the display components and all other optical devices required to complete the display system 2 illustrated in
In an embodiment of the present invention, the control circuits 110, 210, common electrode circuits 150a, 150b, and 250, and associated amplifiers illustrated in
More specifically, in an embodiment, the command parser 44 provides individual voltage inputs to components 116 and 118 as well as control circuit 110. These inputs are digital control inputs (i.e., voltages, logic levels). The voltage input supplied by the command parser 44 to component 116 (e.g., DAC) represents a digital word corresponding to the desired input voltage to amplifier 106. This output of component 116 is amplified by amplifier 106 and produces voltage VPIX+. The voltage input supplied by the command parser 44 to component 118 (e.g. DAC) represents a digital word corresponding to the required input voltage to amplifier 108. The output of component 118 is amplified by amplifier 108 and produces VDAC_COM. The voltage input supplied by the command parser 44 to the control circuit 110 represents one or more logic level inputs that establish the frequency, duty cycle and phase of control output CS. The output of the control circuit 110 is clock output CS.
Referring to
A pixel electrode voltage VPEV is a value of the pixel electrode of each of the plurality of pixels within the display panel 180. In an embodiment, the pixel electrode voltage VPEV switches from VPIX− to VPIX+ according to the value of the data (e.g., data bit) for each pixel within the display panel 180 that is received from the bit plane memory 42 within the digital drive device 40. There is a plurality of pixels (e.g. pixel 186a-n) in the display panel 180 as shown in
The control circuit 110 may be located, for example, on an integrated circuit within a backplane chip of the display panel 180 of the system 100. Alternatively, the control circuit may be located on a separate chip that is electrically connected to the common electrode circuit 150a. The control circuit 110 may include an arrangement including at least one flip-flop device 112 configured to provide (e.g., transmitted via a bus) a clocked control output CS to the common electrode circuit 150a. In some embodiments, the control circuit 150a may include a flip-flop 112 coupled to a buffer 114 to provide a first and a second control output (not shown), wherein the second control output is delayed with respect to the first for the purpose of staggering the ON and OFF switching of the switches within the common electrode circuit 150a. Accordingly, non-overlapping control outputs (i.e., the control output CS is either on or off) may be implemented.
The second low voltage amplifier 106 may be used for generation of the pixel voltage VPIX+. The value of VPIX+ may change dynamically based upon the color sequence output from the bit plane memory 42 in conjunction with command parser 44 corresponding to the display colors and intensity of the image to be displayed by the plurality of pixels of display panel 180. In contrast, the first low voltage amplifier 108 (where “low voltage” represents amplifiers operating at, for example, approximately 5V or less) may be used to generate a voltage VDAC_COM. In an embodiment of the present invention, voltage VDAC_COM is a predetermined voltage, that is achieved at the output by amplifier 108. The voltage input supplied to component 118 (e.g. Digital to Analog Converter (DAC) to achieve voltage VDAC_COM (i.e., a voltage that will be used to establish VCOM) is obtained from the command parser 44. Voltage VDAC_COM is relatively small in comparison to the pixel electrode voltage swing (VPIX+ to VPIX−) of the display panel. This predetermined voltage VDAC_COM is programmable by adjusting the input supplied by component 118 from the command parser 44 and can be used to charge the first and the second capacitors (C1, C2) of the common electrode circuit 150a alternatively, during a first and second respective phase (as will be described below).
In an embodiment, the low power amplifier 108 may be implemented using a 5 mW operational amplifier, where the pixel voltage VPIX+ is 4.0V and the predetermined voltage VDAC_COM is 1.5V. The value of the predetermined voltage VDAC_COM may be selected as a function of the requirements of the liquid crystal material and desired application of the display system (e.g., amplitude and/or phase properties). As such, the range/span and step size of the positive pixel voltage VPIX+ and the common electrode voltage VCOM may be varied. In some embodiments, the step size of the pixel voltage VPIX and the common electrode voltage VCOM may be increased by 2×, eliminating 1 bit from each DAC, as DACs have a range/span and a step size, where the number of bits is log 2 of the range divided by the step size.
In some embodiments, the common electrode circuit 150a may use the output voltage of the first low voltage amplifier 108 and the second low voltage amplifier 106 to generate a common electrode voltage VCOM based upon the predetermined voltage VDAC_COM and the pixel electrode voltages VPIX+ and VPIX−. In particular, the control circuit 110 may be coupled to the common electrode circuit 150a, wherein, during a first phase, the control circuit 110 can selectively control the common electrode circuit 150a to generate a low common voltage V−COM based upon a negative value of the predetermined voltage VDAC_COM. And the pixel electrode voltage VPIX−. Further, during a second phase, the control circuit 110 may selectively control the common electrode circuit 150a to generate a high common voltage V+COM based upon a sum of the predetermined voltage VDAC_COM and the pixel voltage VPIX.
In particular, the common electrode circuit 150a may include a pair of switches (S1 and S2) coupled across a first capacitor C1 to couple the first capacitor C1 across ground and the output of the first amplifier 108 for charging the capacitor C1 to the predetermined voltage VDAC_COM, in some embodiments. In the alternative, the pair of switches (S1 and S2) may couple the first capacitor C1 across the output of the second amplifier 106 and the common electrode node VCOM to provide the high or maximum common electrode voltage value (V+COM).
Further, the common electrode circuit 150a may include a second pair of switches (S3 and S4) coupled across a second capacitor C2 to couple the second capacitor C2 across ground and the output of the first amplifier 108 for charging the capacitor C2 to the predetermined voltage VDAC_COM. In the alternative, the pair of switches (S3 and S4) may couple the second capacitor C2 across the common electrode node VCOM and ground to provide the low common voltage V−COM.
In operation, the control circuit 110 provides the control output CS selectively toggles the first and second pair of switches (S1-S4) and provides two phases of operation. In particular, during the first phase, a clocking control output CS from control circuit 110 can toggle the first pair of switches S1 and S2 and couple the first capacitor C1 across ground and the output of the first amplifier 108 to charge the capacitor C1 to the predetermined voltage VDAC_COM. For example, if the predetermined voltage VDAC_COM is set to 0.8V, the capacitor C1 will be charged to 0.8V. During the first phase, the clocking control output CS from control circuit 110 may, simultaneously, toggle the second pair of switches S3 and S4 to couple the second capacitor C2 across the common electrode node VCOM and ground. As a result, the common electrode node VCOM is supplied with the low common voltage V−COM, where the voltage is set to −VDAC_COM when the second capacitor has been initially charged in a previous cycle. Following the same example, the low common voltage V−COM can be set to −0.8V.
In operation, during the second phase, the clocking control output CS from control circuit 110 can toggle the first pair of switches S1 and S2 to couple the first capacitor C1 across the output of the second amplifier 106 and the common electrode node VCOM. As a result, the common voltage node is set to the high common voltage V+COM, voltage V+COM is the sum of the pixel voltage VPIX+ and the predetermined voltage VDAC_COM. For example, if the predetermined voltage VDAC_COM is set to 0.8V, the high common voltage V+COM will be the sum of VPIX++0.8V. Simultaneously, during the second phase, the clocking control output CS from control circuit 110 can toggle the second pair of switches S3 and S4 to couple the second capacitor C2 across ground and the output of the first amplifier 108. Accordingly, the second capacitor C2 is charged to the output voltage VDAC_COM of the first amplifier 108. For example, when the predetermined voltage VDAC_COM is set to 0.8V, the second capacitor C2 is charged to 0.8 V. In an embodiment, the voltages used to charge C1 and C2 are different, and in an embodiment the voltages used are approximately the same.
In some embodiments, an example of an implementation may include the pixel voltage VPIX+ to set to be between and including 2.8 V and 4.336V, where the voltage can be implemented using a 7-bit DAC with a 12 mV step-size. It should be noted that this example is not meant to be limiting to the inventive concept. The range/number of bits and the step size can be larger or smaller. In an embodiment of the present invention, less hardware is utilized and the manufacturing cost of a system or device, in accordance with the present invention, is less when the number of bits utilized is reduced. In an embodiment of the present invention, the voltage VDAC_COM generated by low voltage amplifier 108 may be, for example, between and including 0.8 V and 2.08V; where the voltage may be implemented using a 7-bit DAC with a 10 mV step-size. Ultimately, the high common electrode voltage V+COM provided may be from (VPIX++0.8V) to (VPIX++2.08V), where the voltage can be implemented, for example, using a 7-bit DAC with a 10 mV step-size. Accordingly, the low common electrode voltage V−COM generated may be from and including −2.08V to −0.8V. However, it should be understood by one of ordinary skill in the art that the number of bits of the DAC, the minimum and maximum values of DAC voltages (range/span) and the step size may vary. It should also be understood by one of ordinary skill in the art that in an embodiment, the operational amplifier 108 may not be coupled to a DAC. These examples are presented to illustrate embodiments of the present invention. However, it should be recognized that the invention is not limited to these examples or embodiments described and can be practiced with modification and alteration within the spirit and scope of the invention.
Referring to
Further, the source of the second transistor T2 may couple to ground, while the drain of transistor T2 couples to the capacitor C1. The source of transistor T3 may couple to receive the predetermined voltage (i.e., the output voltage of the first operational amplifier) VDAC_COM, while the source of transistor T4 may couple to the common electrode node VCOM. Both drains of transistors T3 and T4 may couple to the first capacitor C1, in some embodiments.
Similarly, the pair of switches S3 and S4 may be derived from MOSFET transistors T5-T8. A n-type transistor T5 and a p-type transistor T6 may have their gates coupled to receive the control output CS. The control output CS will effectively turn each one of the transistors (T5, T6) ON and OFF. In some embodiments, the source of transistor T5 may couple to the common electrode node VCOM, while the drain of transistor T5 couples to the second capacitor C2. Further, the source of the transistor T6 may couple to ground, while the drain of transistor T6 couples to the capacitor C2. The source of transistor T7 may couple to receive the predetermined voltage VDAC_COM, while the source of transistor T8 may couple to ground. Both drains of transistors T7 and T8 may couple to the second capacitor C2, in some embodiments. In some embodiments, each one of the transistor pairs implementing a switch (S1-S4) can be represented by more than one transistor coupled in series (not shown). Note, series transistors form a switch that may share/accommodate a larger voltage.
In operation, during a first phase when the control output is high, all of the n-type transistors T2, T3, T5, and T8 turn ON. As will be described in more detail below, the result of these transistors turning on leads to connecting the first capacitor C1 across ground and the predetermined voltage VDAC_COM, while the second capacitor C2 is coupled across the common electrode node VCOM and ground. During the second phase when the control output is low, the p-type transistors (T1, T4, T6, and T7) turn ON. As a result, the first capacitor C1 is coupled across the pixel voltage node VPIX and the common electrode node VCOM, while the second capacitor C2 is coupled across ground and the predetermined voltage VDAC_COM.
During the second phase when the control output CS is low, the p-type transistor T1 will turn ON, effectively connecting the circuit from the pixel voltage node VPIX+ to the first capacitor C1. Simultaneously, when the Control output CS is low, the n-type transistor T2 to will turn OFF, effectively opening the circuit from the node connecting the drain a transistor T2 to ground. That is, when the control output CS is low, the capacitor C1 will be coupled to the node having the pixel voltage VPIX.
In the alternative during the first phase when the control output CS is high, the p-type transistor T1 will turn OFF, effectively opening the circuit between the node containing the pixel voltage and the drain of the first Transistor T1. Simultaneously, as a result of a high control output CS, the n type transistor T2 will turn ON, effectively coupling the drain of transistor T2 to ground. That is, when the control output CS is high, the capacitor C1 will be coupled to ground. Thereby, the switch implementation using the MOSFET transistors effectively couples the first capacitor C1 to either ground/VPIX− or the pixel voltage node VPIX.
For the second switch S2, the implementation using MOSFET transistors is reversed. Switch S2 is implemented using an n-type transistor T3 and a p-type transistor T4, where the gates of the transistors couple to clocking control output CS to turn these transistors ON and OFF. In particular as noted above, the source of the n-type transistor T3 couples to the output of the first amplifier 108, while the source of the p-type transistor T4 couples to the common electrode node VCOM. Both drains of transistors T3 and T4 couple to the first capacitor C1. In operation, during the second phase when the control output CS is low, the n-type transistor 13 will turn OFF, effectively opening the circuit from the output of the first amplifier 108 to the first capacitor C1. Simultaneously, when the control output CS is low, the p-type transistor T4 to will turn ON, effectively shorting the circuit from the node connecting the capacitor C1 and the common electrode node VCOM. That is, when the control output CS is low, the capacitor C1 will be coupled to the common electrode node VCOM.
In the alternative, during the first phase when the control output CS is high, the n-type transistor T3 will turn ON, effectively shorting the circuit between the output node of amplifier 108 and the capacitor C1, thereby coupling capacitor C1 to the predetermined voltage VDAC_COM. Simultaneously, as a result of a high control output CS, the p-type transistor T4 will turn OFF, effectively opening the circuit between the drain of transistor T4 to the common electrode node VCOM. That is, when the control output CS is high, the capacitor C1 will be coupled to receive the predetermined voltage VDAC_COM. Thereby, the switch implementation for switches S1 and S2 using the MOSFET transistors (T1-T4) effectively couples the first capacitor to either across the pixel voltage node and the common electrode node VCOM or across ground and the node having the predetermined voltage VDAC_COM.
Similarly, the pair of switches S3 and S4 may be derived from MOSFET transistors T5-T8. During the second phase when the control output CS is low, the transistors T5-T8 will switch ON and OFF to couple the capacitor C2 across ground and the output node having predetermined voltage VDAC_COM, effectively charging capacitor C2 to the predetermined voltage VDAC_COM. Conversely, during the first phase when the control output CS is high, the switch transistors T5-T8 will switch from ON to OFF to couple the capacitor C2 across the common electrode node VCOM and ground, applying the negative value of the predetermined voltage VDAC_COM at the common electrode node VCOM (as explained in detail with reference to
In an embodiment, the implementation of MOSFET transistors (T1-T8) as switches (S1-S4) has the benefit and advantage of reducing the overhead voltage required. In a conventional implementation however, it takes approximately +/−1V of extra supply voltage above and below V+COM and V−COM, respectively. It is noted that the supply voltage may be selected to ensure correct operation for all possible supply voltage values. Further, in an embodiment of the present invention, the maximum voltage any one of switch transistors S1-S4 experiences appears to be about or equal to 6V or 7V for VCOM=−1V to 5V or −1.5V to 5.5V, respectively. Additionally, negative voltage V−COM can be approximately −1.5V, which requires that switch transistors S1-S4 (e.g., digital transistors) are isolated from ground and that they are also isolated from −1.5V as well.
A display system (e.g., system 100), in accordance with the present invention, for generating a common electrode voltage VCOM, lowering the required breakdown voltage of the transistors used to implement the common electrode voltage VCOM and lowers the power dissipation of the common electrode voltage VCOM circuitry. The lower breakdown voltage effectively reduces the die area because the transistors are smaller. Additionally, the lower breakdown voltage may allow the integration of common electrode voltage VCOM on a future scaled node for size, power, and/or cost savings.
In a known system, the breakdown voltage of the common electrode voltage VCOM transistors of a common electrode circuit is 20V, and the power dissipation of the VCOM amplifier is 20-30 mW. However, the system, circuits and methods of high (V+COM) and low (V−COM) common electrode voltage generation disclosed herein have the benefit and advantage of using a lower voltage amplifier (e.g., amplifier 108), that can be employed to create the common electrode voltage VCOM by establishing the voltages on the first and second capacitors (C1, C2), which get connected either to ground (or VPIX−) for the low common electrode voltage V−COM or to the pixel voltage VPIX+ for the high common electrode voltage V+COM. In an embodiment, the lower voltage amplifier 108 may have an output value in the range of e.g., 0V-1.6V. In an embodiment, the supply voltage for the amplifier 108 to create such a lower voltage may be in the range of e.g., 3.3.-5V. Accordingly, during operation, one of the capacitors (C1, C2) may establish either high common electrode voltage V+COM or the low common electrode voltage V−COM, while the other is being charged and/or replenished. Accordingly, the charging of the capacitors are swapped/switched/changed using switches S1-S4. Amplifier 108
As an added benefit, the common electrode circuits (e.g., 150a, 150b, 250) of the embodiments of the display systems (e.g. system 100, 200) generates the common electrode voltage VCOM and requires a reduced power supply (e.g., approximately 5V) in comparison to the conventional displays that require a large power supply (e.g., approximately 9-10V). In addition, in an embodiment of the present invention, amplifier 108 operates at a lower current of approximately ˜1 mA (versus ˜2-3 mA on conventional systems) and is capable of lowering the power from, for example, about 20-30 mW to approximately 5 mW. A further benefit of this system and method of common electrode voltage generation disclosed herein is that it reduces or eliminates the need for an external power supply voltage and their associated regulator circuitry. As a result, the cost for a device application and/or display system in accordance with the present invention, is lowered; and the size/area and power are reduced.
In some embodiments, because of charge sharing between the first and second capacitors (C1, C2) and the common VCOM capacitance, capacitors C1 and C2 may be approximately, between and including, 0.1 uF to 10 uF in value. In an embodiment of the present invention, capacitors C1 and C2 may be approximately 1 uF in value. This may result in the deviation of the common electrode voltage VCOM from its programmed/desired voltage of about 5-10 mV. In some embodiments, this result may be ignored if sufficiently small. In other embodiments, the effect of this result can be reduced by using larger capacitors to implement capacitors C1 and C2, for example, C1 and C2 may have between and including 2-5 uF. In an embodiment of the present invention, the VCOM deviation may be compensated for by programming the voltage on the capacitors (C1, C2) to be somewhat larger or smaller than the final desired value of the common electrode voltage VCOM, for example, by 1-10 mV.
The foregoing example shown in
Referring to
In the alternative, when the control output CS is low during the second phase, p-type transistors T1, T4, T6, T7 are ON, while the n-type transistors T2, T3, T5, and T8 are OFF. This means that during the second phase switches S1 and S2 toggle to couple the first capacitor C1 between the pixel voltage node VPIX and the common electrode node VCOM, effectively supplying a voltage sum of the pixel voltage VPIX and the predetermined voltage VDAC_COM at the common electrode node VCOM. At the same time, switches S3 and S4 couple the second capacitor C2 across ground and output node having the predetermined voltage VDAC_COM, effectively charging the second capacitor C2 to the predetermined voltage VDAC_COM. Accordingly, during this second phase, the voltage at common electrode node VCOM is equal to the sum the pixel voltage VPIX and the predetermined voltage VDAC_COM As shown in the timing diagram of
Referring to
A preferred voltage difference between the common electrode voltage VCOM and the pixel voltage VPIX can be close to zero, in some embodiments. Alternatively, the pixel voltage VPIX can be 1.5V to 4.5V, possessing a non-uniform duty cycle for color sequential (time multiplexed applications), such as the Red Green Blue (RGB) color model. In an embodiment of the present invention, the polarities of the voltages may be inverted. In an embodiment of the present invention, the power supply may be, for example, Vdd and function as a positive ground, and the VPIX may have a negative voltage value. For example, in an embodiment of the present invention, Vdd is 1.2 V and VPIX is −2.8 V. It should be understood by one of ordinary skill in the art that the voltage values may vary.
Referring to
As similarly discussed with respect to
The voltage input supplied by the command parser 44 to component 218 (e.g. DAC) represents a digital word corresponding to the required input voltage to amplifier 208. The output of component 218 is amplified by amplifier 208 and produces VDAC_COM. The voltage input supplied by the command parser 44 to the control circuit 210 represents one or more logic level inputs that establish the frequency, duty cycle and phase of control output CS. The output of the control circuit 210 is control output CS.
Similar to the first embodiment, the control circuit 210 may include an arrangement including a flip-flop device 212 coupled to provide at least one clocking control output CS. In some embodiments, the control circuit 210 may include a flip-flop 212 coupled to a buffer 214 to provide a first and second clocking control output, wherein the second clocking control output is delayed with respect to the first such that the timing for the turning the transistors ON and OFF overlaps during a first and second phase. The second low voltage amplifier 206 may be used for generation of the pixel voltage VPIX, while the first low voltage amplifier 208 may be used to generate a predetermined voltage VDAC_COM that is relatively small in comparison to the pixel voltage VPIX of the LCoS display panel 280. For example, the low power amplifier 208 may be implemented using a 1-5 mW operational amplifier, where the pixel voltage VPIX is 4.0V and the predetermined voltage VDAC_COM is 1.6V.
In some embodiments, the common electrode circuit 250 may use the output voltage of the first low voltage amplifier 208 and the second low voltage amplifier 206 to generate a common electrode voltage VCOM based upon the predetermined voltage VDAC_COM and the pixel voltage VPIX. In particular, a control circuit 210 may be coupled to the common electrode circuit 250, wherein, during a first phase, the control circuit 210 can selectively control the common electrode circuit 250 to generate a low common voltage V−COM based upon a negative value of a voltage determined by the voltage divider network implemented using resistors R1, R2, and RDAC, where resistor RDAC is a variable resistor that can be used to add a predetermined offset. Further, during a second phase, the control circuit 210 may selectively control the common electrode circuit 250 to generate a high common voltage V+COM based upon a sum of the predetermined voltage VDAC_COM, the pixel voltage VPIX, and the voltage from the voltage divider network of resistors R1, R2, and RDAC
In some embodiments, the common electrode circuit 250 may include a pair of switches (S5 and S6) coupled across a first capacitor C3 to couple the first capacitor C3 across ground and the output of the first amplifier 208. In the alternative, the pair of switches (S5 and S6) may couple the first capacitor C3 across the output of the second amplifier 206 and the common electrode node VCOMPP. Further, the common electrode circuit 250 may include another switch S7 coupled across the common electrode node VCOMPP and ground. As noted above, the variable resistor RDAC may be used to offset the DAC for mismatch and/or DBR/work function. In particular, the resistors R1, R2, and RDAC implement a voltage divider network, where the common electrode voltage VCOM may be approximately (VPIX/2)(1±α), where α represents an adjustment for offset correction added using the variable resistor RDAC.
In operation, the control circuit 210 provides a clocked control output CS that selectively toggles switches S5-S7 to provide two phases of operation. In particular, during the first phase, a control output CS from control circuit 210 can toggle the first pair of switches S5 and S6 to couple the first capacitor C3 across ground and the output of the first amplifier 208 to charge the capacitor C3 to the predetermined voltage VDAC_COM. For example, if the predetermined voltage VDAC_COM is set to 1.6V, the capacitor will be charged to 1.6V. Simultaneously during the first phase, the control output CS from control circuit 210 can toggle switch S7 to couple the second capacitor C4 across the common electrode node VCOM and ground. As a result, the common electrode node VCOM is supplied with charged voltage of the second capacitor C4, which is the voltage supplied by the voltage divider network of resistors R1, R2, and RDAC.
During the second phase, the control output CS from control circuit 210 can toggle the first pair of switches S5 and S6 to couple the first capacitor C3 across the output of the second amplifier 206 (VPIX) and the preliminary common electrode node VCOMPP. As a result, the preliminary common voltage node VCOMPP is set to the high common voltage V+COM, where the voltage V+COM is the sum of voltages VPIX and VDAC_COM.
Simultaneously, during the second phase, the clocking control output CS from control circuit 210 can toggle switch S7 to open the circuit, effectively setting the common electrode voltage node VCOM to be set to the sum of the voltages at the preliminary common voltage node VCOMPP and the voltage supplied by the voltage divider network of resistors R1, R2, and RDAC, which is approximately (VPIX/2)(1±α).
Referring to
Referring again to
In an embodiment, the common electrode circuit 250 of the system 200 may pre-charge lower capacitor C4 to approximately −VDAC_COM/2. In the alternative, additional resistors (not shown) may be used to feed the lower capacitor C4 the common electrode voltage VCOM to increase the discharging time constant and reduce VCOM drop. In an embodiment, e.g., as illustrated in
Referring to
In a decision action 325, a determination is made with regards to whether the process has entered the first phase. For example, a control circuit may send control outputs to toggle select switches in an arrangement coupling the capacitors across specific nodes for a first phase operation. If the first phase has entered, in an action 330 the method 300 includes charging the first capacitor to the predetermined voltage. For example, the first capacitor C1 may be charged to the predetermined voltage VDAC_COM.
Additionally, the method 300 may include coupling the second capacitor across ground GND and the common electrode VCOM to produce a common electrode voltage less than 0 V (V−COM), in an action 340. If the method 300 is not in the first phase, in an action 327 it is a known determination that the process has entered the second phase. When the second phase has been entered, in an action 350 the method 300 may include charging the second capacitor to the predetermined voltage. Additionally, the method 300 may include coupling the first capacitor across the pixel voltage node VPIX and the common electrode VCOM to produce a common electrode voltage greater than the pixel voltage (V+COM), in an action 360. At the end of actions 330, 340, 350, and 360, the process loops back to the decision action 325 in an effort to intermittently charge and connect the capacitors to provide at the common electrode node the high common electrode voltage V+COM and the low common electrode voltage V−COM during the two respective phases.
The foregoing description, for the purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the systems and methods to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the embodiments and its practical applications, to thereby enable others skilled in the art to best utilize the embodiments and various modifications as may be suited to the particular use contemplated. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein and may be modified within the scope and equivalents of the appended claims.
Particularly in the above description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
Further, many other embodiments can be apparent to those of skill in the art upon reading and understanding the above description. Although the present invention has been described with reference to specific exemplary embodiments, it will be recognized that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the disclosure. Embodiments maybe embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense.
It should be understood that although the terms first, second, etc. may be used herein to describe various steps or calculations, these steps or calculations should not be limited by these terms. These terms are only used to distinguish one step or calculation from another. For example, a first calculation could be termed a second calculation, and, similarly, a second step could be termed a first step, without departing from the scope of this disclosure. As used herein, the term “and/or” and the “I” symbol includes any and all combinations of one or more of the associated listed items. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Therefore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Further, although the method operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or the described operations may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing.
Various units, circuits, or other components may be described or claimed as “configured to” perform a task or tasks. In such contexts, the phrase “configured to” is used to so connote structure by indicating that the units/circuits/components include structure (e.g., circuitry) that performs the task or tasks during operation. As such, the unit/circuit/component can be said to be configured to perform the task even when the specified unit/circuit/component is not currently operational (e.g., is not on). The units/circuits/components used with the “configured to” language include hardware; for example, circuits, memory storing program instructions executable to implement the operation, etc. Reciting that a unit/circuit/component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. 112, sixth paragraph, for that unit/circuit/component. Additionally, “configured to” can include generic structure (e.g., generic circuitry) that is manipulated by software and/or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in manner that is capable of performing the task(s) at issue. “Configured to” may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks.
This application is a continuation of U.S. application Ser. No. 17/991,508, filed Nov. 21, 2022, which application is a continuation of U.S. application Ser. No. 17/413,621, filed Jun. 14, 2021, now issued as U.S. Pat. No. 11,580,927, which application is a U.S. National Stage Filing under 35 U.S.C. 371 from International Application No. PCT/US2020/040468, filed on Jul. 1, 2020, and published as WO2021/003253 on Jan. 7, 2021, which application claims priority to U.S. provisional application Ser. No. 62/869,432 filed on Jul. 1, 2019, all of which are incorporated herein by reference in their entirety.
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| 20230079962 | Taylor | Mar 2023 | A1 |
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| Number | Date | Country | |
|---|---|---|---|
| 20230395037 A1 | Dec 2023 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62869432 | Jul 2019 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17991508 | Nov 2022 | US |
| Child | 18450811 | US | |
| Parent | 17413621 | US | |
| Child | 17991508 | US |
