Patent Application
20070268833
Exemplary embodiments of the invention will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. Understanding that these drawings depict only exemplary embodiments and are, therefore, not to be considered limiting of the invention's scope, the exemplary embodiments of the invention will be described with additional specificity and detail through use of the accompanying drawings in which:
A method for measuring two or more input signals using a single-input measuring device is described. Test equipment that comprises a single-input measuring device is provided. A first input is received. A second input is received. The second input is delayed by a time delay T to provide a delayed second input. The first input and the delayed second input are combined to provide a combined input signal. The combined input signal is provided to the test equipment.
In an embodiment, the method for measuring two or more input signals using a single-input measuring device may be used with a Multiple-Input Multiple-Output (MIMO) wireless system. Further, an autocorrelation may be performed by the test equipment on the combined input signal. In another embodiment, the first input and the second input may both be radio frequency signals.
The time delay may be calibrated. In addition, the time delay may be calibrated such that the time delay is greater than the timing skew between the first input and the second input.
The test equipment may be implemented in various embodiments. For example, the test equipment may include a real-time spectrum analyzer, an oscilloscope, a logic analyzer, and the like.
An apparatus for measuring two or more input signals using a single input on test equipment is also disclosed. The apparatus comprises test equipment that includes a test input for receiving an input signal into the test equipment. A summing block is included in electronic communication with the test input. A first input is in electronic communication with the summing block. A time delay block is in electronic communication with the summing block. A second input in electronic communication with the time delay block.
In an embodiment, the apparatus may include one or more antennas to receive the first input and the second input.
In a further embodiment, the apparatus may include a second time delay block in electronic communication with the summing block and a third input in electronic communication with the second time delay block.
A method for converting two or more spatially separated signals into two or more temporally separated signals to measure the signals using a single-input measuring device is also described. Test equipment that comprises a single-input measuring device is provided. A first input is received. A second input is received. The first input and the second input are spatially separated signals. The second input is delayed by a time delay T to provide a delayed second input. The first input and the delayed second input are combined to provide a combined input signal. The combined input signal includes a temporally separated signal derived from the spatially separated signal. The combined input signal is provided to the test equipment.
Various embodiments of the invention are now described with reference to the Figures, where like reference numbers indicate identical or functionally similar elements. The embodiments of the present invention, as generally described and illustrated in the Figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of several exemplary embodiments of the present invention, as represented in the Figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of the embodiments of the invention.
The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
Many features of the embodiments disclosed herein may be implemented as computer software, electronic hardware, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various components will be described generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
Where the described functionality is implemented as computer software, such software may include any type of computer instruction or computer executable code located within a memory device and/or transmitted as electronic signals over a system bus or network. Software that implements the functionality associated with components described herein may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across several memory devices.
Communications systems are used for transmission of information from one device to another. Prior to transmission, information is encoded into a format suitable for transmission over a communication channel. A wireless signal containing the encoded information is then transmitted over the communication channel. A communication receiver is used to receive the wireless signal.
Typically, the received wireless signal includes a plurality of multipath components. These multipath components are different versions of the wireless signal that are generated by reflections from structures and natural formations. The different multipath components experience degradation and additive noise as they travel through the communication channel. Thus, each multipath component includes a signal component that corresponds to the transmitted signal but may be distorted or degraded and a noise component that does not correspond to the transmitted signal.
One method to address multipath is to use receiver diversity. Receiver diversity typically provides multiple antennas separated by some fraction of a wavelength. With receiver diversity it is possible to switch between the antennas so that the system is getting the best signal. Selecting a particular antenna to get the signal with the best Signal to Noise Ratio (SNR) is referred to as antenna selection diversity.
A piece of test equipment that would be put in place of the receiver would typically be testing the transmitter and the transmission of the signals. The current systems and methods below would allow one receiver to be used to process the different signals from each different antenna, as will be discussed more fully below.
Multiple-Input Multiple-Output (MIMO) wireless systems increase user capacity in a variety of environments. MIMO systems use multiple antennas at both the transmitter and the receiver. MIMO systems provide a number of benefits including an increase in capacity, an increase in spectral efficiency, a reduction of fading, and an improved resistance to interference. With a MIMO system, the same information is typically transmitted on all of the antennas, but different coding is used. MIMO gives the system spatial diversity. One reference that discusses MIMO is by S. M. Alamouti, “A Simple Transmit Diversity Technique for Wireless Communications”, IEEE Journal on Select Areas in Communications, vol. 16, no. 8, October 1998, which is incorporated herein by reference.
Measuring MIMO Radio Frequency (RF) devices traditionally requires RF measurement equipment with as many input connections as there are RF outputs from the device being tested. While sequential testing of the multiple outputs is possible, it fails to test the simultaneous nature of modern MIMO devices. The current systems and methods below would allow one receiver to be used to process the different signals from each different antenna, as will be discussed more fully below.
The multiple signals 104, 106 being tested are usually the same frequency and often the same modulation. As such, they would normally require separate RF processing and acquisition. One implementation with separate RF processing and acquisition would use multiple instruments 102 for separate acquisitions and communication between them for the signal processing that accomplishes the measurements. If multiple pieces of test equipment 102 were required, the cost of the testing is higher, and sometimes much higher, than if a single piece of test equipment 102 were required. In addition, the synchronization between the multiple pieces of test equipment 102 would be complex and would complicate the testing procedure substantially. The present systems and methods do not require multiple pieces of test equipment 102 but provide a system 100 for measuring two or more input signals using a single-input measuring device 102.
If the system 100 of
The delay introduced by the time delay 108 needs to be sufficient so that the separate signals can be distinguished, but short enough so that a repetitive test transmission will not be delayed more than one half of the repetition interval. This will avoid ambiguity in the signal separation.
If this system were being used with MIMO, it may be desirable to obtain the timing skew. To obtain the timing skew between the two input signals 204, 206, the system could simply subtract the time T from the output waveform 216. Once the time T had been subtracted, the timing difference between the signals 204, 206 would be the timing skew.
In electronics and derivative fields such as telecommunications, a delay line is rigorously defined as a single-input-channel device, in which the output channel state at a given instant, t, is the same as the input channel state at the instant t-n, where n is a number of time units, i.e., the input sequence undergoes a delay of n time units, such as n femtoseconds, nanoseconds, or microseconds. (The delay line may have additional taps yielding output channels with values less than n.) In other words, the device introduces a delay of a certain amount of time between its input and output. A delay line may be used for the time delay.
The test equipment 602 may include a processor 603, memory 604, a communications interface 605, multiple input devices 607, multiple output devices 609 and a display 611. The processor 603 may also be referred to as a CPU. The processor 603 may be embodied as a microprocessor, a microcontroller, a programmable gate array or integrated circuit, a digital signal processor (DSP) or other device known in the art. The processor 603 typically performs logical and arithmetic operations based on program instructions, or logical definitions, stored within the memory 604 or circuits contained within the processor 603.
Display devices 611 used with embodiments disclosed herein may utilize any suitable image projection technology, such as a cathode ray tube (CRT), liquid crystal display (LCD), light-emitting diode (LED), gas plasma, electroluminescence, or the like. The display 611 may include a display controller. Alternatively a display controller may be included separately. The display controller may be used to convert data stored in the memory 604 into text, graphics, and/or moving images (as appropriate) shown on the display device 611.
The memory 604 provides instructions and data to the processor 603. A portion of the memory 604 may also include non-volatile random access memory (NVRAM). As used herein, the term “memory” 604 is broadly defined as any electronic component capable of storing electronic information, and may be embodied as read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices in RAM, on-board memory included with the processor 603, EPROM memory, EEPROM memory, registers, etc. The memory 604 typically stores program instructions and other types of data. The program instructions may be executed by the processor 603 to implement test programs 630 or procedures. The test programs 630 are used to process and analyze the data obtained by the piece of test equipment 602.
A piece of test equipment 602 typically also includes one or more input devices 607 and one or more output devices 609. Examples of different kinds of input devices 607 include a keyboard, keypad, switches, knobs, mouse, microphone, remote control device, button, joystick, trackball, touchpad, lightpen, sensors, etc. Examples of different kinds of output devices 609 may include an LCD screen, a speaker, printer, etc.
A transceiver 608 may be included to allow the reception and/or transmission of data by the test equipment 602. An embodiment of a system 600 for measuring two or more input signals using a single-input measuring device may be connected to the test equipment 602 and be electrically coupled to the transceiver 608.
The test equipment 602 may also include one or more communication interfaces 605 for communicating with other electronic devices. The communication interfaces 605 may be based on wired communication technology, wireless communication technology, or both. Examples of different types of communication interfaces 605 include a serial port, a parallel port, a Universal Serial Bus (USB), an Ethernet adapter, an IEEE 1394 bus interface, a small computer system interface (SCSI) bus interface, an infrared (IR) communication port, a Bluetooth wireless communication adapter, a ZigBee wireless communication adapter, WLAN, an ultra wideband wireless communication adapter, and so forth.
One or more data acquisition units 632 are included in the test equipment 602 to acquire data for capture and analysis. The data acquisition units 632 may include analog to digital converters, filters, amplifiers, etc., as needed to capture and store the data. The data acquired by the data acquisition units 632 is stored in the memory 604.
Digital signal processing units 634 may also be included in the test equipment 602 to perform various kinds of digital signal processing on any acquired data. The processor 603 has the ability to perform some data processing, but in some environments faster processing is required. Dedicated digital signal processing units 634 can usually provide significant performance increases over what the processor 603 can provide.
The real-time spectrum analyzer 702 is designed to address the measurement challenges associated with transient and dynamic RF signals. The real-time spectrum analyzer 702 has the ability to trigger on an RF signal, capture it into memory, and analyze it in multiple domains. This makes it possible to reliably detect and characterize RF signals that change over time.
The input 704 is obtained from an embodiment of a system 700 for measuring two or more input signals using a single-input measuring device. The input signal 704 that is to be analyzed is sent through a low pass filter 740 after which it is down-converted by an RF down-converter 742 to a fixed Intermediate Frequency (IF) that is related to the maximum real-time bandwidth of the real-time spectrum analyzer 702. This RF front-end can be tuned across the entire frequency range of the instrument 702.
The signal is then filtered by an IF filter 744, digitized by the Analog to Digital Converter (ADC) 746, and passed to the DSP engine 748 that manages the instrument's digital signal processing 750, triggering 752, and memory 754, and analysis functions.
The DSP engine 748 enables the real-time spectrum analyzer 702 to provide a user with many different and useful views of the input signal. A frequency domain view 756 may be provided, as well as a time domain view 758. Furthermore, views of modulation analysis 760 may be provided. A spectrogram is a frequency versus time versus amplitude display where the frequency is represented on the x-axis and time on the y-axis. The power is typically expressed by the color. A spectrogram view 762 may be provided. The analyzer 702 may also provide a codogram view 764. A codogram view 764 is a code channel versus time versus power display where the CDMA code channel is represented on the x-axis and time respectively on the y-axis. The power level is expressed by the color.
If the system is being used with MIMO, one way to calibrate 802 the time delay is to first determine the timing skew between the two signals. One way to determine the timing skew is to perform a cross correlation between the two signals. Once the timing skew has been determined, the delay may be set so that it is greater than the timing skew such that the separate signals can be distinguished.
For each additional input that needs to be captured and analyzed, a time delay is introduced 804 into the additional inputs. Specific examples of this were shown in
Through use of the present systems and methods a single-input measuring device is used to measure multiple input signals. Two or more spatially separated signals are converted into two temporally separated signals.
One possible application of the present systems and methods is with a MIMO system. With MIMO, because the time delay T is known, the system can subtract out the T and know the timing skew. Furthermore, the systems and methods delay the second (and any more than two) signal and use DSP processing (auto-correlation) to identify multiple copies of the signal at different time offsets. These multiple copies will be evident as correlation peaks at a time separation equal to the introduced delay. This is particularly useful with digitally modulated signals.
Information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the present invention. In other words, unless a specific order of steps or actions is required for proper operation of the embodiment, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the present invention.
While specific embodiments and applications of the present invention have been illustrated and described, it is to be understood that the invention is not limited to the precise configuration and components disclosed herein. Various modifications, changes, and variations which will be apparent to those skilled in the art may be made in the arrangement, operation, and details of the methods and systems of the present invention disclosed herein without departing from the spirit and scope of the invention.
