Patent Application
20110080211
The present inventions are related to systems and methods for detecting and/or decoding information, and more particularly to systems and methods for reducing noise in the when detecting and/or decoding information.
Various data transfer systems have been developed including storage systems, cellular telephone systems, and radio transmission systems. In each of the systems data is transferred from a sender to a receiver via some medium. For example, in a storage system, data is sent from a sender (i.e., a write function) to a receiver (i.e., a read function) via a storage medium. The effectiveness of any transfer is impacted by any noise evident in the data being received from the medium. In some cases, the received signal exhibits a noise level that does not allow any downstream data detection process to converge. To heighten the possibility of convergence, various existing processes utilize two or more detection and decode iterations. However, even with such extended data detection capability, the noise included in the received signal may still preclude convergence.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for data processing.
The present inventions are related to systems and methods for detecting and/or decoding information, and more particularly to systems and methods for reducing noise in the when detecting and/or decoding information.
Various embodiments of the present invention provide noise reduced data processing circuits. Such circuits include a selector circuit, a sample set averaging circuit, and a data detection circuit. The selector circuit provides either a new sample set or an averaged sample set as a sample output based on a select control signal. The sample set averaging circuit receives the new sample set and provides the averaged sample set. The averaged sample set is based upon two or more instances of the new sample set. The data detection circuit receives the sample output, and performs a data detection algorithm on the sample output and provides the select control signal and a data output. Some instances of the aforementioned embodiments include a sample buffer that stores the sample output from the selector circuit, and provides the sample output to the data detection circuit. In particular instances, the sample set averaging circuit includes the sample buffer and an adder circuit. The adder circuit adds the new sample set to the sample output.
In various instances of the aforementioned embodiments, the sample buffer includes a divider circuit. The divider circuit divides the sample output by the number of instances of the new sample set included in the sample output, and the output of the divider circuit is provided to the data detection circuit as the sample output. In other instances of the aforementioned embodiments, the number of instances of the new sample set included in the sample output is a power of two. In such instances, a shift circuit divides the sample output by the number of instances of the new sample set included in the sample output. The output of the shift circuit is provided to the data detection circuit as the sample output.
In some instances of the aforementioned embodiments, the select control signal is asserted to select the averaged sample set as the sample output when the data detection circuit fails to converge when processing an initial instance of the new sample set. In various embodiments of the present invention, the data detection circuit includes a channel detector, and a low density parity check decoder. The channel detector receives the sample output, and an output of the channel detector is provided to the low density parity check decoder. In particular instance of the aforementioned embodiments, the data detection circuit further includes a soft/hard decision buffer. The data output is provided by the soft/hard decision buffer. In some embodiments of the present invention, the data detection circuit further includes an averaged retry logic circuit that receives an indication of whether the low density parity check decoder converged, and asserts the select control signal.
Other embodiments of the present invention provide methods for performing reduced noise data processing. Such methods include receiving a first instance of a new sample set, and performing a data detection on the new sample set. Where the data detection fails to converge, a second instance of the new sample set is received and a sample set average is performed. The sample set average includes adding at least the first instance of the new sample set with the second instance of the new sample set to create an averaged sample set. A data detection is then performed on the averaged sample set. In particular instances of the aforementioned embodiments, the methods further include receiving a third instance and a fourth instance of the new sample set.
Yet other embodiments of the present invention provide systems for selectively performing reduced noise data processing. The systems include a data input derived from a medium. The systems further include a data processing circuit that includes a selector circuit, a sample set averaging circuit, and a data detection circuit. The selector circuit provides either a new sample set or an averaged sample set as a sample output based on a select control signal. The sample set averaging circuit receives the new sample set and provides the averaged sample set. The averaged sample set is based upon two or more instances of the new sample set. The data detection circuit receives the sample output, and performs a data detection algorithm on the sample output and provides the select control signal and a data output. In some cases, the medium is a magnetic storage medium. In other instances, the medium is a transmission medium, such as, for example, a wireless transmission medium, a wired transmission medium, or an optical transmission medium.
This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.
A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several figures to refer to similar components. In some instances, a sub-label consisting of a lower case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components.
The present inventions are related to systems and methods for detecting and/or decoding information, and more particularly to systems and methods for reducing noise in the when detecting and/or decoding information.
Various embodiments of the present invention provide data processing circuits that reduce or eliminate the effects of read and/or write noise associated with a transferred data set. In some embodiments of the present invention, the noise reduction is selectively utilized. In such cases, the noise reduction may involve some level of latency. By selectively enabling the noise reduction, the latency is only incurred when necessary. In some embodiments of the present invention, the noise reduction is provided by multiply receiving a given set of data and averaging the multiple reads. This averaging process tends to reduce data independent noise that may have been introduced during transfer of the data set. The averaged data set is then provided for data detection where the noise reduction increases the probability that the data detection process will converge. In some embodiments, the noise reduction function is only selected after the non-averaged data set fails to converge.
Turning to
In addition, sample output 127 is provided to a digital detection circuit 135 that is responsible for decoding and/or detecting the information represented by sample output 127. Digital detection circuit 135 may be any detection/decoding circuit known in the art. For example, digital detection circuit 135 may include a channel detector feeding a low density parity check decoder as are known in the art. As another example, digital detection circuit 135 may include a channel detector feeding a Reed Solomon decoder as are known in the art. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a myriad of decoder and/or detectors that may be used to implement digital detection circuit 135 in accordance with different embodiments of the present invention. Digital detection circuit 135 provides a data output 140.
In addition to the standard decoding and detection circuitry, digital detection circuit 135 is modified to provide select control signal 137 and enable input 115. Select control signal 137 and enable input 115 determines whether the noise reduction processes noise reduction front end circuit 105 are implemented in relation to a given data set. The following pseudo-code describes the operation of noise reduction front end circuit 105:
Consistent with the preceding pseudo-code and the embodiment depicted in
Where, on the other hand, digital detection circuit 135 fails to converge when operating on a non-averaged data set, data output 140 is indicated as unavailable and potentially recoverable. In this situation, the previously processed data set is re-read a number of times (i.e., a number of times corresponding to “Defined Count” in the pseudo-code). Each time the data set is re-read, it is averaged with the other times the data set has been read. This process of averaging averages the re-read data sets together on a bit period by bit period basis resulting in an averaged data set of the same length as the originally received data set. This process of averaging reduces or eliminates any random read noise (i.e., non-data dependent noise exhibited by the data set). Once the defined number or re-reads and averaging is completed, averaged sample input 117 is provided to sample buffer 125 via multiplexer 120, and then to digital detection circuit 135 where the detection and/or decoding processes are performed to derive data output 140.
In some cases where data processing circuit 100 is implemented as part of a hard disk drive system, the data set that is processed on any iteration of data processing circuit 100 corresponds to a full sector of data. In other cases, the data set has a length less than or more than an entire sector. In particular cases, the data set may include a portion from one sector and a portion from another sector. Where, on the other hand, data processing circuit 100 is implemented as part of a data communication system, the length of the given data set may be pre-defined. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize various data lengths that may be processed.
In one particular embodiment of the present invention, selective adder circuit 110 is implemented as an adder circuit. When enable input 115 is asserted such that new sample input 103 is to be written to selective adder circuit 110, the adder circuit adds each bit of new sample input 103 to a zero. This effectively results in a write of new sample input 103 to selective adder circuit 110. Alternatively, when enable input 115 is asserted such that averaging is to be performed, the adder circuit adds new sample input 103 to sample output 127 on a bit period by bit period basis. As new sample input 103 is another instance of sample output 127, noise in one instance may operate to cancel noise in another instance. As averaged output 117 is written to sample buffer 125, the combination of the adder circuit and sample buffer 125 operate as an accumulator. Prior to providing sample output 127 to digital detection circuit 135, the accumulated value is divided by the number of added samples to create an average. In some embodiments, a divider is employed as part of sample buffer 125 to finish the averaging process. In other cases, the number of averaged samples is a factor of two (i.e., 2n). In these cases, the average is obtained by using a shift function incorporated in sample buffer 125, where the amount of the shift corresponds to the number of averaged samples. In some embodiments, the averaging is performed by weighted addition. In these cases, the averaged output 117 and the new input 103 are multiplied by two weighting factors such that the sum of the weighting factors equals 1. The weighted sum of the averaged output 117 and the new input 103 is written into the sample buffer 125. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other circuitry that may be used to average a number of new samples 103.
Turning to
In addition, sample output 227 is provided to a channel detector 250 that performs a detection process and provides a series of hard outputs and soft outputs to a low density parity check decoder 260. Low density parity check decoder 260 may perform one or more local iterations 264 where the result of a prior low density parity check feeds back to perform another low density parity check as is known in the art. In some cases, one or more global iterations 262 may be performed where the result of a prior low density parity check feeds back to perform another iteration of channel detector 250 and low density parity checking as is known in the art. Low density parity check decoder 260 provides a data output to a soft/hard decision buffer 280 as is known in the art. Soft/hard decision buffer 280 provides a data output 240.
In addition to the standard decoding circuitry, low density parity check decoder 260 indicates whether low density parity check decoder 260 converged. Where the result converges, a convergence indicator 268 is asserted. Otherwise, convergence indicator 268 is de-asserted. An averaged retry logic circuit 270 receives convergence indicator 268, and provides select control signal 237 and enable input 215. Select control signal 237 and enable input 215 determines whether the noise reduction processes noise reduction front end circuit 205 are implemented in relation to a given data set. The following pseudo-code describes the operation of noise reduction front end circuit 205:
Consistent with the preceding pseudo-code and the embodiment depicted in
Where, on the other hand, low density parity check decoder 260 fails to converge when operating on a non-averaged data set, data output 240 is indicated as unavailable and potentially recoverable. In this situation, the previously processed data set is re-read a number of times (i.e., a number of times corresponding to “Defined Count” in the pseudo-code). Each time the data set is re-read, it is averaged with the other times the data set has been read. This process of averaging averages the re-read data sets together on a bit period by bit period basis resulting in an averaged data set of the same length as the originally received data set. This process of averaging reduces or eliminates any random noise (i.e., non-data dependent noise exhibited by the data set). Once the defined number or re-reads and averaging is completed, averaged sample input 217 is provided to sample buffer 225 via multiplexer 220, and then to channel detector 250 and low density parity check decoder 260 where the detection and decoding processes are performed to derive data output 240.
In some cases where data processing circuit 200 is implemented as part of a hard disk drive system, the data set that is processed on any iteration of data processing circuit 200 corresponds to a full sector of data. In other cases, the data set has a length less than or more than an entire sector. In particular cases, the data set may include a portion from one sector and a portion from another sector. Where, on the other hand, data processing circuit 200 is implemented as part of a data communication system, the length of the given data set may be pre-defined. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize various data lengths that may be processed.
In one particular embodiment of the present invention, selective adder circuit 210 is implemented as an adder circuit. When enable input 215 is asserted such that new sample input 203 is to be written to selective adder circuit 210, the adder circuit adds each bit of new sample input 203 to a zero. This effectively results in a write of new sample input 203 to selective adder circuit 210. Alternatively, when enable input 215 is asserted such that averaging is to be performed, the adder circuit adds new sample input 203 to sample output 227 on a bit period by bit period basis. As new sample input 203 is another instance of sample output 227, noise in one instance may operate to cancel noise in another instance. As averaged output 217 is written to sample buffer 225, the combination of the adder circuit and sample buffer 225 operate as an accumulator. Prior to providing sample output 227 to channel detector 250 and low density parity check decoder 260, the accumulated value is divided by the number of added samples to create an average. In some embodiments, a divider is employed as part of sample buffer 225 to finish the averaging process. In other cases, the number of averaged samples is a factor of two (i.e., 2n). In these cases, the average is obtained by using a shift function incorporated in sample buffer 225, where the amount of the shift corresponds to the number of averaged samples. Also in some embodiments, the averaging is obtained by computing the weighted sum of the new sample input 203 and the sample output 227, where the weighting factors are programmable and sum up to 1. In these cases, a divider is avoided and the samples stored in Y sample buffer 225 can have less bit width than using an accumulator and divider. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other circuitry that may be used to average a number of new samples 203.
Turning to
It is determined whether the data detection process converged (block 310). Where the data detection process converged (block 310), the data output is provided as an output (block 350). Then, the data corresponding to the next defined information set are read (block 302) and the processes of blocks 304-310 are repeated for the next data input.
Alternatively, where the data detection process failed to converge (block 310), the data corresponding to the defined data set is re-read (block 322). This may include, for example, performing the same process as block 302 on the same data set previously read. This newly read data set is averaged with the originally read data set (or with the averaged data sets for the second or later read) (block 324) and the resulting average is stored to a sample buffer (block 326). It is then determined whether a programmed number of re-reads have been averaged together (block 328). Where the programmed number of re-reads has not been completed (block 328), the defined information set is again re-read (block 322) and the processes of blocks 324-328 are repeated for the newly read data samples.
Alternatively, where the programmed number of re-reads has been incorporated in the average (block 328), the data detection process is performed on the averaged samples (block 330). The data detection process is the same data detection process previously discussed in relation to block 308, except that the input to the process is an averaged sample set. It is determined whether the data detection process converged (block 332). Where the data detection process converged (block 332), the data output is provided as an output (block 350). Then, the data corresponding to the next defined information set are read (block 302) and the processes of blocks 304-310 are repeated for the next data input. Alternatively, where the data detection process failed to converge (block 332), an error is indicated (block 334). Then, the data corresponding to the next defined information set are read (block 302) and the processes of blocks 304-310 are repeated for the next data input.
Turning to
Once read/write head assembly 476 is positioned adjacent the proper data track, magnetic signals representing data on disk platter 478 are sensed by read/write head assembly 476 as disk platter 478 is rotated by spindle motor 472. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter 478. This minute analog signal is transferred from read/write head assembly 476 to read channel module 410 via preamp 430. Preamp 430 is operable to amplify the minute analog signals accessed from disk platter 478. In addition, preamp 430 is operable to amplify data from read channel module 410 that is destined to be written to disk platter 478. In turn, read channel module 410 decodes and digitizes the received analog signal to recreate the information originally written to disk platter 478. Where the data fails to converge, it may be re-read multiple times and an average of the re-read data may then be decoded and digitized as discussed above in relation to
Turning to
In conclusion, the invention provides novel systems, devices, methods and arrangements for performing noise reduced data decoding and/or detection. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. For example, one or more embodiments of the present invention may be applied to various data storage systems and digital communication systems, such as, for example, tape recording systems, optical disk drives, wireless systems, and digital subscribe line systems. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.
The present application claims priority to (is a non-provisional of) U.S. Pat. App. No. 61/116,389 entitled “Systems and Methods for Noise Reduced Data Detection” and filed Nov. 20, 2008 by Yang et al. The entirety of the aforementioned provisional patent application is incorporated herein by reference for all purposes.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/US09/40986 | 4/17/2009 | WO | 00 | 11/16/2010 |
| Number | Date | Country | |
|---|---|---|---|
| 61116389 | Nov 2008 | US |
