Patent Application
20170371559
The disclosed embodiments relate generally to memory systems, including but not limited to, optimizing media read times within a non-volatile storage device.
Semiconductor memory devices, including flash memory, typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage. A flash memory cell, for example, typically includes a single transistor with a floating gate that is used to store a charge representative of a data value. Flash memory is a non-volatile data storage device that can be electrically erased and reprogrammed. More generally, non-volatile memory (e.g., flash memory, as well as other types of non-volatile memory implemented using any of a variety of technologies) retains stored information even when not powered, as opposed to volatile memory, which requires power to maintain the stored information. Increases in storage density have been facilitated in various ways, including increasing the density of memory cells on a chip enabled by manufacturing developments, and transitioning from single-level flash memory cells to multi-level flash memory cells, so that two or more bits can be stored by each flash memory cell.
Read response times are increasingly important to storage consumers. In some instances, such as when read operations are much more frequent than write operations, read response times are a primary performance metric. The read response time varies from memory cell to memory cell. It is therefore important to optimize read response times to enhance device performance.
Various implementations of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the attributes described herein. Without limiting the scope of the appended claims, after considering this disclosure, and particularly after considering the section entitled “Detailed Description” one will understand how the aspects of various implementations are used to optimize read times to enhance performance a non-volatile storage device. In one aspect, based on a predicted read frequency for particular data, one or more preferred storage locations within the memory are determined and the particular data is stored in one of the one or more preferred storage locations.
So that the present disclosure can be understood in greater detail, a more particular description may be had by reference to the features of various implementations, some of which are illustrated in the appended drawings. The appended drawings, however, merely illustrate the more pertinent features of the present disclosure and are therefore not to be considered limiting, for the description may admit to other effective features.
In accordance with common practice the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may not depict all of the components of a given system, method or device. Finally, like reference numerals may be used to denote like features throughout the specification and figures.
The various implementations described herein include systems, methods and/or devices used to optimize read times to enhance performance of a non-volatile storage device. Some implementations include systems, methods and/or devices to determine, based on a predicted read frequency for particular data, one or more preferred storage locations within the memory, and store the particular data in one of the one or more preferred storage locations.
(A1) In one aspect, some implementations include a method performed at a storage device with one or more processors and memory coupled to the one or more processors. The method includes: (1) predicting a read frequency (sometimes called a read temperature) for particular data; (2) based on the predicted read frequency, determining one or more preferred storage locations within the memory; and (3) storing the particular data in a preferred storage location of the one or more preferred storage locations.
(A2) In some implementations of the method of A1, predicting the read frequency for the particular data includes predicting the read frequency for the particular data based on an amount of read disturbs associated with the particular data.
(A3) In some implementations of the method of any one of A1-A2, the method further includes obtaining the particular data from a host system; where predicting the read frequency for the particular data includes obtaining read frequency information from the host system.
(A4) In some implementations of the method of any one of A1-A3, the method further includes tracking a number of read operations corresponding to a particular region of a plurality of regions in a logical address space of a host; where the particular data corresponds to a particular region of the plurality of regions; and where predicting the read frequency for the particular data comprises predicting the read frequency for the particular data based on the tracked number of read operations.
(A5) In some implementations of the method of any one of A1-A4, the predicted read frequency indicates that the particular data is hot read data; and the one or more preferred storage locations include storage locations denoted as having a fast read response.
(A6) In some implementations of the method of any one of A1-A5, the storage device further includes a write buffer, and storing the particular data in the preferred storage location comprises: (1) holding the particular data at a location within the write buffer corresponding to the preferred storage location; and (2) transferring the particular data from the write buffer to the preferred storage location.
(A7) In some implementations of the method of any one of A1-A6, the memory includes a plurality of memory groups and the method further includes: (1) obtaining a respective read response parameter for each memory group of the plurality of memory groups; (2) mapping the predicted read frequency to a particular read response parameter value; and (3) comparing the particular read response parameter value to the respective read response parameter for a particular memory group, the particular memory group including at least one preferred storage location of the one or more preferred storage locations; where determining the one or more preferred storage locations within the memory includes determining the at least one preferred storage location based on the comparison of the particular read response parameter value to the read response parameter for the particular memory group.
(A8) In some implementations of the method of A7, the read response parameter is based on at least one of: (1) a read latency for the particular memory group (e.g., an average latency or peak latency); (2) an error rate for the particular memory group (e.g., an error rate for a particular page, die, or block); and (3) a word line corresponding to the particular memory group (e.g., word line 0).
(A9) In some implementations of the method of any one of A7-A8, each memory group of the plurality of memory groups corresponds to a particular memory page type (e.g., upper, middle, lower pages).
(A10) In some implementations of the method of any one of A1-A9, the method further includes: (1) obtaining second data; (2) predicting a read frequency for the second data; (3) based on the predicted read frequency for the second data, determining one or more second preferred storage locations within the memory; and (4) based on one or more write conditions, storing the second data in a location in memory other than the one or more second preferred storage locations.
(A11) In some implementations of the method of any one of A1-A10, the method further includes: (1) obtaining read frequency information corresponding to the particular data; (2) predicting a new read frequency for the particular data based on the obtained read frequency information; (3) determining one or more new preferred storage locations within the memory based on the new read frequency prediction, where the one or more new preferred storage locations are distinct from the one or more preferred storage locations; and (4) transferring the particular data to a new preferred storage location of the one or more new preferred storage locations.
(A12) In some implementations of the method of any one of A1-A11, the memory comprises a plurality of non-volatile memory devices (e.g., flash memory devices).
(A13) In some implementations of the method of any one of A11-A12, the memory comprises one or more three-dimensional (3D) memory devices, and the storage device includes circuitry associated with operation of memory elements in one or more 3D memory devices.
(A14) In some implementations of the method of A13, the circuitry and one or more memory elements in a respective 3D memory device of the one or more 3D memory devices are on the same substrate.
In another aspect, some implementations include a storage system including memory and a controller coupled to the memory. In some implementations, the controller is configured to perform any of the methods described herein (e.g., A1-A14 described above).
In yet another aspect, some implementations include a non-transitory computer-readable storage medium storing one or more programs for execution by one or more processors of a storage device, the one or more programs including instructions for performing any of the methods described herein (e.g., A1-A14 described above).
In yet another aspect, some implementations include a storage system with the means to perform any of the methods described herein (e.g., A1-A14 described above).
Numerous details are described herein in order to provide a thorough understanding of the example implementations illustrated in the accompanying drawings. However, some embodiments may be practiced without many of the specific details, and the scope of the claims is only limited by those features and aspects specifically recited in the claims. Furthermore, well-known methods, components, and circuits have not been described in exhaustive detail so as not to unnecessarily obscure more pertinent aspects of the implementations described herein.
Computer system 110 is coupled to storage controller 124 through data connections 101. However, in some embodiments computer system 110 includes storage controller 124, or a portion of storage controller 124, as a component and/or as a subsystem. For example, in some embodiments, some or all of the functionality of storage controller 124 is implemented by software executed on computer system 110. Computer system 110 may be any suitable computer device, such as a computer, a laptop computer, a tablet device, a netbook, an internet kiosk, a personal digital assistant, a mobile phone, a smart phone, a gaming device, a computer server, or any other computing device. Computer system 110 is sometimes called a host, host system, client, or client system. In some embodiments, computer system 110 is a server system, such as a server system in a data center. In some embodiments, computer system 110 includes one or more processors, one or more types of memory, a display and/or other user interface components such as a keyboard, a touch-screen display, a mouse, a track-pad, a digital camera, and/or any number of supplemental I/O devices to add functionality to computer system 110. In some embodiments, computer system 110 does not have a display and other user interface components.
Storage medium 132 is coupled to storage controller 124 through connections 103. Connections 103 are sometimes called data connections, but typically convey commands in addition to data, and optionally convey metadata, error correction information and/or other information in addition to data values to be stored in storage medium 132 and data values read from storage medium 132. In some embodiments, storage controller 124 and storage medium 132 are included in the same device (i.e., an integrated device) as components thereof. Furthermore, in some embodiments, storage controller 124 and storage medium 132 are embedded in a host device (e.g., computer system 110), such as a mobile device, tablet, other computer or computer controlled device, and the methods described herein are performed, at least in part, by the embedded storage controller. Storage medium 132 may include any number (i.e., one or more) of memory devices (e.g., NVM 134-1, NVM 134-2 through NVM 134-n) including, without limitation, persistent memory or non-volatile semiconductor memory devices, such as flash memory device(s). For example, flash memory device(s) can be configured for enterprise storage suitable for applications such as cloud computing, for database applications, primary and/or secondary storage, or for caching data stored (or to be stored) in secondary storage, such as hard disk drives. Additionally and/or alternatively, flash memory device(s) can also be configured for relatively smaller-scale applications such as personal flash drives or hard-disk replacements for personal, laptop, and tablet computers.
Memory devices (e.g., NVM 134-1, NVM 134-2, etc.) of storage medium 132 include addressable and individually selectable blocks, such as selectable portion of storage medium 136 (also referred to herein as selected portion 136). In some embodiments, the individually selectable blocks (sometimes called erase blocks) are the minimum size erasable units in a flash memory device. In other words, each block contains the minimum number of memory cells that can be erased simultaneously. In some embodiments, each block is further divided into a plurality of pages and/or word lines. In some embodiments, each page or word line is an instance of the smallest individually accessible (readable) portion in a block. In some embodiments (e.g., using some types of flash memory), the smallest individually accessible unit of a data set, however, is a sector, which is a subunit of a page. That is, a block includes a plurality of pages, each page contains a plurality of sectors, and each sector is the minimum unit of data for writing data to or reading data from the flash memory device.
In some embodiments, storage controller 124 includes a management module 121, a host interface 129, a storage medium I/O interface 128, and, optionally, one or more additional module(s) 125, such as an error correction module and/or a garbage collection module. Storage controller 124 may include various additional features that have not been illustrated for the sake of brevity and so as not to obscure pertinent features of the example embodiments disclosed herein, and a different arrangement of features may be possible. Host interface 129 provides an interface to computer system 110 through data connections 101. Similarly, storage medium interface 128 (sometimes called storage medium I/O 128) provides an interface to storage medium 132 through connections 103. In some embodiments, storage medium I/O 128 includes read and write circuitry, including circuitry capable of providing reading signals to storage medium 132 (e.g., reading threshold voltages for NAND-type flash memory).
In some embodiments, management module 121 includes one or more processing units 122 (sometimes herein called CPUs, processors, or hardware processors, and sometimes implemented using microprocessors, microcontrollers, or the like) configured to execute instructions in one or more programs (e.g., in management module 121). In some embodiments, the one or more processing units 122 are shared by one or more components within, and in some cases, beyond the function of storage controller 124. Management module 121 is coupled to host interface 129, additional module(s) 125, and storage medium I/O 128 in order to coordinate the operation of these components. In some embodiments, one or more modules of management module 121 are implemented in a management module of computer system 110 (not shown). In some embodiments, one or more processors of computer system 110 (not shown) are configured to execute instructions in one or more programs. In some embodiments, a management module within computer system 110 is coupled to storage device 120 in order to manage the operation of storage device 120.
In some embodiments, management module 121 includes write buffer 140. In some embodiments, write buffer 140 comprises volatile memory, such as dynamic random access memory (DRAM). In some other embodiments, write buffer 140 comprises non-volatile memory, such as non-volatile random access memory (NVRAM). Write buffer 140 holds (e.g., temporarily stores) data received by management module 121 prior to it being written to storage medium 132. In some embodiments, write buffer 140 holds host data, control data, metadata, and the like. In some embodiments, write buffer 140 is used to arrange data into a particular order so that it can be written to particular memory cells within storage medium 132. Additional details regarding the operation of write buffer 140 are described below with respect to
Additional module(s) 125 are coupled to storage medium I/0128, host interface 129, and management module 121-1. As an example, additional module(s) 125 optionally include an error control module to limit the number of uncorrectable errors inadvertently introduced into data during writes to memory or reads from memory. In some embodiments, additional module(s) 125 are executed in software by the one or more processing units 122 of management module 121, and, in other embodiments, additional module(s) 125 are implemented in whole or in part using special purpose circuitry (e.g., to perform data encoding and decoding functions). In some embodiments, additional module(s) 125 are implemented in whole or in part by software executed on computer system 110.
In some embodiments, an error control module, included in additional module(s) 125, includes an encoder and a decoder. In some embodiments, the encoder encodes data by applying an error-correcting code (ECC) to produce a codeword, which is subsequently stored in NVM devices 134. When encoded data (e.g., one or more codewords) is read from NVM devices 134, the decoder applies a decoding process to the encoded data to recover the data, and to correct errors in the recovered data within the error correcting capability of the error-correcting code. Those skilled in the art will appreciate that various error-correcting codes have different error detection and correction capacities, and that particular codes are selected for various applications for reasons beyond the scope of this disclosure. As such, an exhaustive review of the various types of error-correcting codes is not provided herein. Moreover, those skilled in the art will appreciate that each type or family of error-correcting codes may have encoding and decoding algorithms that are particular to the type or family of error-correcting codes. On the other hand, some algorithms may be utilized at least to some extent in the decoding of a number of different types or families of error-correcting codes. As such, for the sake of brevity, an exhaustive description of the various types of encoding and decoding algorithms generally available and known to those skilled in the art is not provided herein.
In some embodiments, during a write operation, host interface 129 receives data to be stored in NVM devices 134 from computer system 110. The data received by host interface 129 is made available to an encoder (e.g., in additional module(s) 125), which encodes the data to produce one or more codewords. The one or more codewords are made available to storage medium interface 128, which transfers the one or more codewords to storage medium 132 in a manner dependent on the type of storage medium being utilized.
In some embodiments, a read operation is initiated when computer system (host) 110 sends one or more host read commands (e.g., via data connections 101, or alternatively a separate control line or bus) to storage controller 124 requesting data from NVM devices 134. Storage controller 124 (e.g., management module 121) sends one or more read access commands to NVM devices 134, via storage medium interface 128, to obtain raw read data in accordance with memory locations (addresses) specified by the one or more host read commands. Storage medium interface 128 provides the raw read data (e.g., comprising one or more codewords) to a decoder (e.g., in additional module(s) 125). If the decoding is successful, the decoded data is provided to host interface 129, where the decoded data is made available to computer system 110. In some embodiments, if the decoding is not successful, storage controller 124 may resort to a number of remedial actions or provide an indication of an irresolvable error condition.
As explained above, a storage medium (e.g., storage medium 132) is divided into a number of addressable and individually selectable blocks and each block is optionally (but typically) further divided into a plurality of pages and/or word lines and/or sectors. While erasure of a storage medium is performed on a block basis, in many embodiments, reading and programming of the storage medium is performed on a smaller subunit of a block (e.g., on a page basis, word line basis, or sector basis). In some embodiments, the smaller subunit of a block consists of multiple memory cells (e.g., a plurality of single-level cells and/or multi-level cells). In some embodiments, programming is performed on an entire page. In some embodiments, a multi-level cell (MLC) NAND flash is utilized. MLC NAND has four possible states per cell, yielding two bits of information per cell. Further, in some embodiments, an MLC NAND has two page types: (1) a lower page (sometimes called fast page), and (2) an upper page (sometimes called slow page). In some embodiments, a triple-level cell (TLC) NAND flash is utilized. TLC NAND has eight possible states per cell, yielding three bits of information per cell. Although the description herein uses TLC, MLC, and SLC as examples, those skilled in the art will appreciate that the embodiments described herein may be extended to memory cells that have more than eight possible states per cell, yielding more than three bits of information per cell. In some embodiments, the encoding format of the storage media (i.e., TLC, MLC, or SLC and/or a chosen data redundancy mechanism or ECC code) is a choice made when data is received at the storage device or when written to the storage medium.
As an example, in some embodiments, if data is written to a storage medium in pages, but the storage medium is erased in blocks, pages in the storage medium may contain invalid (e.g., stale) data, but those pages cannot be overwritten until the whole block containing those pages is erased. In order to write to the pages with invalid data, the pages (if any) with valid data in that block are read and re-written to a new block and the old block is erased (or put on a queue for erasing). This process is typically called garbage collection. After garbage collection, the new block contains the pages with valid data and may have free pages that are available for new data to be written, and the old block can be erased so as to be available for new data to be written. Since flash memory can only be programmed and erased a limited number of times, the efficiency of the algorithm used to pick the next block(s) to re-write and erase has an impact on the lifetime and reliability of flash-based storage systems.
Write amplification is a phenomenon where the actual amount of physical data written to a storage medium (e.g., NVM devices 134) is a multiple of the logical amount of data written by a host (e.g., computer system 110) to the storage medium. As discussed above, when a block of storage medium must be erased before it can be re-written, the garbage collection process to perform these operations results in re-writing data one or more times. This multiplying effect increases the number of writes required over the life of a storage medium, which shortens the time it can reliably operate. The formula to calculate the write amplification of a storage system is given by an equation, such as Equation 1 below.
In some instances, one of the goals of a flash memory based data storage system architecture is to reduce write amplification as much as possible so that available endurance is used to meet storage medium reliability and warranty specifications. Higher system endurance also results in lower cost as the storage system may need less over-provisioning. By reducing write amplification, the endurance of the storage medium is increased and the overall cost of the storage system is decreased. Generally, garbage collection is performed on erase blocks with the fewest number of valid pages for best performance and best write amplification.
Flash memory devices utilize memory cells to store data as electrical values, such as electrical charges or voltages. Each flash memory cell typically includes a single transistor with a floating gate that is used to store a charge, which modifies the threshold voltage of the transistor (i.e., the voltage needed to turn the transistor on). The magnitude of the charge, and the corresponding threshold voltage the charge creates, is used to represent one or more data values. In some embodiments, during a read operation, a reading threshold voltage is applied to the control gate of the transistor and the resulting sensed current or voltage is mapped to a data value.
The terms “cell voltage” and “memory cell voltage,” in the context of flash memory cells, means the threshold voltage of the memory cell, which is the minimum voltage that needs to be applied to the gate of the memory cell's transistor in order for the transistor to conduct current. Similarly, reading threshold voltages (sometimes also called reading signals and reading voltages) applied to a flash memory cells are gate voltages applied to the gates of the flash memory cells to determine whether the memory cells conduct current at that gate voltage. In some embodiments, when a flash memory cell's transistor conducts current at a given reading threshold voltage, indicating that the cell voltage is less than the reading threshold voltage, the raw data value for that read operation is a “1” and otherwise the raw data value is a “0.”
Although
Host interface 129 provides an interface to computer system 110 through data connections 101. Memory controller 126 is coupled to host interface 129 and non-volatile memory controllers 130. In some implementations, during a write operation, memory controller 126 receives data from computer system 110 through host interface 129 and during a read operation, memory controller 126 sends data to computer system 110 through host interface 129. Further, host interface 129 provides additional data, signals, voltages, and/or other information needed (or preferred) for communication between memory controller 126 and computer system 110. In some embodiments, memory controller 126 and host interface 129 use a defined interface standard for communication, such as double data rate type three synchronous dynamic random access memory (DDR3). In some embodiments, memory controller 126 and non-volatile memory controllers 130 use a defined interface standard for communication, such as serial advance technology attachment (SATA). In some other implementations, the device interface used by memory controller 126 to communicate with non-volatile memory controllers 130 is SAS (serial attached SCSI), or other storage interface. In some implementations, memory controller 126 includes one or more processing units (sometimes herein called CPUs, processors, or hardware processors, and sometimes implemented using microprocessors, microcontrollers, or the like) configured to execute instructions in one or more programs (e.g., in memory controller 126). In some implementations, the one or more processors are shared by one or more components within, and in some instances, beyond the function of memory controller 126.
In some embodiments, the non-volatile memory controllers 130 include management modules 131. In some embodiments, a particular management module 131 (e.g., management module 131-1) comprises management module 121 illustrated in
In some embodiments, memory controller 126 and NVM controllers 130 work in conjunction to perform any of the operations described herein with respect to storage device 120. In some embodiments, management modules 131 work either independently or in conjunction to perform any of the operations described herein with respect to management module 121. In some embodiments, management module 131-1 receives data from memory controller 126 (e.g., host data) and transfers the data to NVM memory (e.g., NVM 134-1). In some embodiments or circumstances, management module 131-1 receives data from another management module 131 (e.g., management module 131-m) and transfers the data to NVM (e.g., NVM 134-n). Additional details regarding the operation of management modules 121 and 131 are described below with respect to
Each of the above identified elements may be stored in one or more of the previously mentioned memory devices, and corresponds to a set of instructions for performing a function described above. The above identified modules or programs (i.e., sets of instructions) need not be implemented as separate software programs, procedures or modules, and thus various subsets of these modules may be combined or otherwise re-arranged in various embodiments. In some embodiments, memory 206 may store a subset of the modules and data structures identified above. Furthermore, memory 206 may store additional modules and data structures not described above. In some embodiments, the programs, modules, and data structures stored in memory 206, or the non-transitory computer-readable storage medium of memory 206, provide instructions for implementing at least some of the methods, or portions of the methods, described herein. In some embodiments, some or all of these modules may be implemented with specialized hardware circuits that subsume part or all of the module functionality.
Although
Each of the above identified elements may be stored in one or more of the previously mentioned memory devices, and corresponds to a set of instructions for performing a function described above. The above identified modules or programs (i.e., sets of instructions) need not be implemented as separate software programs, procedures or modules, and thus various subsets of these modules may be combined or otherwise re-arranged in various embodiments. In some embodiments, memory 242 may store a subset of the modules and data structures identified above. Furthermore, memory 242 may store additional modules and data structures not described above. In some embodiments, the programs, modules, and data structures stored in memory 242, or the non-transitory computer-readable storage medium of memory 242, provide instructions for implementing at least some portions of the methods described herein. In some embodiments, some or all of these modules may be implemented with specialized hardware circuits that subsume part or all of the module functionality. In some embodiments, the above identified modules and/or programs for
Although
Furthermore, in some embodiments, read operations on the first and last word lines in each zone of a block (excluding blocks at the physical edge of a memory array in a die) are known to cause read disturb effects on data stored in neighboring word lines on both sides of those word lines. Stated another way, a read operation on a first word line at a predefined physical edge of a zone (i.e., a zone of the plurality of zones in a block of the plurality of non-volatile memory blocks) causes read disturb effects on data stored in both that zone and also in a neighboring zone. Depending on the location of the zone in the block, the neighboring zone is either in the same block, or in a neighboring block. For example, with reference to
Furthermore, each block of the plurality of non-volatile memory blocks in storage device 120 has one or two neighbors, depending on the physical location of the block in an NVM die 134. For example, block 0 in
As an example, Tables 1-2 below shows quantitative latency values and error correction times for a read response table (e.g., read response table 502). The values shown in Tables 1 and 2 are prophetic values, for illustrative purposes only. Those skilled in the art will understand that latency values depend on the particular technology used in the storage device. For example, in some instances, the relative latency values between the upper, middle, and lower pages of a storage medium may be 7-9-7, while in other instances, the relative latency values may be 5-9-9.
In some embodiments, read response table 502 comprises a static table, for example populated with values determined by measurements performed on multiple memory devices of the same type as the memory devices in storage medium 132. In some embodiments, read response table 502 is informed/constructed during the production process (e.g., a memory characterization step). In some embodiments, read response table 502 is informed by memory testing and analysis, either during production or post-production. In some embodiments, read response table 502 is updated during use of storage device 120 based on measured characteristics of the storage device's storage medium, such as error rates for particular regions.
As another example, data 570 is received by write buffer 140. Data 570 includes a plurality of portions and each portion of data has an associated predicted read frequency. The portions of data 570 are arranged in write buffer 140 such that the portions with high predicted read frequencies are held in pages within write buffer 140 with high ranks (e.g., Rank 1), while pages with low predicted read frequencies are held in pages with low ranks (e.g., Rank 3). The arranged data 572 in write buffer 140 is then written to the storage medium (e.g., storage medium 132,
In some embodiments, the predicted read frequencies associated with each portion of data are used as suggestions rather than as a directive. In some instances, write conditions and/or constraints prevent optimal data organization within write buffer 140. For example, in some circumstances write buffer 140 may be filled with multiple portions of data that each has an associated predicted read frequency that is very high. In this example, the data is arranged in write buffer 140 such that some of the data with predicted high read frequency is held in pages with low ranks (e.g., rather than wait for data with a low predicted read frequency). In some embodiments, the data arrangement in write buffer 140 is based one or more additional parameters, such as predicted write frequencies, as well as the predicted read frequency.
Read prediction engine 602 outputs write placement instructions 610 corresponding to input data 604. In some embodiments, write placement instructions 610 include a predicted read frequency for input data 604. In some embodiments, write placement instructions 610 include a preferred storage region rank for input data 604. For example, input data 604 has a high predicted read frequency and write placement instructions 610 include the preferred storage region rank as the highest available rank (e.g., Rank 1,
A storage device (e.g., storage device 120,
In some embodiments, the storage device tracks (704) a number of read operations corresponding to a particular region of a plurality of regions in a logical address space of a host. In some embodiments, the number of tracked read operations is used to predict a future read frequency for data in a particular logical address space. In some embodiments, the storage device further tracks a time period for the number of tracked read operations. In some embodiments, the number of tracked read operations and the tracked time period are used to calculate a past read frequency for data in a particular logical address space. Using management module 121 in
The storage device predicts (706) a read frequency for particular data. In some embodiments, the storage device predicts a relative or qualitative read frequency for the particular data (e.g., compared to other data within the storage device). In some embodiments, the storage device predicts a quantitative read frequency for the particular data. In some embodiments, the read frequency is predicted based on an analysis of bit error rates for the particular data during a garbage collection operation. In some embodiments, the analysis of bit error rates is performed by a garbage collection module (e.g., garbage collection module 220,
In some embodiments, the storage device predicts (708) the read frequency for the particular data based on an amount of read disturbs associated with the particular data. For example, if data neighboring the particular data has had a high amount of read disturbs, then the past read frequency for the particular data is presumed to be high, and the future read frequency for the particular data is predicted to be high. As another example, when data is moved due to read disturbs, the storage device infers that the data has been read often and thus predicts that the data will have a high future read frequency. Using management module 121 in
In some embodiments, the storage device obtains (710) read frequency information from the host system and predicts the read frequency for the particular data based on the obtained read frequency information. In some embodiments, the read frequency information includes historical read frequency information for the particular data. In some embodiments, the read frequency information includes a prediction by the host system as to the future read frequency of the particular data. In some embodiments, the read frequency information is obtained from the host with the particular data. In some embodiments, the read frequency information includes a flag, which when set to a predefined value (e.g., “1” or “true”) marks the particular data as hot read data, and when not set to the predefined value (e.g., when set to “0” or “false”) marks the particular data as cold read data. In some embodiments, the read frequency information is sent from the host system as metadata associated with the particular data. Using data storage system 100 in
In some embodiments, the storage device predicts the read frequency for the particular data based on one or more of: (1) an analysis of bit error rates associated with the particular data, (2) an amount of read disturbs associated with the particular data, (3) a tracked number of reads for the particular data, (4) other statistical analysis of the particular data, and (5) read frequency information, predictions, and/or hints received from the host system. In some embodiments, the analysis of bit error rates, amount of read disturbs, and/or number of reads is tracked at the block level (e.g., by determining a single bit error rate, read disturb count and/or number of reads for each block of a plurality of blocks in the storage device). In some embodiments, the analysis of bit error rates, amount of read disturbs, and/or number of reads is tracked at the page level (e.g., by determining a single bit error rate, read disturb count and/or number of reads for each page of a plurality of pages in the storage device). In some embodiments, the analysis of bit error rates, amount of read disturbs, and/or number of reads is tracked at the device level (e.g., by determining a single bit error rate, read disturb count and/or number of reads for each NVM device 134 of a plurality of NVM devices in the storage device).
In some embodiments, the storage device obtains (712) a respective read response parameter for each memory group of a plurality of memory groups in the memory. In some embodiments, the read response parameter comprises a read response rank for the particular memory group. Using management module 121 in
In some embodiments, the read response parameter is based on (714) at least one of: a read latency for the particular memory group; an error rate for the particular memory group; and a word line corresponding to the particular memory group (e.g., an edge word line). In some embodiments, the read response parameter is based on the plane/layer of the particular memory group.
In some embodiments, the plurality of memory groups include one or more groups corresponding to: (1) particular pages in the memory devices of the storage device, (2) particular word lines in the memory devices of the storage device, (3) particular planes or layers in the memory devices of the storage device, (4) particular erase blocks in the memory devices of the storage device, and/or (5) particular superblocks in the memory devices of the storage device. In some embodiments, the read response parameter is based on one or more additional metrics, such as voltage levels, age, and the like. In some embodiments, the read response parameter is based on an error correction time for the particular memory group (e.g., an average error correction time). In some embodiments, the read latency for the particular memory group includes an average latency value. In some embodiments, the read latency for the particular memory group includes a peak latency value. In some embodiments, the error rate for the particular memory group is an average error rate. In some embodiments, the error rate for the particular memory group is a peak error rate. Using management module 121 in
In some embodiments, each memory group of the plurality of memory groups corresponds to (716) a particular memory page type. In some embodiments, each memory group in at least a subset of the plurality of memory groups corresponds to a particular memory page type. In some embodiments, the memory page types include lower pages, middle pages, and upper pages. Using read response table 502 in
In some embodiments, the storage device maps (717) the predicted read frequency to a particular read response parameter value. For example, the storage device predicts a high read frequency for the particular data and maps that to a high read response rank 510 (
In some embodiments, the mapping comprises a linear mapping (e.g., as illustrated in Table 3). In some embodiments, the mapping comprises a non-linear mapping. Using management module 121 in
In some embodiments, the storage device compares (718) the particular read response parameter value to the respective read response parameter for a particular memory group, the particular memory group including a preferred storage location. Using data storage system 100 in
Based on the predicted read frequency, the storage device determines (720) one or more preferred storage locations within the memory. In some embodiments, the storage device determines the one or more preferred storage locations by mapping the predicted read frequency to one or more read response categories and identifying storage locations having the one or more read response categories. Using management module 121 in
In some embodiments, the predicted read frequency indicates (722) that the particular data is hot read data and the one or more preferred storage locations are denoted as having a fast read response. In some embodiments, hot read data is data that will be (or is predicted to be) read more frequently than average read data. In some embodiments, hot read data is data that meets certain read frequency criteria. In some embodiments, data is designated as hot read data if the predicted read frequency corresponds to the highest category of relative or absolute read frequencies. In some embodiments, data is designated as hot read data if the predicted read frequency meets certain predefined criteria. In some embodiments, the particular data is designated as hot read data by the host system, and this designation is used in predicting the read frequency for the particular data. In some embodiments, the one or more preferred storage locations are denoted as being in the highest category (or one of the highest categories) of read response times. As an example in reference to Table 3 above, the predicted read frequency for the particular data is a “High Read Frequency” and the one or more preferred storage locations have the “Fastest Read Response.” As another example in reference to Table 3 above, data having a “High Read Frequency” is denoted as hot read data.
In some embodiments, the storage device determines (724) at least one preferred storage location based on the comparison of the particular read response parameter value to the read response parameter for the particular memory group. In some embodiments, determination (724) is based on comparison (718) discussed previously. Using management module 121 in
The storage device stores (726) the particular data in a preferred storage location of the one or more preferred storage locations. Using data storage system 100 in
In some embodiments, the storage device holds (728) the particular data at a location within a write buffer corresponding to the preferred storage location and transfers the particular data from the write buffer to the preferred storage location. Using data storage system 100 in
In some embodiments, the storage device obtains (730) read frequency information corresponding to the particular data. In some embodiments, after storing the particular data in the storage medium, the storage device monitors one or more read parameters of the particular data over a period of time and stores the one or more read parameters as read frequency information corresponding to the particular data. In some embodiments, the read frequency information includes one or more of: (1) an analysis of bit error rates associated with the particular data, (2) an amount of read disturbs associated with the particular data, and (3) a tracked number of reads for the particular data. In some embodiments, the read frequency information includes read frequency information received from a host system (e.g., computer system 110,
In some embodiments, the storage device predicts (732) a new read frequency for the particular data based on the obtained read frequency information. In some embodiments, the predicted new read frequency corresponds to a read frequency bucket that is distinct from the read frequency bucket corresponding to the original predicted read frequency. For example, the particular data is initially predicted as having a low read frequency and thus stored in a memory location with a slow read response parameter. New read frequency information for the particular data is analyzed and a new prediction for the particular data indicates that the particular data will have a high future read frequency. In another example, in reference to Table 3 above, the initial predicted read frequency for the particular data is a “High Read Frequency” and the new read frequency for the particular data is “Medium Read Frequency.” Using management module 121 in
In some embodiments, the storage device determines (734) one or more new preferred storage locations within the memory based on the new read frequency prediction, where the one or more new preferred storage locations are distinct from the one or more preferred storage locations. In some embodiments, determination (734) is similar to determination (720) discussed above. Using management module 121 in
In some embodiments, the storage device transfers (736) the particular data to a new preferred storage location of the one or more new preferred storage locations. Using storage device 120-1 in
In some embodiments, the storage device's memory comprises a plurality of non-volatile memory devices (e.g., NVM devices 134 and 138,
In some embodiments, the storage device's memory comprises one or more three-dimensional (3D) memory devices, and where the storage device further comprises circuitry associated with operation of memory elements in one or more 3D memory devices.
In some embodiments, the storage device's circuitry and one or more memory elements in a respective 3D memory device of the one or more 3D memory devices are on the same substrate.
In some embodiments, method 800 is performed by a storage system (e.g., data storage system 100,
A storage device (e.g., storage device 120,
The storage device predicts (804) a read frequency for the data. In some embodiments, prediction (804) is similar to prediction (706) discussed previously. Using management module 121 in
Based on the predicted read frequency for the data, the storage device determines (806) one or more preferred storage locations within memory. In some embodiments, determination (806) is similar to determination (720) discussed previously. Using management module 121 in
Based on one or more write conditions, the storage device stores (808) the data in a location in memory other than the one or more preferred storage locations. Using write buffer 140 in
In some embodiments, the storage device obtains data from multiple sources prior to writing the data to non-volatile memory. For example, the storage device obtains data from multiple sources to fill a write buffer (e.g., write buffer 140,
Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.
The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.
Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.
The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.
In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.
The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.
A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).
As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration (e.g., in an x-z plane), resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.
By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device level. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.
Then again, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.
Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.
The term “three-dimensional memory device” (or 3D memory device) is herein defined to mean a memory device having multiple memory layers or multiple levels (e.g., sometimes called multiple memory device levels) of memory elements, including any of the following: a memory device having a monolithic or non-monolithic 3D memory array, some non-limiting examples of which are described above; or two or more 2D and/or 3D memory devices, packaged together to form a stacked-chip memory device, some non-limiting examples of which are described above. Additional information regarding the structure and operation of 3D memory devices is discussed in application Ser. No. 14/543,813, entitled “Method and System for Dynamic Word Line Based Configuration of a Three-Dimensional Memory Device,” which is hereby incorporated by reference in its entirety.
One of skill in the art will recognize that this invention is not limited to the two dimensional and three dimensional exemplary structures described but cover all relevant memory structures within the spirit and scope of the invention as described herein and as understood by one of skill in the art.
It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first region could be termed a second region, and, similarly, a second region could be termed a first region, without changing the meaning of the description, so long as all occurrences of the “first region” are renamed consistently and all occurrences of the “second region” are renamed consistently. The first region and the second region are both regions, but they are not the same region. It will be further understood that the term “exemplar” as used herein means an object serving as an illustrative example, but does not mean that the object is the only example or the best example.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. As used in the description of the embodiments and the appended claims, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in accordance with a determination” or “in response to detecting,” that a stated condition precedent is true, depending on the context. Similarly, the phrase “if it is determined [that a stated condition precedent is true]” or “if [a stated condition precedent is true]” or “when [a stated condition precedent is true]” may be construed to mean “upon determining” or “in response to determining” or “in accordance with a determination” or “upon detecting” or “in response to detecting” that the stated condition precedent is true, depending on the context.
The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain principles of operation and practical applications, to thereby enable others skilled in the art.
