Systems and methods for pattern dependent target adaptation

Abstract

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise predictive filter circuit, a data detector circuit, and a first and a second pattern dependent adaptive target circuits. The noise predictive filter circuit includes at least a first pattern dependent filter circuit operable to perform noise predictive filtering on a data input for a first pattern using a first adaptive target to yield a first noise predictive output, and a second pattern dependent filter circuit operable to perform noise predictive filtering on the data input for a second pattern using a second adaptive target to yield a second noise predictive output. The data detector circuit is operable to apply a data detection algorithm to the first noise predictive output and the second noise predictive output to yield a detected output. The first pattern dependent adaptive target circuit is operable to adaptively calculate the first adaptive target based at least in part on the first noise predictive output and a training sequence. The second pattern dependent adaptive target circuit operable to adaptively calculate the second adaptive target based at least in part on the second noise predictive output and the training sequence.

Description

BACKGROUND OF THE INVENTION

The present invention is related to systems and methods for data processing, and more particularly to systems and methods for noise predictive filtering in data processing.

Data processing circuits often include a data detector circuit including noise predictive filtering. The noise predictive filtering includes a number of pattern dependent filters that use a common output from the data detector circuit to select one target used by all of the pattern dependent filters. In some cases, the identified target is less than ideal resulting in a degraded operation of the associated data processing circuit.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for data processing.

BRIEF SUMMARY OF THE INVENTION

The present invention is related to systems and methods for data processing, and more particularly to systems and methods for noise predictive filtering in data processing.

Various embodiments of the present invention provide data processing circuits that include: a noise predictive filter circuit, a data detector circuit, and a first and a second pattern dependent adaptive target circuits. The noise predictive filter circuit includes at least a first pattern dependent filter circuit operable to perform noise predictive filtering on a data input for a first pattern using a first adaptive target to yield a first noise predictive output, and a second pattern dependent filter circuit operable to perform noise predictive filtering on the data input for a second pattern using a second adaptive target to yield a second noise predictive output. The data detector circuit is operable to apply a data detection algorithm to the first noise predictive output and the second noise predictive output to yield a detected output. The first pattern dependent adaptive target circuit is operable to adaptively calculate the first adaptive target based at least in part on the first noise predictive output and a training sequence. The second pattern dependent adaptive target circuit operable to adaptively calculate the second adaptive target based at least in part on the second noise predictive output and the training sequence.

In some instances of the aforementioned embodiments, the training sequence is a portion of the detected output corresponding to the data input. In other instances of the aforementioned embodiments, the training sequence is a known data set stored in a memory. The data detection algorithm may be, but is not limited to, a Viterbi data detection algorithm or a maximum a posteriori data detection algorithm. Of note, the general phrase “Viterbi data detection algorithm” is used in its broadest sense to mean any Viterbi detection algorithm or variations thereof including, but not limited to, bi-direction Viterbi detection algorithm. Also, the general phase “maximum a posteriori data detection algorithm” is used in its broadest sense to mean any maximum a posteriori detection algorithm or variations thereof including, but not limited to, simplified maximum a posteriori data detection algorithm and a max-log maximum a posteriori data detection algorithm.

In various instances of the aforementioned embodiments, the data processing circuit further includes a data decoding circuit operable to apply a data decode algorithm to the detected output to yield a decoded output. In some cases, the data decode algorithm is a low density parity check algorithm. In particular cases, the data processing circuit further includes: an analog to digital converter circuit operable to convert an analog input into a series of digital samples; and an equalizer circuit operable to receive the series of digital samples and to equalize the series of digital samples to yield the data input.

In some instances of the aforementioned embodiments, adaptively calculating the first adaptive target based at least in part on the first noise predictive output and a training sequence includes multiplying an ideal output by a programmable adaptation gain. In some such instances, the ideal output is calculated in accordance with the following equation:

$\mathrm{ideal}\mathrm{output}=\sum _{j=1}^D{T}_j{b}_{D-j},$ where D is the depth of a pattern, T is the adaptive target, and b is the training sequence.

Other embodiments of the present invention provide methods that include: receiving a data input; pattern dependent filtering the data input using a first pattern dependent filter for a first pattern using a first adaptive target to yield a first noise predictive output; pattern dependent filtering the data input using a second pattern dependent filter for a second pattern using a second adaptive target to yield a second noise predictive output; applying a data detection algorithm to the first noise predictive output and the second noise predictive output to yield a detected output; calculating in a first pattern dependent adaptive target circuit the first adaptive target based at least in part on the first noise predictive output and a training sequence; and calculating in a second pattern dependent adaptive target circuit the second adaptive target based at least in part on the second noise predictive output and the training sequence.

Yet other embodiments of the present invention provide A storage devices that include: a storage medium; a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to information on the storage medium; and a read channel circuit. The read channel circuit includes: an analog to digital converter circuit operable to sample an analog signal derived from the sensed signal to yield a series of digital samples; an equalizer circuit operable to equalize the digital samples to yield an equalized output; a noise predictive filter circuit including at least a first pattern dependent filter circuit operable to perform noise predictive filtering on the equalized output for a first pattern using a first adaptive target to yield a first noise predictive output, and a second pattern dependent filter circuit operable to perform noise predictive filtering on the equalized output for a second pattern using a second adaptive target to yield a second noise predictive output; a data detector circuit operable to apply a data detection algorithm to the first noise predictive output and the second noise predictive output to yield a detected output; a first pattern dependent adaptive target circuit operable to adaptively calculate the first adaptive target based at least in part on the first noise predictive output and a training sequence; and a second pattern dependent adaptive target circuit operable to adaptively calculate the second adaptive target based at least in part on the second noise predictive output and the training sequence.

This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several figures to refer to similar components. In some instances, a sub-label consisting of a lower case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components.

FIG. 1 shows a data processing circuit including multi-pattern noise predictive filter adaptation circuitry in accordance with one or more embodiments of the present invention;

FIG. 2 shows an example trellis diagram of a Viterbi algorithm detection process of which the output is used to adaptively train pattern dependent target values in the data processing circuit of FIG. 1;

FIG. 3 is a flow diagram showing a method in accordance with one or more embodiments of the present invention for pattern dependent target adaptation;

FIG. 4 shows a storage device including a read channel having multi-pattern noise predictive filter adaptation circuitry; and

FIG. 5 shows a data transmission system including a read channel having multi-pattern noise predictive filter adaptation circuitry.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is related to systems and methods for data processing, and more particularly to systems and methods for noise predictive filtering in data processing.

Various embodiments of the present invention provide a noise predictive filter including a bank of pattern dependent filter circuits each operating based upon a respective pattern and governed at least in part by an adaptive target. A respective adaptive target is calculated for each of the pattern dependent filter circuits. Such an approach provides target values adapted for individual pattern dependent filter circuits. By allowing the target values to adjust for a particular pattern dependent filter circuit independent of target values for other pattern dependent filter circuits, the target values more closely adapt actual conditions.

Turning to FIG. 1, a data processing circuit 100 is shown that includes multi-pattern noise predictive filter adaptation circuitry in accordance with some embodiments of the present invention in accordance with some embodiments of the present invention. Data processing circuit 100 includes an analog front end circuit 110 that receives an analog signal 105. Analog front end circuit 110 processes analog signal 105 and provides a processed analog signal 112 to an analog to digital converter circuit 114. Analog front end circuit 110 may include, but is not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog front end circuit 110. In some cases, analog signal 105 is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium (not shown). In other cases, analog signal 105 is derived from a receiver circuit (not shown) that is operable to receive a signal from a transmission medium (not shown). The transmission medium may be wired or wireless. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of source from which analog input 105 may be derived.

Analog to digital converter circuit 114 converts processed analog signal 112 into a corresponding series of digital samples 116. Analog to digital converter circuit 114 may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. Digital samples 116 are provided to an equalizer circuit 120. Equalizer circuit 120 applies an equalization algorithm to digital samples 116 to yield an equalized output 125. In some embodiments of the present invention, equalizer circuit 120 is a digital finite impulse response filter circuit as are known in the art.

Equalized output 125 is provided to a buffer circuit 140 that provides a buffered output 142 to noise predictive filter circuit 130. In particular, buffered output 142 is provided in parallel to a number of pattern dependent filter circuits (P.D.F. Circuit A 132, P.D.F. Circuit B 134, P.D.F. Circuit A 136, P.D.F. Circuit A 138) that are included as part of noise predictive filter circuit 130. Each of the pattern dependent filter circuits is tuned to perform noise predictive filtering for a particular pattern and using an adaptive target. In particular, operation of pattern dependent filter circuit 132 is tuned to a particular pattern and governed at least in part by an adaptive target 179; operation of pattern dependent filter circuit 134 is tuned to another particular pattern and governed at least in part by an adaptive target 177; operation of pattern dependent filter circuit 136 is tuned to another particular pattern and governed at least in part by an adaptive target 175; and operation of pattern dependent filter circuit 138 is tuned to another particular pattern and governed at least in part by an adaptive target 173.

Pattern dependent filter circuit 132 filters buffered output 142 according to a first pattern and governed by adaptive target 179 to yield a noise predictive output 133. Similarly, pattern dependent filter circuit 134 filters buffered output 142 according to a second pattern and governed by adaptive target 177 to yield a noise predictive output 135; pattern dependent filter circuit 136 filters buffered output 142 according to a first pattern and governed by adaptive target 175 to yield a noise predictive output 137; and pattern dependent filter circuit 138 filters buffered output 142 according to a first pattern and governed by adaptive target 173 to yield a noise predictive output 139. Pattern dependent filter circuits 132, 134, 136, 138 may be any filter circuits known in the art that are capable of providing a pattern dependent filtered output using an target input. In one particular embodiment, noise predictive filter circuit 130 includes eight pattern dependent filter circuits each tuned to a different three bit pattern (i.e., ‘000’, ‘001’, ‘010’, ‘011’, ‘100’, ‘101’, ‘110, and ‘111’), and a corresponding number of noise predictive outputs.

Noise predictive outputs 133, 135, 137, 139 are provided to a data detector circuit 150. Data detector circuit 150 applies a data detection algorithm to a selected one of noise predictive outputs 133, 135, 137, 139 to yield a detected output 152. The data detection algorithm may be any data detection algorithm known in the art. In some embodiments of the present invention, the data detection algorithm is a Viterbi algorithm data detection as is known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detection algorithms that may be implemented as part of data detector circuit 150 in accordance with different embodiments of the present invention. Detected output 152 is provided to data decoder circuit 160 that applies a decode algorithm to detected output 152 to yield a decoded output 162. The data decode algorithm may be any data decode algorithm known in the art. In one particular embodiment of the present invention, the data decode algorithm is a low density parity check (LDPC) algorithm as are known in the art.

Where data decoder circuit 160 does not converge (i.e, fails to result in the properly decoded data set), decoded output 162 is fed back to data detector circuit 150 where it is used to guide a subsequent data detection of buffered output 142 by data detector circuit 150. Alternatively, where data decoder circuit 160 converges (i.e, results in the properly decoded data set), decoded output 162 is provided as an output from data processing circuit 100.

As shown in FIG. 2, an example trellis diagram 200 of a Viterbi algorithm detection process. Each path of trellis diagram 200 corresponds to a bit sequence. The ideal sample is bit sequence or pattern dependent, and the mean variance of the noise for each path is different and will affected by a training bit sequence 190. In some embodiments of the present invention, training bit sequence 190 may be detected output 152 or may be a canned expected data set. Since trellis diagram 200 is pattern dependent, each of noise predictive outputs 133, 135, 137, 139 are used for two of the path metrics within data detector circuit 150. The two paths corresponding to a noise predictive output corresponding to the ‘000’ pattern are shown on trellis diagram 200 (i.e., the two four bit paths ending in ‘000’). Where there are eight noise predictive outputs (e.g., noise predictive output 133, 135, 137, 139), there are a total of sixteen (2*8) path metrics.

Returning to FIG. 1, pattern dependent adaptive target circuit 178, pattern dependent adaptive target circuit 176, dependent adaptive target circuit 174, pattern dependent adaptive target circuit 172 each use channel statistics and training sequence 190 to more accurately tune adaptive target 179, adaptive target 177, adaptive target 175, and adaptive target 173, respectively. In particular, each of the pattern dependent adaptive target circuits calculates an error as a squared difference between a respective noise predictive output (i.e., noise predictive outputs 133, 135, 137, 139) and an ideal output as set forth in the following equation:error=(noise predictive output−ideal output)².The ideal output is calculated in accordance with the following equation:

$\mathrm{ideal}{\mathrm{output}}_i=\sum _{j=1}^D{T}_{i,j}{b}_{D-j},$ where i corresponds to a particular one of pattern dependent adaptive target circuits (pattern dependent adaptive target circuit 178, pattern dependent adaptive target circuit 176, pattern dependent adaptive target circuit 174, or pattern dependent adaptive target circuit 172); D is the depth of the path (i.e., the number of bits in the pattern). T is the adaptive target that is provided by the particular pattern dependent adaptive target circuit provided to the corresponding pattern dependent filter circuit. b is the corresponding portion of training bit sequence 190. Using this ideal output, the error is calculated in accordance with the following equation:

$\mathrm{error}={\left(\mathrm{noise}\mathrm{predictive}\mathrm{output}-\sum _{j=1}^D{T}_{i,j}{b}_{D-j}\right)}^2.$ A scaled derivative of the error is set forth in the following equation:

$\frac{\partial \mathrm{error}}{\partial T_{i,j}}=-\eta *b_{D-j}\times \left(\mathrm{noise}\mathrm{predictive}\mathrm{output}-\sum _{j=1}^D{T}_{i,j}{b}_{D-j}\right).$ η is a programmable adaptation gain. Adaptively resolving this equation results in values of an adaptive target provided to a corresponding pattern dependent filter circuit. Adaptive resolution is done using the following equation:

$T_{i,j}\left(\mathrm{Next}\mathrm{Period}\right)=T_{i,j}\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{noise}\mathrm{predictive}\mathrm{output}-\sum _{j=1}^D{T}_{i,j}{b}_{D-j}\right).$ In some cases, initially T1 may be set to a value of ‘1’, and T2 and T3 are each initially set to a value of ‘0’.

As set forth above, the target adaptation is pattern dependent. As an example, the adaptation of the respective target values may proceed as:

• • (A) The first noise predictive output (i.e., noise predictive output 133 from pattern dependent filter circuit 132) is used to train the target corresponding to paths ‘0000’ and ‘1000’ of the Viterbi trellis; the second noise predictive output is used to train the target corresponding to paths ‘0001’ and ‘1001’ of the Viterbi trellis; the third noise predictive output is used to train the target corresponding to paths ‘0010’ and ‘1010’ of the Viterbi trellis; the fourth noise predictive output is used to train the target corresponding to paths ‘0011’ and ‘1011’ of the Viterbi trellis; the fifth noise predictive output is used to train the target corresponding to paths ‘0100’ and ‘1100’ of the Viterbi trellis; the sixth noise predictive output (i.e., noise predictive output 135 from pattern dependent filter circuit 134) is used to train the target corresponding to paths ‘0101’ and ‘1101’ of the Viterbi trellis; the seventh noise predictive output (i.e., noise predictive output 137 from pattern dependent filter circuit 136) is used to train the target corresponding to paths ‘0110’ and ‘1110’ of the Viterbi trellis; and the eighth noise predictive output (i.e., noise predictive output 139 from pattern dependent filter circuit 138) is used to train the target corresponding to paths ‘0111’ and ‘1111’ of the Viterbi trellis.
  • (B) The adaptive algorithm set forth above is applied for each pattern dependent filter circuit of noise predictive filter circuit 130.

Using pattern dependent adaptive target circuit 178 as an example, the following equation is used to adaptively calculate adaptive target 179 (T1, T2, T3):adaptive target 179=T1,T2,T3(Next Period)=

$T1,T2,T3\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{noise}\mathrm{predictive}\mathrm{output}133-\sum _{j=1}^D{T}_j{b}_{D-j}\right).$ Similarly, using pattern dependent adaptive target circuit 176 as an example, the following equation is used to adaptively calculate adaptive target 177 (T1, T2, T3):adaptive target 177=T1,T2,T3(Next Period)=

$T1,T2,T3\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{noise}\mathrm{predictive}\mathrm{output}135-\sum _{j=1}^D{T}_j{b}_{D-j}\right);$ using pattern dependent adaptive target circuit 174 as an example, the following equation is used to adaptively calculate adaptive target 177 (T1, T2, T3):adaptive target 175=T1,T2,T3(Next Period)=

$T1,T2,T3\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{noise}\mathrm{predictive}\mathrm{output}137-\sum _{j=1}^D{T}_j{b}_{D-j}\right);$ andadaptive target 173=T1,T2,T3(Next Period)=

$T1,T2,T3\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{noise}\mathrm{predictive}\mathrm{output}139-\sum _{j=1}^D{T}_j{b}_{D-j}\right).$

Such an approach provides target values adapted for individual pattern dependent filter circuits. By allowing the target values to adjust for a particular pattern dependent filter circuit independent of target values for other pattern dependent filter circuits, the target values more closely adapt actual conditions.

Turning to FIG. 3, a flow diagram 300 shows a method in accordance with one or more embodiments of the present invention for pattern dependent target adaptation. Following flow diagram 300, an analog input signal is received (block 305). The analog input may be derived from, for example, a storage medium or a data transmission channel. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources of the analog input. The analog input is converted to a series of digital samples (block 510). This conversion may be done using an analog to digital converter circuit or system as are known in the art. Of note, any circuit known in the art that is capable of converting an analog signal into a series of digital values representing the received analog signal may be used. The resulting digital samples are equalized to yield an equalized output (block 515). In some embodiments of the present invention, the equalization is done using a digital finite impulse response circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of equalizer circuits that may be used in place of such a digital finite impulse response circuit to perform equalization in accordance with different embodiments of the present invention. Of note, the equalized output may include both electronic noise and media noise.

Noise predictive filtering is applied to the equalized output (block 320). In particular, pattern dependent filtering on the equalized output is performed for a first pattern (e.g., ‘000’) using a first target to yield a first noise predictive output, pattern dependent filtering on the equalized output is performed for a second pattern (e.g., ‘001’) using a second target to yield a second noise predictive output, pattern dependent filtering on the equalized output is performed for a third pattern (e.g., ‘010’) using a third target to yield a third noise predictive output, pattern dependent filtering on the equalized output is performed for a fourth pattern (e.g., ‘011’) using a fourth target to yield a fourth noise predictive output, pattern dependent filtering on the equalized output is performed for a fifth pattern (e.g., ‘100’) using a fifth target to yield a fifth noise predictive output, pattern dependent filtering on the equalized output is performed for a sixth pattern (e.g., ‘101’) using a sixth target to yield a sixth noise predictive output, pattern dependent filtering on the equalized output is performed for a seventh pattern (e.g., ‘110’) using a seventh target to yield a seventh noise predictive output, and pattern dependent filtering on the equalized output is performed for a eighth pattern (e.g., ‘111’) using an eighth target to yield an eighth noise predictive output. Of note, flow diagram 300 is described as including eight pattern dependent filter circuits, but other embodiments of the present invention may be implemented to include more or fewer than eight pattern dependent filter circuits.

A data detection is performed using the eight noise predictive outputs to yield a detected output (block 325). In some embodiments of the present invention, the data detection is a Viterbi algorithm data detection as is known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other data detection algorithms that may be used in relation to different embodiments of the present invention. Data decoding is applied to the detected output to yield a decoded output (block 335). The decoding algorithm may be, but is not limited to, a low density parity check decoding algorithm as are known in the art. It is determined whether the decoding converged (block 340). Where the decode algorithm converged (i.e., there are no remaining unsatisfied checks)(block 340), the decoded output is provided as a data output (block 345). Alternatively, where the data decoding algorithm failed to converge (i.e., there are remaining unsatisfied checks) (block 340), the decoded output is provided to guide a subsequent performance of the data detection algorithm to yield an updated detected output (block 325).

The detected output and the eight noise predictive outputs are used to calculate updated target values (block 330). In particular, an updated first target is calculated in accordance with the following equation:

$\mathrm{First}\mathrm{Target}=T1,T2,T3\left(\mathrm{Next}\mathrm{Period}\right)=T1,T2,T3\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{First}\mathrm{noise}\mathrm{predictive}\mathrm{output}-\sum _{j=1}^D{T}_j{b}_{D-j}\right);$ an updated second target is calculated in accordance with the following equation:

$\mathrm{Second}\mathrm{Target}=T1,T2,T3\left(\mathrm{Next}\mathrm{Period}\right)=T1,T2,T3\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{Second}\mathrm{noise}\mathrm{predictive}\mathrm{output}-\sum _{j=1}^D{T}_j{b}_{D-j}\right);$ an updated third target is calculated in accordance with the following equation:

$\mathrm{Third}\mathrm{Target}=T1,T2,T3\left(\mathrm{Next}\mathrm{Period}\right)=T1,T2,T3\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{Third}\mathrm{noise}\mathrm{predictive}\mathrm{output}-\sum _{j=1}^D{T}_j{b}_{D-j}\right);$ an updated fourth target is calculated in accordance with the following equation:

$\mathrm{Fourth}\mathrm{Target}=T1,T2,T3\left(\mathrm{Next}\mathrm{Period}\right)=T1,T2,T3\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{Fourth}\mathrm{noise}\mathrm{predictive}\mathrm{output}-\sum _{j=1}^D{T}_j{b}_{D-j}\right);$ an updated fifth target is calculated in accordance with the following equation:

$\mathrm{Fifth}\mathrm{Target}=T1,T2,T3\left(\mathrm{Next}\mathrm{Period}\right)=T1,T2,T3\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{Fifth}\mathrm{noise}\mathrm{predictive}\mathrm{output}-\sum _{j=1}^D{T}_j{b}_{D-j}\right);$ an updated sixth target is calculated in accordance with the following equation:

$\mathrm{Sixth}\mathrm{Target}=T1,T2,T3\left(\mathrm{Next}\mathrm{Period}\right)=T1,T2,T3\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{Sixth}\mathrm{noise}\mathrm{predictive}\mathrm{output}-\sum _{j=1}^D{T}_j{b}_{D-j}\right);$ an updated seventh target is calculated in accordance with the following equation:

$\mathrm{Seventh}\mathrm{Target}=T1,T2,T3\left(\mathrm{Next}\mathrm{Period}\right)=T1,T2,T3\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{Seventh}\mathrm{noise}\mathrm{predictive}\mathrm{output}-\sum _{j=1}^D{T}_j{b}_{D-j}\right);$ and an updated eighth target is calculated in accordance with the following equation:

$\mathrm{Eighth}\mathrm{Target}=T1,T2,T3\left(\mathrm{Next}\mathrm{Period}\right)=T1,T2,T3\left(\mathrm{Prior}\mathrm{Period}\right)-\eta *b_{D-j}\times \left(\mathrm{Eighth}\mathrm{noise}\mathrm{predictive}\mathrm{output}-\sum _{j=1}^D{T}_j{b}_{D-j}\right).$ These updated target values are used to perform a subsequent noise predictive filtering (block 320). In some cases, initially T1 may be set to a value of ‘1’, and T2 and T3 are each initially set to a value of ‘0’.

As set forth above, the target adaptation is pattern dependent. As an example, the adaptation of the respective target values may proceed as:

• • (A) The first noise predictive output is used to train the target corresponding to paths ‘0000’ and ‘1000’ of the Viterbi trellis; the second noise predictive output is used to train the target corresponding to paths ‘0001’ and ‘1001’ of the Viterbi trellis; the third noise predictive output is used to train the target corresponding to paths ‘0010’ and ‘1010’ of the Viterbi trellis; the fourth noise predictive output is used to train the target corresponding to paths ‘0011’ and ‘1011’ of the Viterbi trellis; the fifth noise predictive output is used to train the target corresponding to paths ‘0100’ and ‘1100’ of the Viterbi trellis; the sixth noise predictive output is used to train the target corresponding to paths ‘0101’ and ‘1101’ of the Viterbi trellis; the seventh noise predictive output is used to train the target corresponding to paths ‘0110’ and ‘1110’ of the Viterbi trellis; and the eighth noise predictive output is used to train the target corresponding to paths ‘0111’ and ‘1111’ of the Viterbi trellis.
  • (B) The adaptive algorithm set forth above is applied for each pattern dependent filter circuit of the noise predictive filter circuit.

Turning to FIG. 4, a storage system 400 including a read channel circuit 410 including a multi-pattern noise predictive filter adaptation circuitry is shown in accordance with some embodiments of the present invention. Storage system 400 may be, for example, a hard disk drive. Storage system 400 also includes a preamplifier 470, an interface controller 420, a hard disk controller 466, a motor controller 468, a spindle motor 472, a disk platter 478, and a read/write head assembly 476. Interface controller 420 controls addressing and timing of data to/from disk platter 478. The data on disk platter 478 consists of groups of magnetic signals that may be detected by read/write head assembly 476 when the assembly is properly positioned over disk platter 478. In one embodiment, disk platter 478 includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.

In a typical read operation, read/write head assembly 476 is accurately positioned by motor controller 468 over a desired data track on disk platter 478. Motor controller 468 both positions read/write head assembly 476 in relation to disk platter 478 and drives spindle motor 472 by moving read/write head assembly to the proper data track on disk platter 478 under the direction of hard disk controller 466. Spindle motor 472 spins disk platter 478 at a determined spin rate (RPMs). Once read/write head assembly 478 is positioned adjacent the proper data track, magnetic signals representing data on disk platter 478 are sensed by read/write head assembly 476 as disk platter 478 is rotated by spindle motor 472. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter 478. This minute analog signal is transferred from read/write head assembly 476 to read channel circuit 410 via preamplifier 470. Preamplifier 470 is operable to amplify the minute analog signals accessed from disk platter 478. In turn, read channel circuit 410 decodes and digitizes the received analog signal to recreate the information originally written to disk platter 478. This data is provided as read data 403 to a receiving circuit. A write operation is substantially the opposite of the preceding read operation with write data 401 being provided to read channel circuit 410. This data is then encoded and written to disk platter 478.

During a read operation, data received from preamplifier circuit 470 is converted from an analog signal to a series of corresponding digital samples, and the digital samples are equalized to yield an equalized output. The equalized output is then provided to a noise predictive filter circuit that includes a number of pattern dependent filter circuits. The output from the pattern dependent filter circuits are used in relation to a data detection algorithm to yield a detected output. The multi-pattern noise predictive filter adaptation circuitry is operable to adaptively train a respective target for each of the pattern dependent filter circuits. The multi-pattern noise predictive filter adaptation circuitry may be implemented similar to that described above in relation to FIG. 1 and/or operates similar to the method discussed above in relation to FIG. 3.

It should be noted that storage system 400 may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. It should also be noted that various functions or blocks of storage system 100 may be implemented in either software or firmware, while other functions or blocks are implemented in hardware.

Turning to FIG. 5, a data transmission system 500 including a receiver 520 having multi-pattern noise predictive filter adaptation circuitry is shown in accordance with some embodiments of the present invention. Data transmission system 500 includes a transmitter 510 that is operable to transmit encoded information via a transfer medium 530 as is known in the art. The encoded data is received from transfer medium 530 by receiver 520. Receiver 520 incorporates multi-pattern noise predictive filter adaptation circuitry. While processing received data, an analog signal is converted to a series of corresponding digital samples, and the digital samples are equalized to yield an equalized output. The equalized output is then provided to a noise predictive filter circuit that includes a number of pattern dependent filter circuits. The output from the pattern dependent filter circuits are used in relation to a data detection algorithm to yield a detected output. The multi-pattern noise predictive filter adaptation circuitry is operable to adaptively train a respective target for each of the pattern dependent filter circuits. The multi-pattern noise predictive filter adaptation circuitry may be implemented similar to that described above in relation to FIG. 1 and/or operates similar to the method discussed above in relation to FIG. 3.

It should be noted that the various blocks discussed in the above application may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or only a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.

In conclusion, the invention provides novel systems, devices, methods and arrangements for data processing. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

1. A data processing system, the data processing circuit comprising: a noise predictive filter circuit including at least a first pattern dependent filter circuit operable to perform noise predictive filtering on a data input for a first pattern using a first adaptive target to yield a first noise predictive output, and a second pattern dependent filter circuit operable to perform noise predictive filtering on the data input for a second pattern using a second adaptive target to yield a second noise predictive output;data detector circuit operable to apply a data detection algorithm to the first noise predictive output and the second noise predictive output to yield a detected output;a first pattern dependent adaptive target circuit operable to adaptively calculate the first adaptive target based at least in part on the first noise predictive output and a training sequence including multiplying an ideal output by a programmable adaptation gain; anda second pattern dependent adaptive target circuit operable to adaptively calculate the second adaptive target based at least in part on the second noise predictive output and the training sequence.

2. The data processing system of claim 1, wherein the training sequence is a portion of the detected output corresponding to the data input.

3. The data processing system of claim 1, wherein the training sequence is a known data set stored in a memory.

4. The data processing system of claim 1, wherein the data detection algorithm is selected from a group consisting of: a Viterbi data detection algorithm, and a maximum a posteriori data detection algorithm.

5. The data processing system of claim 1, wherein the data processing circuit further comprises: a data decoding circuit operable to apply a data decode algorithm to the detected output to yield a decoded output.

6. The data processing system of claim 5, wherein the data decode algorithm is a low density parity check algorithm.

7. The data processing system of claim 1, wherein the data processing circuit further comprises: an analog to digital converter circuit operable to convert an analog input into a series of digital samples; andan equalizer circuit operable to receive the series of digital samples and to equalize the series of digital samples to yield the data input.

8. The data processing system of claim 1, wherein the data processing circuit is implemented as part of a device selected from a group consisting of: a storage device and a receiving device.

9. The data processing system of claim 1, wherein the data processing circuit is implemented as part of an integrated circuit.

10. The data processing system of claim 1, wherein the ideal output is calculated in accordance with the following equation:

11. A method, the method comprising: receiving a data input;pattern dependent filtering the data input using a first pattern dependent filter for a first pattern using a first adaptive target to yield a first noise predictive output;pattern dependent filtering the data input using a second pattern dependent filter for a second pattern using a second adaptive target to yield a second noise predictive output;applying a data detection algorithm to the first noise predictive output and the second noise predictive output to yield a detected output;calculating in a first pattern dependent adaptive target circuit the first adaptive target based at least in part on the first noise predictive output and a training sequence including multiplying an ideal output by a programmable adaptation gain; andcalculating in a second pattern dependent adaptive target circuit the second adaptive target based at least in part on the second noise predictive output and the training sequence.

12. The method of claim 11, herein the ideal output is calculated in accordance with the following equation:

13. The method of claim 11, wherein the method further comprises: applying a low density parity check algorithm to the detected output to yield a decoded output.

14. The method of claim 11, wherein the data detection algorithm is selected from a group consisting of: a Viterbi data detection algorithm, and a maximum a posteriori data detection algorithm.

15. The method of claim 11, wherein the training sequence is a portion of the detected output corresponding to the data input.

16. The method of claim 11, wherein the training sequence is a known data set stored in a memory.

17. A storage device, the storage device comprising: a storage medium;a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to information on the storage medium;a read channel circuit including:an analog to digital converter circuit operable to sample an analog signal derived from the sensed signal to yield a series of digital samples;an equalizer circuit operable to equalize the digital samples to yield an equalized output;a noise predictive filter circuit including at least a first pattern dependent filter circuit operable to perform noise predictive filtering on the equalized output for a first pattern using a first adaptive target to yield a first noise predictive output, and a second pattern dependent filter circuit operable to perform noise predictive filtering on the equalized output for a second pattern using a second adaptive target to yield a second noise predictive output;a data detector circuit operable to apply a data detection algorithm to the first noise predictive output and the second noise predictive output to yield a detected output;a first pattern dependent adaptive target circuit operable to adaptively calculate the first adaptive target based at least in part on the first noise predictive output and a training sequence including multiplying an ideal output by a programmable adaptation gain; anda second pattern dependent adaptive target circuit operable to adaptively calculate the second adaptive target based at least in part on the second noise predictive output and the training sequence.

18. The storage device of claim 17, wherein the training sequence is a portion of the detected output corresponding to the data input.

19. The storage device of claim 17, wherein the training sequence is a known data set stored in a memory.

20. The storage device of claim 17, wherein the storage further comprises: a data decoding circuit operable to apply a low density parity check algorithm to the detected output to yield a decoded output.