Patent Application
20130151877
The introduction of multi-core sockets integrating a higher number of memory channels and central processing unit (CPU) cores than in traditional CPUs is driving a need to operate servers at an efficient point for power savings. As servers are configured with an increasing memory capacity for Internet and/or software virtualization applications, customers are demanding improvement in power efficiency that can translates into costs savings.
In the example of
During operation of the associated computer system, the computer component 12 can include controls configured to selectively activate and deactivate the functional component(s) 16. For instance, the activation and deactivation of the functional component(s) 16 can vary based on the current operational status of the computer system.
By way of example, for situation where the computer component 12 is configured as a processor, such that the functional component(s) 16 are processor cores, the computer component 12 may be configured to switch one or more of the processor cores from an idle mode to an active mode during increased processing operations. Similarly, where the computer component 12 is configured as a memory system, such that the functional component(s) 16 are memory modules, the computer component 12 can include controls configured to activate one or more memory channels and memory modules, depending on the application, such as to store large amounts of data. Additionally, where the computer component 12 is configured as an I/O system, such that the functional component(s) 16 are I/O modules, the computer component 12 can include controls configured to activate one or more of the I/O modules to implement specific functions of the associated computer system. Additionally or alternatively, the functional component(s) can correspond to embedded functionality of the computer component 12 that affects the power demand of the computer component 12. That is, the functional component(s) 16 are not limited to separate subcomponents of the computer component 12 that can be selectively activated; deactivated as mentioned in the preceding example. Regardless of how the functional component(s) is implemented, the power demand of the computer component 12 can change significantly over a given span of operating time.
In the example of
Additionally, the VRD system 14 can be configured to selectively enable and disable the power phases 18 based on the power demand of the computer component 12 during operation of the computer component 12. Thus, the VRD system 14 can dynamically respond to the power demands of the computer component 12. As a result, the VRD system 14 can provide power efficiently in manner based on the power demand of the computer component 12. As described herein, an efficient manner can correspond to providing an output current associated with the voltage VCOMP, which depends on the number of power phases 18 that are enabled by the VRD system 14, to provide a high efficiency within defined operating parameters.
In the example of
As a further example, to help conserve space and available pins between circuit packages that comprise the computer component 12 and/or the VRD system 4, the signal POWDEM can be communicated over a single conductor. As an example, the signal POWDEM can be an analog voltage signal having a magnitude that corresponds to the number of power phases 18 to be selectively enabled by the VRD system 14. As another example, the signal POWDEM can be a single conductor digital signal, such as a pulse-width modulated signal having a duty-cycle that corresponds to the number of power phases 18 to be selectively enabled by the VRD system 14. However, the signal POWDEM can be configured as other types of signals instead. For example, the signal POWDEM can be configured as a set of interrupt signals, a combination of signals reflecting different power states, or one or more voltage identification digital (VID) signals.
As described herein, to provide power efficiently to the computer component 12 based on the power demand of the computer component 12, the VRD system 14 can dynamically enable and disable the power phases 18, and thus dynamically adjust the magnitude of the current associated with the voltage VCOMP, in a predictive manner. The VRD system 14 can adjust the magnitude of the current associated with the voltage VCOMP to meet the power demand before the functional component(s) 16 that necessitate the change in power demand are activated or deactivated. For instance, controls in the computer component 12 can anticipate a change in activation (or deactivation) of the functional component(s) for a predetermined time from when the (POWDEM) signal is provided to the VRD system 14. This delay can be small enough as to not impact the overall performance of the associated computer system to allow sufficient time for the VRD system to enable and/or disable one or more phases according to the signal POWDEM.
By way of further example, the power demand logic can employ a look-up table or other structure (e.g., hardware look table or other logic structure) that is configured to determine a value of the power demand signal POWDEM. The value of the power demand signal POWDEM can thus be used to control the VRD system 14 to change the power delivery based on the change to the associated current corresponding to the voltage VCOMP, which that can efficiently power the computer component in response to amount of functional components (e.g., functionality) being requested. For instance, the look-up table can be programmed with a plurality of values for the power demand signal POWDEM according to system design and application requirements. Each value of the signal POWDEM can be used to activate a predetermined number of power phases designed to power the computer component 12 at or above a predetermined efficiency level.
In this way, the VRD system 14 can provide power efficiently to the computer component 12 with substantially no voltage droop of the voltage VCOMP. Accordingly, the power management system 10 can substantially mitigate the chance of a fault that could shut down one or more of the power phases 18 in response to temporarily not being able to meet the power demand, such as based on adjusting the power delivery in a reactive manner, as opposed to the predictive manner described herein. Such delay can be fixed or it may vary according to application design requirements. In addition, the predictive adjustment to power delivery can be performed in real time so as to not affect performance of the associated computer system.
The computer component 50 includes a request component 52. The request component 52 can be configured to selectively activate and deactivate one or more functional components 54, similar to as described above in the example of
As mentioned above, for example, the functional component(s) 54 can be a plurality of core processors, a plurality of memory controllers and associated memory modules, or a plurality of I/O modules in the example of the computer component 50 being configured as a processor, a memory system, or an I/O system, respectively. The request component 52 can be configured as any of a variety of circuits, such as a memory queue configured to queue activation and/or deactivation of the functional component(s) 54, a processor task dispatcher configured to selectively enable one or more processor cores, or a controller (e.g., an I/O controller) configured to activate and/or deactivate the functional component(s) 54. The request component 52 can thus generate a respective one or more control signals CTRL in response to the request signal(s) REQ to selectively activate or deactivate of the functional component(s) 54 in accordance with the request signal(s) REQ. For the example where the computer component 50 is a memory system, the control signal CTRL can be provided in response to a request to activate one or more chip select (CS) signals (e.g., based on the request signal(s) REQ), such that each of the CS signals corresponds to activation of a respective DIMM.
In the example of
As an example, the request signal(s) REQ can simply be configured as an early indication of further activation of one or more functional components 54. As an example, the power demand logic 56 can be configured to generate the signal POWDEM, such that the relative timing between the generation of the signal POWDEM and the control signal(s) CTRL can be carefully controlled by the power demand logic 56. However, while the example of
The power demand logic 56 thus allows rapid adjustments to switching a number of the power phases 18 for the power provided to the computer component 50, while still allowing fast operation of the associated computer system without compromising performance. For instance, by implementing the power demand logic 56 as gate logic, such as within the request component 52, the power demand logic 56 provides a hardware solution for adjustment to the new power demand in terms of increased current delivered by activating one or more power phases 18 when one or more functional components 54 are activated, which can function with greater speed when compared to a software solution. Because of the fast changes in activation and deactivation of functional components 54, a software solution would operate in a significantly slower manner to achieve the same results and therefore would greatly affect the overall system performance. Furthermore, if the value of signal POWDEM was the result of a software function, the transient current demand from computer components 50 would be significantly slow to respond, resulting in disabling faults of the associated VRD system. Accordingly, the power demand logic 56 in the example of
It is to be understood that the power management system 10 and the computer component 50 are not limited to the examples of
At a time T0, the voltage POWDEM has a magnitude of V1, such that a single one of the power phases 18 can be enabled to generate the required current for the voltage POWDEM. At a time T1, the voltage POWDEM increases to V2. As an example, the increase in the magnitude of the voltage POWDEM can be as a result of one or more additional functional components 54 being activated. At a time T2, the voltage POWDEM increases in magnitude from V2 to V4. Similar to as described above, the increase in the magnitude of the voltage POWDEM can be a result of a request of activation of one or more additional functional components 54. However, because the power management system 10 manages power in a predictive manner, the VRD system 14 can enable multiple power phases (e.g., two at the time T2) at one time in response to anticipated large increases in the power demand as indicated by the signal POWDEM. Thus, the voltage VCOMP does not experience voltage droop and the VRD system 14 can adjust dynamically for increased power demand for powering the computer component 50 efficiently.
At times T3 and T4, the voltage POWDEM decreases from V4 to V3 and from V3 to V1, respectively. As an example, the decrease in the magnitude of the voltage VCOMP can be as a result of one or more additional functional components 54 being requested to deactivate. Similar to as described above, the predictive manner in which the VRD system 14 manages power can result in one or more power phases disabled at one time in response to anticipated (e.g., prior to) large decreases in the power demand indicated by the signal POWDEM to keep the power efficiency within desired operating parameters depending on the overall efficiency curve (e.g., the number of power phases 18 activated versus the current delivery) of the design of the VRD system 14.
At a time T5, the voltage POWDEM increases from V3 to V5. Such increase could result from the control signal(s) CTRL requesting activation of some or all of the functional component(s) 54. As an example, at the time T5, the functional component(s) 54, such as processor cores, memory controllers, memory modules, and/or I/O controllers, could have all been in an idle or deactivated state. Thus, the control signal(s) CTRL can request that some or all of the functional component(s) 54 be activated substantially concurrently. Therefore, the power demand logic 56 can predict the maximum power demand of the computer component 50 based on the control signal(s) CTRL, such that the magnitude of signal POWDEM can be adjusted to a maximum available measurable characteristic. In response to such power demand being indicated by the signal POWDEM, the VRD system 14 can enable all of the power phases 18 to provide a maximum output power.
In the example of
The memory system 154 includes memory power demand logic 168 and a plurality M of memory modules 170 in the memory system 154, such as DIMMs. The processor 152 can be configured to control activation and deactivation of the memory modules 170. For example, when the processor 152 requires access to one or more of the memory modules 170, the processor 152 can generate request signals MEMREQ that request activation of one or more select memory modules 170 according to the memory channels being accessed. As an example, the request signals MEMREQ can be queued in one or more memory controllers (not shown), such that one or more chip select signals are generated to control activation of the memory modules 170 in response to activation requests in the respective queue. Alternatively, the memory controller(s) can be arranged as part of the processor system 152, such that the processor 152 generates the chip select signals to the memory system 154. Thus, the chip select signals provided from the processor system 152 could be delayed relative to the request signals MEMREQ, as also provided from the processor system 152. In this way, the memory power demand logic 168 can predictively control VMEM in anticipation of changes in the number of active memory modules.
In a similar arrangement, the I/O system 156 can include I/O power demand logic 172 and a plurality P of I/O modules 174, where P is a positive integer denoting the number of I/O modules. For example, the I/O modules 174 can be configured as one or more of embedded function ICs and/or I/O cards, such as peripheral component interconnect (PCI) cards. As an example, the processor 152 can communicate with the I/O system 156 via a bus according to a set of signals demonstrated as IODATA. The signals IODATA can include control signals configured to request activity associated with one or more of the I/O modules 174. Thus, the I/O system 156 can selectively activate and deactivate the I/O modules 174 in response to the signals IODATA, such as based on the operation of an I/O controller (not shown).
In the example of
In addition, the VRD systems 158, 160, and 162 can be configured to selectively enable and disable the respective power phases 176, 178, and 180 based on the power demands of the respective processor 152, memory system 154, and I/O system 156 during run time. Thus, the VRD systems 158, 160, and 162 can dynamically respond to transient current demands from the respective processor 152, memory system 154, and I/O system 156 in an efficient manner based on the respective power demands.
As an example, the core power demand logic 164, the memory power demand logic 168, and the I/O power demand logic 172 can be configured to generate respective power demand signals, demonstrated in the example of
In addition, to provide power efficiently to the respective processor 152, memory system 154, and I/O system 156 based on their respective power demands, the VRD systems 158, 160, and 162 can dynamically enable and disable the power phases 176, 178, and 180, to respond to transient current demands in a predictive and efficient manner, such as described above in the example of
It is to be understood that the power management system 150 is not intended to be limited to the example of
In view of the foregoing structural and functional features described above, an example method will be better appreciated with reference to
At 206, an input power to the computer component from a voltage regulator down (VRD) system (e.g., VRD system 14 of
What have been described above are examples. It is, of course, not possible to describe every conceivable combination of components or methodologies, but one of ordinary skill in the art will recognize that many further combinations and permutations are possible. Accordingly, the invention is intended to embrace all such alterations, modifications, and variations that fall within the scope of this application, including the appended claims. Additionally, where the disclosure or claims recite “a,” “an,” “a first.” or “another” element, or the equivalent thereof, it should be interpreted to include one or more than one such element, neither requiring nor excluding two or more such elements.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/US10/53161 | 10/19/2010 | WO | 00 | 2/20/2013 |
