Systems and methods for providing a pipelined analog-to-digital converter

Abstract

Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.

Description

BACKGROUND

Power hungry buffers and/or large decoupling capacitors have long been the solution to providing accurate reference voltages in pipelined Analog-to-Digital Converters (ADCs). Zero-crossing based pipelined ADCs offer a low power alternative to traditional op-amp based solutions, but their reference buffer design is exacerbated since the reference voltage has only a fraction of the hold phase (known as the pre-charge phase) to settle to the desired accuracy.

Accordingly, new systems and methods for providing a pipelined Analog-to-Digital Converter (ADC) are desirable.

SUMMARY

Systems and methods for providing a pipelined Analog-to-Digital Converter (ADC) are provided. In some embodiments, systems for providing a pipelined Analog-to-Digital Converter are provided, the systems comprising: a first multiplying Digital-to-Analog Converter (MDAC) stage comprising: a sub-Analog-to-Digital Converter (ADC) that outputs a value based on an input signal; at least two reference capacitors that are charged to a reference voltage; at least two sampling capacitors that are charged to a sampling voltage; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.

In some embodiments, methods for providing a pipelined Analog-to-Digital Converter are provided, the methods comprising: in a first multiplying Digital-to-Analog Converter (MDAC) stage: outputting from a sub-Analog-to-Digital Converter (ADC) a value based on an input signal; charging at least two reference capacitors to a reference voltage; charging at least two sampling capacitors to a sampling voltage; and using a plurality of switches to couple the at least two reference capacitors so that they are charged during a sampling phase, to couple the at least two sampling capacitors so that they are charged during the sampling phase, to couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and to couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a pipelined Analog-to-Digital Converter (ADC) in accordance with some embodiments.

FIGS. 2a-2c are block diagrams of a Multiplying Digital-to-Analog Converter (MDAC) stage in accordance with some embodiments.

FIG. 3 is a timing diagram of clock signals in accordance with some embodiments.

FIGS. 4a-4h are circuit diagrams showing a pipelined ADC stage in accordance with some embodiments.

FIG. 5 is a circuit diagram of another pipelined ADC stage in accordance with some embodiments.

FIG. 6 is another timing diagram of clock signals in accordance with some embodiments.

FIG. 7 is a circuit diagram of a final ADC stage in accordance with some embodiments.

DETAILED DESCRIPTION

Systems and methods for providing a pipelined Analog-to-Digital Converter (ADC) are provided. In accordance with some embodiments, a zero-crossing pipelined ADC that uses a reference pre-charge technique is provided.

Turning to FIG. 1, an example of a general architecture 100 that can be used for a pipelined ADC in some embodiments is shown. As illustrated, architecture 100 can include a clock generator 102, non-final ADC stages 104, 106, and 108, and a final ADC stage 110. Although three non-final ADC stages are illustrated in FIG. 1, any suitable number of non-final ADC stages can be used in some embodiments.

Clock generator 102 can be any suitable circuit for generating clock signals for controlling the pipelined ADC in some embodiments. Examples of clock signals that can be generated by generator 102 are described below in accordance with some embodiments.

Non-final ADC stages 104, 106, and 108 can be any suitable non-final ADC stages, and may include a sub-ADC and a Multiplying Digital-to-Analog Converter (MDAC) such as the MDAC described below in accordance with some embodiments. Final ADC stages 110 can be any suitable final ADC stages, such as those described below in accordance with some embodiments.

FIGS. 2a, 2b, and 2c illustrate example architectures 202, 216, and 222 of a 1-bit MDAC with a charge based reference that can be used in a non-final ADC stage in accordance with some embodiments. More particularly, FIG. 2a illustrates an example 1-bit MDAC architecture during a sample phase, FIG. 2b illustrates an example 1-bit MDAC architecture during a hold phase, and FIG. 2c illustrates an alternative 1-bit MDAC architecture to that in FIG. 2a during a sample phase.

As shown in FIG. 2a, architecture 202 can include reference capacitors C_refp 204 and C_refn 206, sampling capacitors C₁ 208 and C₂ 210, a comparator 212, and a load capacitance 214.

As shown, in the sample phase, the reference voltages V_refp and V_refn can be sampled onto the reference capacitors and input voltage V_in can be sampled onto the sampling capacitors.

During a hold phase, as shown in FIG. 2b, one of two switches 218 and 220 can be closed based on whether a sub-ADC output bit associated with the stage is a zero or a one. That is, if the bit is a zero, then switch 218 will be closed, and if the bit is a one, then switch 220 will be closed. Charge stored on the corresponding capacitor 204 (which corresponds to switch 218) or capacitor 206 (which corresponds to switch 220) can be added to parallel sampling capacitor C₂ 210 and transferred along with charge from sampling capacitor C₁ 208 to load capacitance 214.

As shown in FIG. 2c, in some embodiments, the charge that is supplied to the reference capacitors need not come from a voltage source. Instead, currents I_refp and I_refn from current sources 224 and 226 can be used to charge capacitors C_refp and C_refn for a period of time T_ref and thereby provide the same amount of charge. The value of the reference voltage can be given by V_ref=(I_ref/C_ref)T_ref. When using a current source to charge a reference capacitor, the exact value of the reference voltage sampled may not be known beforehand, as the parameters I_ref, C_ref and T_ref can be process dependent. But because this value is input signal independent, the error can be combined with stage gain error and corrected with Digital Gain Error Correction.

In some embodiments, each MDAC can use a 1 bit/stage architecture with a nominal gain of 1.75.

Turning to FIG. 3, a timing diagram of clock signals that can be generated by a clock generator for controlling the operation of a pipelined ADC in accordance with some embodiments is illustrated. As shown, each stage of the pipelined ADC has a sample phase and a hold phase represented by Φ_s and Φ_h, respectively. During the sample phase, the stage input V_in is sampled onto the sampling capacitors. During the hold phase, charge from the stage is transferred to the next stage.

During a pre-charge phase of the reference phase, represented by Φ_rpe for even numbered stages and Φ_rpo for odd numbered stages, the reference capacitors can be discharged.

During a reference charge phase, represented by Φ_re for even numbered stages and Φ_ro for odd numbered stages, reference current sources I_refp and I_refn can charge the reference capacitors C_refp1, C_refp2 and C_refn1, C_refn2 to a nominal reference voltage V_refp and V_refn, respectively

During a pre-charge phase for the sampling phase, represented by Φ_po for odd numbered stages and Φ_pe for even numbered stages, the sampling capacitors can be discharged.

FIGS. 4a-4h illustrate an example of a design for a pipelined ADC stage of a circuit 400 that uses a 1-bit MDAC architecture as described above in FIGS. 2a-2C in accordance with some embodiments. As shown, the ADC stage is a differential stage and receives input voltages V_inp and V_inn. Charge from these input voltages is stored in sampling capacitors C_1p, C_2p and C_1n, C_2n, respectively. Input voltages V_inp and V_inn are also compared by comparator 402 (which acts as a 1-bit sub-ADC) to provide an output bit b_N. Reference capacitors C_refp1, C_refp2, C_refn1, and C_refn2 are charged by current sources I_refp and I_refn. At the end of the sample phase, based on the value of b_N output by comparator 402, the charge from one pair of reference capacitors C_refp1, C_refn1 or C_refp2, C_refn2 is transferred to the output capacitors C_1p, C_1n during the hold phase, by shorting one of their plates to V_cm.

In circuit 400, the sampling of the input voltages, the charging of the reference capacitors, and the transfer of charge from these capacitors to the next stage is controlled by the illustrated switches that open or close based on the value of Φ_h, Φ_rpe, Φ_rpo, Φ_re, Φ_ro, Φ_pe, Φ_po, Φ_N−1, Φ_dN−1, Φ_N, Φ_dN, Φ_N+1, Φ_dN+1, b_N, and b_N+1.

As described above, Φ_h, Φ_rpe, Φ_rpo, Φ_re, Φ_ro, Φ_pe, Φ_po can be generated by a clock generator in some embodiments. The eight FIGS. 4a-4h show the states of switches for Φ_h, Φ_rpe, Φ_rpo, Φ_re, Φ_ro, Φ_pe, Φ_po at the eight sub-stage periods 1-8, respectively, shown in FIG. 3, in some embodiments.

Φ_N−1, Φ_dN−1, Φ_N, Φ_dN, Φ_N+1, Φ_dN+1 can be generated by the ZCDs and delay circuits shown in some embodiments. b_N and b_N+1 can be generated by the comparators shown in some embodiments. Although specific states for the switches for Φ_N−1, Φ_dN−1, Φ_N, Φ_dN, Φ_N+1, Φ_dN+1, b_N, and b_N+1 are shown, these switches can be opened or closed in some of the sub-stage periods based on the operation of the circuit and the stage input voltage in some embodiments. b_N and b_N+1 can correspond to switches that close when these signals are high and b_N* and b_N+1* can correspond to switches that close when the signals b_N and b_N+1 are low.

Any suitable zero-crossing detector (ZCD) can be used in circuit 400 in some embodiments. For example, a ZCD similar to the ZCD described in L. Brooks et al., “A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC,” IEEE Journal of Solid-State Circuits, December 2009, which is hereby incorporated by reference herein in its entirety, can be used in some embodiments. In some embodiments, this ZCD can use static inverters at its output to generate the necessary logic levels. Overshoot can be corrected by adjusting the relative strengths of the PMOS load pair of the ZCD in some embodiments.

Although not shown, additional calibration logic for gain calibration can be implemented in some embodiments.

In some embodiments, the output current sources I_p, I_n that perform the charge transfer can employ local negative feedback to provide a constant ramp rate for good linearity.

In some embodiments, the bias currents for a first set of stages (e.g., stages 1-3) can be analog and digitally programmable, while those of the rest of the stages can share a common digital control.

In some embodiments, pipelined ADC 100 of FIG. 1 can be implemented so as to provide a multi-bit output at each ADC stage. Multi-bit non-final ADC stages 104, 106, and 108 in such a pipelined ADC can be any suitable multi-bit ADC stages, and can include a sub-ADC path and a multi-bit MDAC stage in some embodiments.

In some embodiments, the sub-ADC path can include a set of signal and reference capacitors and a sequential search a successive approximation register (SAR) ADC that can obtain its thresholds by capacitive division between its input and its reference, and hence may not require a reference buffer.

In some embodiments, the multi-bit MDAC stages can be implemented using a 2.5 bit zero-crossing MDAC stage, each with a gain of four, such as stage 500 of FIG. 5 in some embodiments.

Similarly to the circuits described above, in stage 500, during the sample phase Φ_s, the differential input V_inp, V_inn is sampled on the signal (or sampling) capacitors C_sigp, C_sign. Concurrently, during the reference pre-charge phase Φ_ref, six reference current sources, I_refp<5:0> and I_refn<5:0>, pre-charge six reference capacitors, C_refp<5:0> and C_refn<5:0>, to the nominal reference voltages. At the end of the pre-charge phase Φ_p, based on outputs S<5:0> of a sub-ADC corresponding to the stage (not shown), the reference capacitors are connected appropriately to V_p and V_n by a switch 502. By the end of the hold phase Φ_h, the charge is transferred to the next stage capacitors C′_sigp, C′_sign. The value of the reference voltage in the case of reference pre-charging is given by V_ref=(I_refp/C_refp−I_refn/C_refn)T_ref, where T_ref is the duration for which the reference current sources I_refp<5:0> and I_ref<5:0> charge the reference capacitors, C_refp<5:0> and C_ref<5:0>. The exact value of V_ref may not be known beforehand in some embodiments, but, because V_ref is input-signal independent, the variation can be combined with stage gain error and corrected with digital gain error correction.

The loading can be reduced in some embodiments by connecting the reference capacitors to V_p and V_n only when required.

In some embodiments, each C_ref<5:0> can be chosen to be half the size of C_sig as a tradeoff between the extra loading and power supply noise rejection. In some embodiments, the reference current sources I_refp<5:0> and I_refn<5:0> can be implemented as digitally programmable cascoded current sources. Switches (not shown) can be used to short the reference capacitors to the common-mode voltage V_cm during Φ_pr, and pre-charge the outputs V_outp and V_outn to GND and V_DD respectively, during Φ_p, in a similar manner to that shown in FIGS. 4a-4h in some embodiments.

The output current sources, I_p and I_n, perform the actual charge transfer and can be implemented as regulated cascodes for good linearity performance in some embodiments. The zero-crossing detector (ZCD) can include a two-stage differential-to-single-ended amplifier for improved common-mode rejection. The overshoot at the output of the MDAC due to the finite delay of the ZCD can be compensated for by introducing an offset through a digitally programmable capacitor array connected to V_p and V_n as described in J. Chu et al., “A zero-crossing based 12b 100 MS/s pipelines ADC with decision boundary gap estimation calibration,” VLSI Circuits (VLSIC), 2010 IEEE Symposium on, June 2010, which is hereby incorporated by reference herein in its entirety.

A timing diagram for clock signals that can be used control stage 500 of FIG. 5 in accordance with some embodiments is shown in FIG. 6. The illustrated clock signals can be generated by any suitable clock generator in some embodiments.

An example of a circuit 700 that can be used to implement a final ADC stage 110 in accordance with some embodiments is shown in FIG. 7. As illustrated, reference pre-charging can be implemented in circuit 700 similarly to that shown and described above in connection with FIG. 5. Circuit 700 can also use a binary search SAR 702 to resolve the final eight bits of the pipelined ADC in some embodiments. Depending on the outputs D<7:1> of SAR 702, the reference capacitors are connected appropriately by switch 704 to implement a binary search in some embodiments. The SAR timing can be controlled using a delay locked loop in some embodiments.

In some embodiments, a pipelined ADC as described here can be implemented using only two external voltages: a V_DD and a common-mode voltage V_cm, which can be nominally V_DD/2 formed using a resistive divider from V_DD.

Although the invention has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of implementation of the invention can be made without departing from the spirit and scope of the invention, which is only limited by the claims which follow. Features of the disclosed embodiments can be combined and rearranged in various ways.

Claims

1. A system for providing a pipelined Analog-to-Digital Converter, comprising: a first multiplying Digital-to-Analog Converter (MDAC) stage comprising: a sub-Analog-to-Digital Converter (ADC) that outputs a value based on an input signal;a first reference capacitor that is charged to a reference voltage;a second reference capacitor that is charged to the reference voltage;a first sampling capacitor that is charged to a sampling voltage;a second sampling capacitor that is charged to the sampling voltage; anda plurality of switches that couple the first reference capacitor and the second reference capacitor so that the first reference capacitor and the second reference capacitor are charged during a sampling phase, that couple the first sampling capacitor and the second sampling capacitor so that the first sampling capacitor and the second sampling capacitor are charged during the sampling phase, that couple the first reference capacitor so that the first reference capacitor is parallel to the second sampling capacitor during a hold phase in response to the value output by the sub-ADC having a first value, and that couple the first sampling capacitor so that the first sampling capacitor couples the first reference capacitor and the second sampling capacitor to a reference capacitor of a second MDAC stage during the hold phase in response to the value output by the sub-ADC has the first value.

2. The system of claim 1, wherein the first MDAC stage further comprises a first current source coupled to the first reference capacitor and a second current source coupled to the second reference capacitor.

3. The system of claim 2, wherein the first current source and the second current source are cascoded current sources.

4. The system of claim 2, wherein the first current source charges the first reference capacitor for a given period of time and the second current source charges the second reference capacitor for the given period of time.

5. The system of claim 1, wherein the first MDAC stage further comprises a zero-crossing detector that controls how long the first sampling capacitor and second sampling capacitor are coupled to an input voltage.

6. The system of claim 5, wherein the first MDAC stage further comprises a delay circuit that receives an output signal of the zero-crossing detector and provides a delayed signal that controls when the first sampling capacitor and second sampling capacitor are coupled to the input voltage.

7. The system of claim 1, wherein the sub-ADC is a comparator.

8. The system of claim 1, wherein the sub-ADC is a flash ADC.

9. The system of claim 1, wherein the first MDAC stage is a differential MDAC stage.

10. The system of claim 1, wherein the first reference capacitor and the second reference capacitor are each half the size of the first sampling capacitor and the second sampling capacitor.

11. A method for providing a pipelined Analog-to-Digital Converter, comprising: in a first multiplying Digital-to-Analog Converter (MDAC) stage: outputting from a sub-Analog-to-Digital Converter (ADC) a value based on an input signal;charging a first reference capacitor and a second reference capacitor to a reference voltage;charging a first sampling capacitor and a second sampling capacitor to a sampling voltage; andusing a plurality of switches to couple the first reference capacitor and the second reference capacitor so that the first reference capacitor and the second reference capacitor are charged during a sampling phase, to couple the first sampling capacitor and the second sampling capacitor so that the first sampling capacitor and the second sampling capacitor are charged during the sampling phase, to couple the first reference capacitor so that the first reference capacitor is parallel to the second sampling capacitor during a hold phase in response to the value output by the sub-ADC having a first value, and to couple the first sampling capacitor so that the first sampling capacitor couples the first reference capacitor and the second sampling capacitor to a reference capacitor of a second MDAC stage during the hold phase in response to the value output by the sub-ADC has the first value.

12. The method of claim 11, charging the first reference capacitor using a first current source and charging the second reference capacitor using a second current source.

13. The method of claim 12, wherein the first current source and the second current source are cascoded current sources.

14. The method of claim 12, wherein the first current source charges the first reference capacitor for a given period of time and the second current source charges the second reference capacitor for the given period of time.

15. The method of claim 11, wherein controlling how long the first sampling capacitor and second sampling capacitor are coupled to an input voltage using a zero-crossing detector.

16. The method of claim 15, further comprising providing a delayed signal that controls when the first sampling capacitor and second sampling capacitor are coupled to the input voltage in response to an output of the zero-crossing detector.

17. The method of claim 11, wherein the sub-ADC is a comparator.

18. The method of claim 11, wherein the sub-ADC is a flash ADC.

19. The method of claim 11, wherein the first MDAC stage is a differential MDAC stage.

20. The method of claim 11, wherein the first reference capacitor and the second reference capacitor are each half the size of the first sampling capacitor and the second sampling capacitor.