Embodiments of the present invention provide security systems and methods for computing systems having one or more processing components, such as a microprocessors, each with one or more processor components such as cache units, instruction cache units, branch prediction units, branch target buffers, and other components. In one specific embodiment, for example, the present invention provides methods and systems for preventing security breaches related to branch prediction by central processing units. Merely by way of example, the invention is described as it applies to architectural level security of computing systems, but it should be recognized that the invention has a broader range of applicability. Embodiments of the present invention are useful in a variety of computing systems and device incorporating computing systems. Examples include desktop computer systems, laptop computer systems, mainframe computer systems, cell phone devices, personal digital assistant devices, smart cards, embedded systems, etc. and any other systems incorporating a microprocessor or similar intelligence module.
Also, although the remainder of this document will discuss embodiments and aspects of the invention in terms of their applicability to BPU and BTB units, it should be appreciated that embodiments and aspects of the present invention may be applied to any other processor components. Examples of such components include data cache and instruction cache. In general, a processor component is a component having an internal state that is affected by execution of a process, which produce state transitions in the component. In many cases, these states and state transitions may be observable by an adversary using appropriate measurement techniques. A processor component typically includes a collection of one or more circuit elements that are configured to perform one or more specific tasks. Additionally, it should be appreciated that, where an output signal is mentioned, embodiments of the present invention are equally applicable to any signal in a processor component, e.g., any signal on a wire internal to a component or any signal between components.
According to various embodiments, system security is improved by making it difficult for an adversary to observe the output of a processor component using methods described herein. In certain aspects, new secure instructions are used, and the implementers need to use them to indicate for which conditional branches need to be handled securely. According to one aspect, in these new secure branch instructions, at least one bit, which indicates whether the branch needs to be handled securely, is different than in the original branch instruction.
In certain embodiments, the predictor for certain user-determined conditional branches is disabled. In a specific embodiment, the predictor is disabled so that branch prediction operations are not performed. In another embodiment, the predictor functions normally but the outcome of the prediction is ignored. For example, the execution has to stall until the actual outcome of the branch is determined. To achieve this functionality, the control logic of the predictor is modified.
These embodiments can also be adapted to the cases of other microprocessor components such as data cache, instruction cache, and the like. For example, data cache and/or instruction cache can be disabled for certain user-determined memory accesses. In some embodiments, data cache and/or instruction cache may be disabled so that memory accesses are not served from these components. In some embodiments, certain user-determined memory accesses may not be served from these components. In other embodiments, these microprocessor components may function normally but the outcomes may be ignored and certain user-determined memory accesses may not served from these components.
For example, in one embodiment, randomization functionality is added to the behavior of the predictor. Conventional predictor functionalities are usually implemented as a function of the state of the predictor (i.e., local and global branch history, BTB state and the individual predictors), and the address of the conditional branch. The state transition is usually also a function of the above items plus the actual outcome of the branch:
These functions can be generalized for other processor components such as data cache, instruction cache, and the like:
In one embodiment, an element is added to the above functions, which element makes it difficult for an adversary to predict or observe the state or state transition. For example, in one aspect, a pseudorandom element is added to the above state functions. One example is a pseudo random number generator (PRNG) 60, as shown in
In other aspects, any signal may be used to add randomness or unpredictability to the output of the predictor. For example, In one aspect, the function of PRNG 60 (to provide a signal to logic circuit 70) in
This protection method may be implemented in a variety of ways. For example, in one embodiment, a protection method is implemented by selecting either the actual prediction or the fake prediction as illustrated in
The present invention also improves system security by reducing potential vulnerabilities related to the BTB. More specifically, in certain aspects, new secure branch instructions are introduced. In one aspect, to avoid the interference of malicious code, such as a spy/dummy process, to the execution of the cipher, the BTB records of each process are located in a different buffer. In another aspect, the BTB is implemented in such a way that the critical conditional branches always cause BTB hits or misses, in which case it is possible to implement a cipher so that the execution becomes independent of the BTB outcomes. In another aspect, the BTB records of critical conditional branches are located in an unpredictable manner so that the attacks become harder to apply, e.g., if the attacker does not know the exact location of a BTB record, the attacks will be more costly.
According to one embodiment, a BPU is implemented with independent (i.e., unshared) branch target buffers. For example, in one aspect, each process in a CPU is allocated its own BTB space. Additionally or alternatively, each logical and/or physical processor unit is allocated its own BTB space. A physical processor may present itself to the OS as two or more independent logical processors. For example, in a Simultaneous Multi-Threading System (e.g., Intel's Hyper-Threading technology), a real physical processor is able to presents itself to the operating system as two or more independent logical processors. As a result of using independent, unshared buffer spaces, the interference between spy and cipher processes via BTB is minimized and/or prevented. An operating system (OS) is a set of computer programs that manage the hardware and software resources of a computer. An operating system processes raw system and user input and responds by allocating and managing tasks and internal system resources as a service to users and programs of the system. In general, all software that manages hardware and software resources of a computing environment will be referred to herein as the operating system. Examples of such software include virtual machine monitors, hypervisors, and reference monitors. While an adversary may clear the BTB during a context switch, the amount of biased BTB outcomes of the cipher is greatly reduced. The OS in the system may clear (e.g., flush, invalidate) a BTB space with a certain frequency and/or during special events. For example, the OS may clear the BTB during each context switch and/or before starting an execution of some applications and/or after the termination of some applications. Furthermore, the hardware system, e.g. a processor, or an application may also clear a BTB space with a certain frequency and/or during special events. A BTB space may include a portion of a BTB unit, an entire (separate) BTB unit, portions of separate BTB units, or a plurality of separate BTB units.
In one embodiment, the allocated BTB spaces are independent and are virtually and/or dynamically allocated. For example, in one aspect, BTBs may be implemented as separate physical units. In general, any number of separate physical BTB units may be implemented. Physical independence is implemented, in one aspect, (at least) by way of using a different physical BTB for each process and/or logical processor in the CPU. Also, each process and/or logical processor can be allocated more than one physical BTB. In another aspect, each process and/or logical processor can be allocated a separate buffer space that spans more than one physical BTB, e.g., multiple processes and/or logical processors share multiple BTBs, but the buffer space allocated to each process and/or logical processor is separate and unshared. According to another embodiment, a single large physical BTB is partitioned into multiple and preferably disjoint portions by way of hard coding (i.e., forcing each logical processor to use a disjoint portion of the BTB).
In another embodiment, the BTB are utilized as dynamically allocated virtual partitions. For example, a specific instruction set is provided for the process. In another embodiment, instructions are used to indicate the presence of sensitive operations and the need of (virtually) independent BTB.
In one aspect, to make each BTB independent, the BTB line is modified. For example, a modified BTB line according embodiments of the present invention allows for BTB lines to be virtually independent.
To preserve the correct functionality, the tag address space in the BTB line is increased by a number of bits, N, where N is a number greater than or equal to zero.
In a specific embodiment, it is possible to dynamically switch between a normal BTB operation mode and a virtually unshared BTB mode using special instructions. For example, a process may indicate that it needs to be virtually independent (e.g. needs a virtually unshared BTB buffer) and/or the CPU can switch to the virtually unshared BTB mode. In one embodiment, during a context switch, the operating system stores this information (i.e. the need of be virtually independent) as part of the process state. For example, the operating system is able to set/reset the mode when determined to be necessary by the operating system.
According to another embodiment, the present invention provides a partitioned BTB. Some parts of a BTB can be exclusively reserved and/or dedicated to some certain processes and/or logical processors. Depending upon the application, partitions can be dynamically allocated or statically implemented. In the case of dynamic partition allocation, new instructions are introduced to manage the dynamic partitioning. This management can be software based (i.e., the operating system can manage the partitions) and/or hardware based.
The software based partitioning can be implemented in different ways. By way of an example, the operating system (OS) can modify the logical addresses of the branches before starting the execution of a process. In order to do this, the OS has to have detailed information of the process' code, which can be provided by the compiler. Therefore, the OS can remove inter-process BTB collisions.
Another approach is to manage the partitioning in the hardware. Again this approach can be implemented in many different ways. The following are some examples.
In one embodiment, a process executes a special instruction that instructs the CPU to reserve a part of the BTB only to this process. For example, it may be necessary to use one of the reserved bits in control registers as a flag to indicate if the BTB has been partitioned. When the CPU receives the special instruction from a process, the CPU sets the flag and uses a special part of the BTB that is to be used only for this process's entries.
The special instruction is one way of various BTB protection methods. For example, in Pentium®4, the BTB is 4-way associative. Accordingly, a CPU can reserve one or more specific ways of these 4 ways for a process and the entries of this process can exclusively use these parts of the BTB and the rest of the buffer can be used for general purposes, i.e., for other processes. For example, during a context switch, the new flag needs to be reset so that the partitioned way(s) can be used again for general purposes.
Depending on the application, the BTB may also be partitioned in many other ways. For example, the BTB can be partitioned in the same way a traditional cache is partitioned (with some minor modifications which are suitable for the BTBs as would be apparent to one skilled in the art). In this manner, a large part of the BTB does not need to be partitioned.
According to certain embodiments, rather than reserving a large portion of the BTB, one or more BTB entries (or sets) may be reserved for one or more entries of some processes. For example, reserving a smaller portion of the BTB advantageously allows for avoiding BP attacks without closing a large part of the BTB to general use. In one embodiment, as shown in
In some cases, this technique may cause a race-condition and a possible deadlock. In an embodiment, a special part of BTB may be used to avoid deadlocks. For example, if a secure conditional branch faces a deadlock situation, an entry from this special part can be used to store the record of that branch.
A single or several BTB entries or a single/several BTB sets can be reserved in BTB for security critical branches. According to one embodiment, a BTB locking mechanism provides this capability. A process can determine which and how many of its branches needs to be handled in a more secure way. Some branches in a software can be marked as critical and the CPU would handle these branches differently than the others, e.g., in a more secure manner. Hardware additions to the BTB and a system interface for controlling which branches should be locked are provided. The system interface may be defined in several different ways including adding new instructions to the instruction set of the processor to specify which branches should be locked in BTB. The hardware additions to the BTB may also be implemented in several different ways. In one embodiment, a single bit is added to each BTB line. This bit specifies whether the entry stored in this BTB line is locked. In another embodiment, a single bit is added to each BTB set. In another embodiment, the CPU store this information in another part of the system, e.g., a buffer separate from the BTB. In general, the CPU stores the information of which entries in BTB should be locked. When an entry is locked in a BTB by a process, this entry should not be evicted as a result of execution of a branch that belongs to another process. In other words, a locked entry in the BTB should not be replaced by another entry that belongs to another process. A locked entry that belongs to a process can be removed from the BTB when this process terminates.
In one embodiment, as long as a process is active (i.e., not terminated), the locked entries that belong to this BTB cannot be evicted from BTB by a process different from the process that owns the entry and cannot be replaced by other processes' entries. The operating system or any other software that controls the overall system (referred to herein as the OS) may remove the locked entries from the BTB. For example, in one aspect, the OS removes the lock on the locked entries that belong to a process when this process terminates. In certain aspects, a lock on a BTB line can be removed by resetting the lock bit in this line.
The OS or the CPU needs to keep track of which locked BTB entries belong to which process. In one embodiment, additional hardware is added to each BTB line to store to which process this BTB entry belongs. In one aspect, this is done by storing an identification of the process, i.e., ID of the process. In another aspect, the CPU stores this information in another part of the system; for example in a dedicated buffer. In yet another aspect, this information is stored by the OS in buffer in main memory. In one embodiment, a new instruction is added to the instruction set. This new instruction can be executed by OS after the termination of a process to automatically remove the locking on the BTB entries that belong to this process. In one embodiment, the CPU needs to know the information on which processes are active and which processes are not active. This is done, in certain aspects, by a communication between the OS and CPU (for example via executing an instruction) and the OS can pass this information to CPU. In this aspect, the CPU can remove the locking on BTB entries that belong to a terminated process. In another aspect, the OS handles this task by removing the locking on BTB entries that belong to a terminated process. In one embodiment, a new instruction is added to the instruction set for removing the locking on a specified BTB entry (for example by resetting the lock bit). There can be several other alternatives. It should be realized that the techniques of locking a BTB entry is not limited to these specified entries and has a broader application range.
According to one embodiment, an implementer-specified conditional branch, which can always yield a constant BTB output (e.g., either always a hit or a miss), is provided. One example of such a protected BTB area is described below.
According to various embodiments, the target addresses of certain implementer-specified conditional branches may be stored in a protected BTB area in advance. For example, new pre-load instructions and secure conditional branch instructions may have to be preloaded.
The target addresses can be loaded before the actual computations in a buffer and the new secure conditional branches can refer to the indices of this buffer. For example, as shown in
While the invention has been described by way of example and in terms of the specific embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
This application claims the benefit of U.S. Provisional Application Ser. No. 60/830,210 (Attorney Docket No. 026490-000100US), filed Jul. 11, 2006, and U.S. Provisional Application Ser. No. 60/843,448 (Attorney Docket No. 026490-000200US), filed Sep. 7, 2006, the disclosures of which are each incorporated herein by reference in its entirety.
Number | Date | Country | |
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60843448 | Sep 2006 | US | |
60830210 | Jul 2006 | US |