Patent Application
20180335828
Portable computing devices (e.g., cellular telephones, smart phones, tablet computers, portable digital assistants (PDAs), portable game consoles, wearable devices, and other battery-powered devices) and other computing devices continue to offer an ever-expanding array of features and services, and provide users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, such devices have become more powerful and more complex. Portable computing devices now commonly include a system on chip (SoC) comprising a plurality of memory clients embedded on a single substrate (e.g., one or more central processing units (CPUs), a graphics processing unit (GPU), digital signal processors (DSPs), etc.). The memory clients may read data from and store data in an external dynamic random access memory (DRAM) electrically coupled to the SoC via a high-speed bus, such as, a double data rate (DDR) bus.
Although various memory standards define the protocols and timings with which the SoC may interface with the DRAM, existing system have several disadvantages for selecting optimal bandwidth/frequency operating points. In existing systems, there are generally three degrees of freedom from which the SoC may select the optimal operating points. First, there are silicon various between DRAM suppliers, between different process nodes, and to a large extent between different wafers coming from the same supplier and process node. Second, there are channel variations between platform industrial designs, SoC and DRAM package designs, and radio frequency compliance. Third, various DRAM interface parameter settings (e.g., clock frequency, latency, on-die termination, etc.) may be adjusted.
Existing systems employ best-effort lumped parameters for these variables, which are designed to provide reliable error-free operation. Such a “one-size-to-fit-all” parameter setting can be wasteful of energy because there may be device samples that outperform the norm and could benefit from optimized settings.
Accordingly, there is a need for improved systems and methods for customizing DRAM interface parameter settings to enable individual units to expend the least amount of energy and to allow finer granularity of bandwidth/frequency operating points.
Systems and methods are disclosed for reducing double data rate (DDR) memory power consumption via device-specific customization of DDR interface parameters. One embodiment comprises a method for minimizing double data rate (DDR) power consumption. The method selects one of a plurality of operating points for a DDR interface electrically coupling a DDR memory to a memory controller residing on a system on chip (SoC). The memory controller executes a memory test via the DDR interface at the selected operating point. During the execution of the memory test at the selected operating point, the method determines an optimal value of a setting for one or more DDR interface parameters associated with the DDR interface that minimizes memory power consumption and maintains a predetermined DDR eye margin.
Another embodiment of a system comprises a double date rate (DDR) memory and a system on chip (SoC). The SoC comprises a memory controller electrically coupled to the DDR memory via a DDR interface. The memory controller is configured to execute a memory test via the DDR interface at one or more of a plurality of operating points. During the execution of the memory test, the memory controller determines an optimal value of a setting for one or more DDR interface parameters associated with the DDR interface that minimizes memory power consumption and maintains a predetermined DDR eye margin.
In the Figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as “102A” or “102B”, the letter character designations may differentiate two like parts or elements present in the same Figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral to encompass all parts having the same reference numeral in all Figures.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
In this description, the term “application” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, an “application” referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
The term “content” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, “content” referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
As used in this description, the terms “component,” “database,” “module,” “system,” and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device may be a component. One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components may execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal).
In this description, the terms “communication device,” “wireless device,” “wireless telephone”, “wireless communication device,” and “wireless handset” are used interchangeably. With the advent of third generation (“3G”), fourth generation (“4G”), fifth generation (“5G”) and other wireless technology, greater bandwidth availability has enabled more portable computing devices with a greater variety of wireless capabilities.
The SoC 102 comprises various on-chip components electrically coupled via SoC bus 115. In the embodiment of
The CPU 112 may support a high-level operating system (O/S) 126. As described below in more detail, the CPU 112 may execute various modules (e.g., DDR data eye training module 128, DDR interface parameter customization module 130) for performing the customization of device-specific DDR interface parameters.
The power controller 124 is electrically coupled to a power supply 138 via a power control bus 142, which comprises a power monitor 140 configured to measure energy usage associated with the SoC 102 and the DRAM 104 and, thereby, monitor memory power consumption.
As further illustrated in
The DCVS controller 120 is configured to implement various DCVS techniques. As known in the art, the DCVS techniques involve selectively adjusting the frequency and/or voltage applied to the SoC components (e.g., CPU 112, power controller 124, and other hardware devices) to yield a desired performance and/or power efficiency characteristics.
The DRAM controller 114 comprises a physical layer 132, which is electrically coupled to a physical layer 106 residing on DRAM 104. Physical layer 106 is coupled to DRAM peripheral logic 108, which is coupled to a cell array 110.
As further illustrated in
As known in the art, the memory interface frequency may be determined by the required traffic bandwidth requested from all memory clients. This frequency may rise or fall as the traffic bandwidth demand changes. Typically, several voltage/frequency bins may be used. For each frequency operating point, the system comprising the SoC, the physical channel, and the DRAM are tuned during factory initialization to establish “common parameter settings” that will provide reliable operation.
In this manner, the DDR interface parameter settings at each frequency operating point may be optimized for individual devices or units to address potential chip-to-chip variation. During the execution of the memory test pattern 151 at the various frequency operating points, the power monitor 140 may measure power consumption of the SoC 102 and DRAM 104 while the DDR interface parameter settings are adjusted. It should be appreciated that the memory test pattern 151 exercises the DRAM 104 to characterize the magnitude of the power consumption for each frequency bin. There may be multiple reliable or successful parameter settings for each frequency bin. In an embodiment, the optimal setting is determined to be the setting that results in the lowest power consumption while maintaining the DDR data eye margin within predetermined margin(s).
One of ordinary skill in the art will appreciate that the variations in memory power consumption between sample A and sample B may result from chip-to-chip variations related to the SoC 102 chip, the DRAM 104 chip(s), and/or variations in the physical channel comprising DRAM control and data bus 134 and DRAM clock bus 136. These and other variations between different devices having an identical system design may be caused by silicon process variation(s) between chips, which affect the DDR interface parameter settings that determine the operational characteristics such as interface power, frequency of operation, and bit error rate. For example, if either the SoC 102 or any DRAM 104 silicon is “slow”, then for a given target frequency of operation the device may need to be configured with parameters, such as, drive strength or termination strength to compensate, resulting in higher power consumption compared to “fast” silicon. “Fast” or “slow” refers to the circuit signal propagation delay, rise/fall times, and skew characteristics.
The exemplary graph 300 shows that the power monitor 140 may determine different power consumption levels at the same frequency bins for sample A and sample B. For example, sample A has the lowest energy at low frequency (i.e., PA0 in bin0). Sample B has the lowest energy at peak frequency (i.e. PB2000 in bin2000). Sample A has a generally steeper slope than sample B (i.e., [PA800−PA0]>[PB800−PB0]). Sample A may require elevated power earlier at 1100 MHz compared to sample B at 1500 MHz. To minimize memory power consumption, the power monitor 140 residing in sample A and sample B may measure the corresponding illustrated memory power consumption and determine the DDR interface parameter settings, for each frequency bin, that results in the lowest memory power consumption for each sample.
At block 406, the common parameter settings or values may be committed to a software build for devices incorporating the system 100. At block 408, a device incorporating the system 100 may be initially booted up during OEM factory installation. At block 410, the common parameter settings or values are applied to the device and the system 100 may begin executing the memory test pattern 151. At block 412, the DDR date eye training module 128 may begin training DDR data eye parameters (e.g., horizontal eye sampling point, vertical eye sampling point) to maximize DDR data eye margins for each frequency operating point. It should be appreciated that these DDR data eye parameters may not affect the shape, size, and/or quality of the data eye. For example, the DDR data eye training may determine an optimal sampling decision point within the eye. In contrast, the common parameter settings are capable of changing the shape, size, and/or quality of the data eye (e.g., making the eye clean versus noisy, large versus closed, etc.).
Referring to
Referring again to
As mentioned above, the system 100 may be incorporated into any desirable computing system.
A display controller 828 and a touch screen controller 830 may be coupled to the CPU 802. In turn, the touch screen display 806 external to the on-chip system 822 may be coupled to the display controller 828 and the touch screen controller 830.
Further, as shown in
As further illustrated in
As depicted in
It should be appreciated that one or more of the method steps described herein may be stored in the memory as computer program instructions, such as the modules described above. These instructions may be executed by any suitable processor in combination or in concert with the corresponding module to perform the methods described herein.
Certain steps in the processes or process flows described in this specification naturally precede others for the invention to function as described. However, the invention is not limited to the order of the steps described if such order or sequence does not alter the functionality of the invention. That is, it is recognized that some steps may performed before, after, or parallel (substantially simultaneously with) other steps without departing from the scope and spirit of the invention. In some instances, certain steps may be omitted or not performed without departing from the invention. Further, words such as “thereafter”, “then”, “next”, etc. are not intended to limit the order of the steps. These words are simply used to guide the reader through the description of the exemplary method.
Additionally, one of ordinary skill in programming is able to write computer code or identify appropriate hardware and/or circuits to implement the disclosed invention without difficulty based on the flow charts and associated description in this specification, for example.
Therefore, disclosure of a particular set of program code instructions or detailed hardware devices is not considered necessary for an adequate understanding of how to make and use the invention. The inventive functionality of the claimed computer implemented processes is explained in more detail in the above description and in conjunction with the Figures which may illustrate various process flows.
In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, NAND flash, NOR flash, M-RAM, P-RAM, R-RAM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessed by a computer.
Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (“DSL”), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.
Disk and disc, as used herein, includes compact disc (“CD”), laser disc, optical disc, digital versatile disc (“DVD”), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
Alternative embodiments will become apparent to one of ordinary skill in the art to which the invention pertains without departing from its spirit and scope. Therefore, although selected aspects have been illustrated and described in detail, it will be understood that various substitutions and alterations may be made therein without departing from the spirit and scope of the present invention, as defined by the following claims.
