Patent Application
20250138875
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is Information Handling Systems (IHSs). An IHS generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, IHSs may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in IHSs allow for IHSs to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, IHSs may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Modern day IHS administrative management is often provided via baseboard management controllers (BMCs). The baseboard management controller (BMC) generally includes a specialized microcontroller embedded in the IHS, and may provide an interface between system-management software and platform hardware. Different types of sensors built into the IHS report to the BMC on parameters such as temperature, cooling fan speeds, power status, operating system (O/S) status, and the like. The BMC monitors the sensors and can send alerts to a system administrator via the network if any of the parameters do not stay within pre-set limits, indicating a potential failure of the system. The administrator can also remotely communicate with the BMC to take certain corrective actions, such as resetting or power cycling the system to get a hung O/S running again. These abilities can often save on the total cost of ownership of an IHS, particularly when implemented in large clusters, such as server farms.
Embodiments of the present disclosure provide a system and method to provide a thread-safe environment for non-thread-safe objects used with multi-thread processes. According to one embodiment, an Information Handling System (IHS) includes at least one processor, and at least one memory having program instructions that upon execution by at least one processor, cause the IHS to create multiple objects including at least one non-thread-safe object, generate a thread-safe interface associated with the non-thread-safe object, and when a task request is received from a multi-threaded process, generate a single thread to perform a task with the non-thread-safe object. The task is associated with the task request.
According to another embodiment, a thread-safe interfacing method for non-thread-safe objects includes the steps of creating a plurality of objects comprising at least one non-thread-safe object, generating a thread-safe interface associated with the non-thread-safe object, and when a task request is received from a multi-threaded process, generating, by the thread-safe interface, a single thread to perform a task with the non-thread-safe object, the task being associated with the task request.
According to yet another embodiment, a memory storage device is configured with program instructions stored thereon that, upon execution by one or more processors of a client Information Handling System (IHS), cause the client IHS to create a plurality of objects comprising at least one non-thread-safe object, generate a thread-safe interface associated with the non-thread-safe object, and when a task request is received from a multi-threaded process, the thread-safe interface generates a single thread to perform a task with the non-thread-safe object, the task being associated with the task request.
The present invention(s) is/are illustrated by way of example and is/are not limited by the accompanying figures. Elements in the figures are illustrated for simplicity and clarity, and have not necessarily been drawn to scale.
The present disclosure is described with reference to the attached figures. The figures are not drawn to scale, and they are provided merely to illustrate the disclosure. Several aspects of the disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the disclosure. The present disclosure is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present disclosure.
Certain IHSs may be configured with BMCs that are used to monitor, and in some cases manage computer hardware components of their respective IHSs. A BMC is normally programmed using a firmware stack that configures the BMC for performing out-of-band (e.g., external to a computer's operating system or BIOS) hardware management tasks. The BMC firmware can support industry-standard specifications, such as the Intelligent Platform Management Interface (BMC) and Systems Management Architecture of Server Hardware (SMASH) for computer system administration. The BMC (also referred to as a remote access controller) may include a processor, memory, and an out-of-band network interface separate from and physically isolated from an in-band network interface of the IHS, and/or other embedded resources. In certain embodiments, the BMC may include or may be part of a BMC (e.g., a DELL Remote Access Controller (DRAC) or an Integrated DRAC (iDRAC)).
The BMC firmware is normally proprietary and is often developed by the vendor and shipped along with the BMC to the end user. Nevertheless, industry trends have migrated toward custom BMC firmware stacks (e.g., operating systems) that allow the end user greater control over how the BMC operates. OpenBMC is one example standard under which custom BMC firmware stacks may be generated. In general, openBMC is a collaborative open-source Linux distribution for BMCs meant to work across heterogeneous systems that include enterprise, high-performance computing (HPC), telecommunications, and cloud-scale data centers.
Advances in BMC design has led to the development of an Inter-Process Communication (IPC) and remote procedure call (RPC) mechanism, such as Desktop Bus (D-Bus), which typically operate outside the operating-system space. D-Bus is usually provided as a “daemon” process that functions in the background to effectively facilitate exchange of IPC messages between processes that provide various services. Implementation of D-Bus in BMCs are advantageous in that it provides for abstraction of invoking interfaces of a service and responding to interface invocations. Thus, the service may be shielded from, among other things, serialization and deserialization of data shared with other services, thus yielding portable services that may be easily migrated from one platform to another. Because D-Bus is a standard feature provided by the openBMC platform, it may be beneficial to re-use established services on other platforms, such as vendor-based platforms, such as Open Server Manager (OMS) provided by DELL TECHNOLOGIES and vice-versa.
Nevertheless, while implementation of D-Bus in BMCs may provide enhanced manageability, transparency, and customization, its implementation has not been without drawbacks. For example, current implementations of are developed using the C and/or C++ programming language with Application Program Interfaces (APIs) that are not thread-safe. A thread-safe API generally refers to one that functions correctly while being called from multiple threads, in spite of the scheduling (e.g., timing) of those threads that are calling the thread-safe API. An application may take advantage of parallel threading in which two or more tasks execute on different threads that access the same data object. Despite the advantages provided by parallel threading, the process of developing bug free, multi-thread software can be challenging. Particular challenges may exist in scenarios where tasks when executing asynchronously on parallel program threads must access the same instance of a data object. In such a scenario, asynchronous execution may result in unpredictable or unstable behavior.
Because many C and C++ APIs are not thread safe, it may be difficult for threaded applications to make use of them because, among other things, converting the application to be non-threaded may be sometimes difficult. D-Bus services are an example of non-thread safe APIs. Conventionally, one solution has been to only use the non-thread safe APIs from only one of the threads. This solution, however, may be difficult in legacy multi-threaded applications where it is often difficult to sort out what code is running in which threads. Another conventional solution has been to build thread safe API layers on top of the non-thread safe APIs. This solution, however, may be difficult to do in practice.
As will be described in detail herein below, embodiments of the present disclosure provide systems and methods to use non-thread safe APIs in threaded programs using thread-safe interfaces, which in one embodiment, may include using C++ lambdas. The C++ programming language provides a mechanism to create lambdas which are basically a package of data and a function. C++ code in any thread can create a lambda that use a non-thread safe API such that each lambda can be passed to a single thread for execution on the non-thread-safe API. Once the lambda single thread (e.g., thread funnel) is created, any non-thread safe API can be used by a threaded application safely and with little or no modifications to the non-thread-safe API.
Chassis 100 may include one or more bays that each receive an individual sled (that may be additionally or alternatively referred to as a tray, blade, and/or node), such as compute sleds 105a-n and storage sleds 115a-n. Chassis 100 may support a variety of different numbers (e.g., 4, 8, 16, 32), sizes (e.g., single-width, double-width) and physical configurations of bays. Embodiments may include additional types of sleds that provide various storage, power and/or processing capabilities. For instance, sleds installable in chassis 100 may be dedicated to providing power management or networking functions. Sleds may be individually installed and removed from the chassis 100, thus allowing the computing and storage capabilities of a chassis to be reconfigured by swapping the sleds with diverse types of sleds, in some cases at runtime without disrupting the ongoing operations of the other sleds installed in the chassis 100.
Multiple chassis 100 may be housed within a rack. Data centers may utilize large numbers of racks, with various different types of chassis installed in various configurations of racks. The modular architecture provided by the sleds, chassis and racks allow for certain resources, such as cooling, power, and network bandwidth, to be shared by the compute sleds 105a-n and storage sleds 115a-n, thus providing efficiency improvements and supporting greater computational loads. For instance, certain computational tasks, such as computations used in machine learning and other artificial intelligence systems, may utilize computational and/or storage resources that are shared within an IHS, within an individual chassis 100 and/or within a set of IHSs that may be spread across multiple chassis of a data center.
Implementing computing systems that span multiple processing components of chassis 100 is aided by high-speed data links between these processing components, such as PCIe connections that form one or more distinct PCIe switch fabrics that are implemented by PCIe switches 135a-n, 165a-n installed in the sleds 105a-n, 115a-n of the chassis. These high-speed data links may be used to support algorithm implementations that span multiple processing, networking, and storage components of an IHS and/or chassis 100. For instance, computational tasks may be delegated to a specific processing component of an IHS, such as to a hardware accelerator 185a-n that may include one or more programmable processors that operate separate from the main CPUs 170a-n of computing sleds 105a-n. In various embodiments, such hardware accelerators 185a-n may include DPUs (Data Processing Units), GPUs (Graphics Processing Units), SmartNICs (Smart Network Interface Card) and/or FPGAs (Field Programmable Gate Arrays). These hardware accelerators 185a-n operate according to firmware instructions that may be occasionally updated, such as to adapt the capabilities of the respective hardware accelerators 185a-n to specific computing tasks.
Chassis 100 may be installed within a rack structure that provides at least a portion of the cooling utilized by the sleds 105a-n, 115a-n installed in chassis 100. In supporting airflow cooling, a rack may include one or more banks of cooling fans that may be operated to ventilate heated air from within the chassis 100 that is housed within the rack. The chassis 100 may alternatively or additionally include one or more cooling fans 130 that may be similarly operated to ventilate heated air away from sleds 105a-n, 115a-n installed within the chassis. In this manner, a rack and a chassis 100 installed within the rack may utilize various configurations and combinations of cooling fans 130 to cool the sleds 105a-n, 115a-n and other components housed within chassis 100.
The sleds 105a-n, 115a-n may be individually coupled to chassis 100 via connectors that correspond to the bays provided by the chassis 100 and that physically and electrically couple an individual sled to a backplane 160. Chassis backplane 160 may be a printed circuit board that includes electrical traces and connectors that are configured to route signals between the various components of chassis 100 that are connected to the backplane 160 and between different components mounted on the printed circuit board of the backplane 160. In the illustrated embodiment, the connectors for use in coupling sleds 105a-n, 115a-n to backplane 160 include PCIe couplings that support high-speed data links with the sleds 105a-n, 115a-n. In various embodiments, backplane 160 may support diverse types of connections, such as cables, wires, midplanes, connectors, expansion slots, and multiplexers. In certain embodiments, backplane 160 may be a motherboard that includes various electronic components installed thereon. Such components installed on a motherboard backplane 160 may include components that implement all or part of the functions described with regard to the SAS (Serial Attached SCSI) expander 150, I/O controllers 145, network controller 140, chassis management controller 125 and power supply unit 136.
In certain embodiments, each individual sled 105a-n, 115a-n-n may be an IHS such as described with regard to IHS 200 of
In high-availability computing systems, such as may be implemented using embodiments of chassis 100, any downtime that can be avoided is preferred. As described above, firmware updates are expected in the administration and operation of data centers, but it is preferable to avoid any downtime in making such firmware updates. For instance, in updating the firmware of the individual hardware components of the chassis 100, it is preferable that such updates can be made without having to reboot the chassis. As described in additional detail below, it is also preferable that updates to the firmware of individual hardware components of sleds 105a-n, 115a-n be likewise made without having to reboot the respective sled of the hardware component that is being updated.
As illustrated, each sled 105a-n, 115a-n includes a respective BMC 110a-n, 120a-n. As described in additional detail with regard to
The BMC s 110a-n, 120a-n that are present in chassis 100 may support secure connections with a remote management interface 101. In some embodiments, remote management interface 101 provides a remote administrator with various capabilities for remotely administering the operation of an IHS, including initiating updates to the firmware used by hardware components installed in the chassis 100. For example, remote management interface 101 may provide capabilities by which an administrator can initiate updates to all of the storage drives 175a-n installed in a chassis 100, or to all of the storage drives 175a-n of a particular model or manufacturer. In some instances, remote management interface 101 may include an inventory of the hardware, software, and firmware of chassis 100 that is being remotely managed through the operation of the BMC s 110a-n, 120a-n. The remote management interface 101 may also include various monitoring interfaces for evaluating telemetry data collected by the BMC s 110a-n, 120a-n. In some embodiments, remote management interface 101 may communicate with BMC s 110a-n, 120a-n via a protocol such the Redfish remote management interface.
In the illustrated embodiment, chassis 100 includes one or more compute sleds 105a-n that are coupled to the backplane 160 and installed within one or more bays or slots of chassis 100. Each of the individual compute sleds 105a-n may be an IHS, such as described with regard to
As illustrated, chassis 100 includes one or more storage sleds 115a-n that are coupled to the backplane 160 and installed within one or more bays of chassis 100 in a similar manner to compute sleds 105a-n. Each of the individual storage sleds 115a-n may include various different numbers and types of storage devices. As described in additional detail with regard to
As illustrated, a storage sled 115a may include one or more DPUs (Data Processing Units) 190 that provide access to and manage the operations of the storage drives 175a of the storage sled 115a. Use of a DPU 190 in this manner provides low-latency and high-bandwidth access to numerous SSDs 175a. These SSDs 175a may be utilized in parallel through NVMe transmissions that are supported by the PCIe switch 165a that connects the SSDs 175a to the DPU 190. In some instances, PCIe switch 165a may be an integrated component of a DPU 190. The immense data storage and retrieval capabilities provided by such storage sled 115a implementations may be harnessed by offloading storage operations directed as storage drives 175a to a DPU 190a, and thus without relying on the main CPU of the storage sled, or of any other component of chassis 100. As indicated in
In addition to the data storage capabilities provided by storage sleds 115a-n, chassis 100 may provide access to other storage resources that may be installed components of chassis 100 and/or may be installed elsewhere within a rack that houses the chassis 100. In certain scenarios, such storage drives 155 may be accessed via a SAS expander 150 that is coupled to the backplane 160 of the chassis 100. The SAS expander 150 may support connections to a number of JBOD (Just a Bunch of Disks) storage drives 155 that, in some instances, may be configured and managed individually and without implementing data redundancy across the various drives 155. The additional storage drives 155 may also be at various other locations within a datacenter in which chassis 100 is installed.
In light of the various manners in which storage drives 175a-n, 155 may be coupled to chassis 100, a wide variety of different storage topologies may be supported. Through these supported topologies, storage drives 175a-n, 155 may be logically organized into clusters or other groupings that may be collectively tasked and managed. In some instances, a chassis 100 may include numerous storage drives 175a-n, 155 that are identical, or nearly identical, such as arrays of SSDs of the same manufacturer and model. Accordingly, any firmware updates to storage drives 175a-n, 155 require the updates to be applied within each of these topologies being supported by the chassis 100. Despite the substantial number of different storage drive topologies that may be supported by an individual chassis 100, the firmware used by each of these storage devices 175a-n, 155 may be occasionally updated. In some instances, firmware updates may be limited to a single storage drive, but in other instances, firmware updates may be initiated for a large number of storage drives, such as for all SSDs installed in chassis 100.
As illustrated, the chassis 100 of
Chassis 100 may similarly include a power supply unit 136 that provides the components of the chassis with various levels of DC power from an AC power source or from power delivered via a power system provided by a rack within which chassis 100 may be installed. In certain embodiments, power supply unit 136 may be implemented within a sled that may provide chassis 100 with redundant, hot-swappable power supply units. Power supply unit 136 may operate according to firmware instructions that may be occasionally updated.
Chassis 100 may also include various I/O controllers 145 that may support various I/O ports, such as USB ports that may be used to support keyboard and mouse inputs and/or video display capabilities. Each of the I/O controllers 145 may operate according to firmware instructions that may be occasionally updated. Such I/O controllers 145 may be utilized by the chassis management controller 125 to support various KVM (Keyboard, Video and Mouse) 125a capabilities that provide administrators with the ability to interface with the chassis 100. The chassis management controller 125 may also include a storage module 125c that provides capabilities for managing and configuring certain aspects of the storage devices of chassis 100, such as the storage devices provided within storage sleds 115a-n and within the JBOD 155.
In addition to providing support for KVM 125a capabilities for administering chassis 100, chassis management controller 125 may support various additional functions for sharing the infrastructure resources of chassis 100. In some scenarios, chassis management controller 125 may implement tools for managing the power supply unit 136, network controller 140 and airflow cooling fans 130 that are available via the chassis 100. As described, the airflow cooling fans 130 utilized by chassis 100 may include an airflow cooling system that is provided by a rack in which the chassis 100 may be installed and managed by a cooling module 125b of the chassis management controller 125.
For purposes of this disclosure, an IHS may include any instrumentality or aggregate of instrumentalities operable to compute, calculate, determine, classify, process, transmit, receive, retrieve, originate, switch, store, display, communicate, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes. For example, an IHS may be a personal computer (e.g., desktop or laptop), tablet computer, mobile device (e.g., Personal Digital Assistant (PDA) or smart phone), server (e.g., blade server or rack server), a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. An IHS may include Random Access Memory (RAM), one or more processing resources such as a Central Processing Unit (CPU) or hardware or software control logic, Read-Only Memory (ROM), and/or other types of nonvolatile memory. Additional components of an IHS may include one or more disk drives, one or more network ports for communicating with external devices as well as various I/O devices, such as a keyboard, a mouse, touchscreen, and/or a video display. As described, an IHS may also include one or more buses operable to transmit communications between the various hardware components. An example of an IHS is described in more detail below.
IHS 200 may utilize one or more system processors 205, that may be referred to as CPUs (central processing units). In some embodiments, CPUs 205 may each include a plurality of processing cores that may be separately delegated with computing tasks. Each of the CPUs 205 may be individually designated as a main processor and as a co-processor, where such designations may be based on delegation of specific types of computational tasks to a CPU 205. In some embodiments, CPUs 205 may each include an integrated memory controller that may be implemented directly within the circuitry of each CPU 205. In some embodiments, a memory controller may be a separate integrated circuit that is located on the same die as the CPU 205. Each memory controller may be configured to manage the transfer of data to and from a system memory 210 of the IHS, in some cases using a high-speed memory bus. The system memory 210 is coupled to CPUs 205 via one or more memory buses 205a that provide the CPUs 205 with high-speed memory used in the execution of computer program instructions by the CPUs 205. Accordingly, system memory 210 may include memory components, such as static RAM (SRAM), dynamic RAM (DRAM), NAND Flash memory, suitable for supporting high-speed memory operations by the CPUs 205. In certain embodiments, system memory 210 may combine persistent non-volatile memory and volatile memory.
In certain embodiments, the system memory 210 may be comprised of multiple removable memory modules. The system memory 210 of the illustrated embodiment includes removable memory modules 210a-n. Each of the removable memory modules 210a-n may correspond to a printed circuit board memory socket that receives a removable memory module 210a-n, such as a DIMM (Dual In-line Memory Module), that can be coupled to the socket and then decoupled from the socket as needed, such as to upgrade memory capabilities or to replace faulty memory modules. Other embodiments of IHS system memory 210 may be configured with memory socket interfaces that correspond to diverse types of removable memory module form factors, such as a Dual In-line Package (DIP) memory, a Single In-line Pin Package (SIPP) memory, a Single In-line Memory Module (SIMM), and/or a Ball Grid Array (BGA) memory.
IHS 200 may utilize a chipset that may be implemented by integrated circuits that are connected to each CPU 205. All or portions of the chipset may be implemented directly within the integrated circuitry of an individual CPU 205. The chipset may provide the CPU 205 with access to a variety of resources accessible via one or more in-band buses. IHS 200 may also include one or more I/O ports 215 that may be used to couple the IHS 200 directly to other IHSs, storage resources, diagnostic tools, and/or other peripheral components. A variety of additional components may be coupled to CPUs 205 via a variety of in-line buses. For instance, CPUs 205 may also be coupled to a power management unit 220 that may interface with a power system of the chassis 100 in which IHS 200 may be installed. In addition, CPUs 205 may collect information from one or more sensors 225 via a management bus.
In certain embodiments, IHS 200 may operate using a BIOS (Basic Input/Output System) that may be stored in a non-volatile memory accessible by the CPUs 205. The BIOS may provide an abstraction layer by which the operating system of the IHS 200 interfaces with hardware components of the HIS 200. Upon powering or restarting IHS 200, CPUs 205 may utilize BIOS instructions to initialize and test hardware components coupled to the IHS 200, including both components permanently installed as components of the motherboard of IHS 200 and removable components installed within various expansion slots supported by the IHS 200. The BIOS instructions may also load an operating system for execution by CPUs 205. In certain embodiments, IHS 200 may utilize Unified Extensible Firmware Interface (UEFI) in addition to or instead of a BIOS. In certain embodiments, the functions provided by a BIOS may be implemented, in full or in part, by the BMC 230.
In some embodiments, IHS 200 may include a TPM (Trusted Platform Module) that may include various registers, such as platform configuration registers, and a secure storage, such as an NVRAM (Non-Volatile Random-Access Memory). The TPM may also include a cryptographic processor that supports various cryptographic capabilities. In IHS embodiments that include a TPM, a pre-boot process implemented by the TPM may utilize its cryptographic capabilities to calculate hash values that are based on software and/or firmware instructions utilized by certain core components of IHS 200, such as the BIOS and boot loader of IHS 200. These calculated hash values may then be compared against reference hash values that were previously stored in a secure non-volatile memory of the IHS 200, such as during factory provisioning of IHS 200. In this manner, a TPM may establish a root of trust that includes core components of IHS 200 that are validated as operating using instructions that originate from a trusted source.
As illustrated, CPUs 205 may be coupled to a network controller 240, such as provided by a Network Interface Controller (NIC) card that provides IHS 200 with communications via one or more external networks, such as the Internet, a LAN, or a WAN. In some embodiments, network controller 240 may be a replaceable expansion card or adapter that is coupled to a connector (e.g., PCIe connector of a motherboard, backplane, midplane, etc.) of IHS 200. In some embodiments, network controller 240 may support high-bandwidth network operations by the IHS 200 through a PCIe interface that is supported by the chipset of CPUs 205. Network controller 240 may operate according to firmware instructions that may be occasionally updated.
As indicated in
Using the available PCIe lanes, the PCIe switches 265a-b may be used to implement a PCIe switch fabric. Also through this switch fabric, PCIe NVMe (Non-Volatile Memory Express) transmission may be supported and utilized in high-speed communications with SSDs, such as storage drives 235a-b, of the IHS 200. Also through this switch fabric, PCIe VDM (Vendor Defined Messaging) may be supported and utilized in managing PCIe-compliant hardware components of the IHS 200, such as in updating the firmware utilized by the hardware components.
As indicated in
As illustrated, PCIe switch 265a is coupled via a PCIe link to a hardware accelerator 250, such as a DPU, SmartNIC, GPU and/or FPGA, that may be a connected to the IHS 200 via a removable card or baseboard that couples to a PCIe connector of the IHS 200. In some embodiments, hardware accelerator 250 includes a programmable processor that can be configured for offloading functions from CPUs 205. In some embodiments, hardware accelerator 250 may include a plurality of programmable processing cores and/or hardware accelerators, which may be used to implement functions used to support devices coupled to the IHS 200. In some embodiments, the processing cores of hardware accelerator 250 include ARM (advanced RISC (reduced instruction set computing) machine) processing cores. In other embodiments, the cores of the DPUs may include MIPS (microprocessor without interlocked pipeline stages) cores, RISC-V cores, or CISC (complex instruction set computing) (i.e., ×86) cores. Hardware accelerator may operate according to firmware instructions that may be occasionally updated.
In the illustrated embodiment, the programmable capabilities of hardware accelerator 250 implement functions used to support storage drives 235a, such as SSDs. In such storage drive topologies, hardware accelerator 250 may implement processing of PCIe NVMe communications with storage drives 235a, thus supporting high-bandwidth connections with the storage drives. Hardware accelerator 250 may also include one or more memory devices used to store program instructions executed by the processing cores and/or used to support the operation of storage drives 235a such as in implementing cache memories and buffers utilized in support of high-speed operation of these storage drives, and in some cases may be used to provide high-availability and high-throughput implementations of the read, write and other I/O operations that are supported by these storage drives 235a. In other embodiments, hardware accelerator 250 may implement operations in support of other types of devices and may similarly support high-bandwidth PCIe connections with these devices. For instance, in various embodiments, hardware accelerator 250 may support high-bandwidth connections, such as PCIe connections, with networking devices in implementing functions of a network switch, compression and codec functions, virtualization operations or cryptographic functions.
As illustrated in
As illustrated in
As described, IHS 200 includes a BMC 230 that supports remote management of IHS 200 and of various internal components of IHS 200. In certain embodiments, BMC 230 may operate from a different power plane from the processors 205 and other components of IHS 200, thus allowing the BMC 230 to operate, and management tasks to proceed, while the processing cores of IHS 200 are powered off. Various functions provided by the BIOS, including launching the operating system of the IHS 200, and/or functions of a TPM may be implemented or supplemented by the BMC 230. In some embodiments, the BMC 230 may perform various functions to verify the integrity of the IHS 200 and its hardware components prior to initialization of the operating system of IHS 200 (i.e., in a bare-metal state). In some embodiments, certain operations of the BMC 230, such as the operations described herein for updating firmware used by managed hardware components of IHS 200, may operate using validated instructions, and thus within the root of trust of IHS 200.
In some embodiments, BMC 230 may include a service processor 230a, or specialized microcontroller, which operates management software that supports remote monitoring and administration of IHS 200. The management operations supported by BMC 230 may be remotely initiated, updated, and monitored via a remote management interface 101, such as described with regard to
In some embodiments, BMC 230 may implement monitoring and management operations using MCTP (Management Component Transport Protocol) messages that may be communicated to managed devices 205, 235a-b, 240, 250, 255, 260 via management connections supported by a sideband bus 253. In some embodiments, the BMC 230 may additionally or alternatively use MCTP messaging to transmit Vendor Defined Messages (VDMs) via the in-line PCIe switch fabric supported by PCIe switches 265a-b. In some instances, the sideband management connections supported by BMC 230 may include PLDM (Platform Level Data Model) management communications with the managed devices 205, 235a-b, 240, 250, 255, 260 of IHS 200.
As illustrated, BMC 230 may include a network adapter 230c that provides the BMC with network access that is separate from the network controller 240 utilized by other hardware components of the IHS 200. Through secure connections supported by network adapter 230c, BMC 230 communicates management information with remote management interface 101. In support of remote monitoring functions, network adapter 230c may support connections between BMC 230 and external management tools using wired and/or wireless network connections that operate using a variety of network technologies. As a non-limiting example of a BMC, the integrated Dell Remote Access Controller (iDRAC) from Dell® is embedded within Dell servers and provides functionality that helps information technology (IT) administrators deploy, update, monitor, and maintain servers remotely.
BMC 230 supports monitoring and administration of the managed devices of an IHS 200 via a sideband bus interface 253. For instance, messages utilized in device and/or system management may be transmitted using I2C sideband bus 253 connections that may be individually established with each of the respective managed devices 205, 235a-b, 240, 250, 255, 260 of the IHS 200 through the operation of an I2C multiplexer 230d of the BMC. As illustrated in
In certain embodiments, the service processor 230a of BMC 230 may rely on an I2C co-processor 230b to implement sideband I2C communications between the BMC 230 and the managed hardware components 205, 235a-b, 240, 250, 255, 260 of the IHS 200. The I2C co-processor 230b may be a specialized co-processor or micro-controller that is configured to implement an I2C bus interface used to support communications with managed hardware components 205, 235a-b, 240, 250, 255, 260 of HIS 200. In some embodiments, the I2C co-processor 230b may be an integrated circuit on the same die as the service processor 230a, such as a peripheral system-on-chip feature that may be provided by the service processor 230a. The sideband I2C bus 253 is illustrated as single line in
In various embodiments, an IHS 200 does not include each of the components shown in
In one embodiment, the BMC firmware 308 may be included with logic to generate lambdas that function as thread-safe interfaces 312 for multi-threaded processes that are executed by the BMC firmware 308. Lambdas generally refer to an unnamed function that is useful for short snippets of code that may be difficult to reuse and are not worth naming. In other words, lambdas have been developed for use in the C and C++ programming language to perform one-off tasks that may not require normal structural paradigms normally associated with other parts of a structured code, such as C or C++. Lambdas may be considered essentially to be a package including data and a function. In one embodiment, the underlying compiler used to generate (e.g., compile and link) the BMC firmware 308 may be a C++ 17 version, or newer version, of the ISO/IEC 14882 standard for the C++ programming language in which its lambda expressions can capture the ‘*this’ parameter by value.
As each new thread 310a-n (collectively 310) is spawned in the BMC firmware 308, it can create a lambda that that interfaces with a non-thread safe API, such as one of the services 306 of the D-Bus 304. Then each lambda can be passed to a single thread 314 for execution. Once the single thread 314 is (e.g., thread funnel) is created, any non-thread safe API can be used by a threaded application safely and with little or no modifications to the non-thread-safe API. While the present embodiment shows a lambda (e.g., thread safe interface 312) corresponding to each service 306, it should be appreciated that a lambda may be created for any non-thread-safe object generated by either the services 306 or the BMC firmware 308 without departing from the spirit and scope of the present disclosure.
The services 306 using the D-Bus 304 may be any suitable type. As shown, services 306 that use the D-Bus 304 may include a Secure Enterprise Key Manager (SEKM) module 306a, a telemetry module 306b, a support assist module 306c, a non-root GUI module 306d, a non-root redfish module 306e, an IPMI module 306f, a SEL/Event logger module 306g, an entity manager 306h, a thermal/PID control module 306i, a GPIO monitor 306j, a LED manager 306k, a power control and state manager 306l, a temp sensor daemon 306m, a Field Replaceable Unit (FRU) device daemon 306n, an IPMB bridge daemon 306o, a Power Supply Unit (PSU) sensor daemon 306p, an NVMe sensor daemon 306q, a fan sensor daemon 306r, an LED controller module 306s, and a GPIO/Buttons module 306t. It should be appreciated that other embodiments may have additional, fewer, or different services 306 than what is shown and described herein.
For the purposes of this disclosure, the term “BMC GUI” may refer broadly to systems that are configured to couple to a management controller, such as a BMC 230, and issue management instructions for an information handling system (e.g., computing device) that is being managed by the management controller. One example of such a system management console is the DELL OpenManage Enterprise (OME) systems management console. In various embodiments, management consoles may be implemented via specialized hardware and/or via software running on a standard information handling system. In one embodiment, a system management console may be deployed on a secure virtual machine (VM), such as a VMWARE Workstation appliance.
The code segment 400 includes an initialization snippet 402, a first lambda function 404, a second lambda function 406, a third lambda function 408, and an error code function 410. Referring specifically to the first lambda function 404, the code ‘std::function<void (void)> Ifunc0=[&]( )->void {argument};’ is providing the thread safe execution, while the argument portion of the code represents code that needs to run thread safe. While the argument shown is shown as a single word, it should be appreciated that the argument can include any number of lines of code, and may be written just like any ordinary in-line code. Additionally, the argument is all executed in a single thread 314 associated with its respective lambda. The second and third lambda functions 406, 408 function at least partially similar to that of the first lambda function 404 and will not be described further for purposes of brevity and clarity of disclosure.
The code segment 400 may be written into any suitable multi-threaded application, such as the BMC firmware 308, that needs to function with non-thread-safe objects. Other portions of the code of the multi-threaded application, such as the initialization snippet 402 and error code function 410 may run in any other thread. For example, local variables ‘error_code’ and ‘an_argument’ can be used just as in ordinary in-line code. Any code represented by the ‘argument’ is sequentially presented to its respective non-thread-safe object using the lambda functions 404, 406, 408; that is, the arguments from each of the lambda functions 404, 406, 408 do not run asynchronously. No initialization for the lambda functions may be required because it is inherently not required with lambda functions. Everything necessary for processing multi-threaded messages through its single thread 314 is handled inside the call ‘TF_init_and_send_work’.
Initially at step 502, the thread-safe interfacing method 500 generates a thread-safe interface 312 for each non-thread-safe object that needs to be run thread-safe. In one embodiment, the thread-safe interface comprises a lambda function. In another embodiment, the lambda function may be one that is built (e.g., compiled and linked) using a compiler conforming to the C++ 17 or newer platform. In yet another embodiment, the non-thread-safe object comprises a D-Bus service 304 or an object generated by the D-Bus service 304. In yet another embodiment, the lambda is written such that task requests to its respective non-thread-safe object are forwarded to the thread-safe interface 312 (e.g., the lambda), such as by overriding the non-thread-safe object.
At step 504, when executed, one thread-safe interface 312 receives a task request intended for its respective non-thread-safe object. The task request may be any type typically sent to the non-thread-safe object, such as a command, instruction, request for data, or any combination thereof. The thread-safe interface 312 then determines at step 506 whether a previous task request is still being processed over the single thread 314 established between the thread-safe interface 312 and non-thread-safe object. If so, processing continues at step 506 to wait until the previous task has been processed; otherwise, the thread-safe interfacing method 500 continues at step 508.
At step 508, the thread-safe interface 312 processes the task request with the non-thread-safe object using the single thread 314. If the task request is being processed while another ensuing task request is received, that ensuing task request may be placed on hold until the task associated with the present task request is finished. The lambdas compiled using C++ 17 or newer possess the means to queue multiple calls to similarly named routines such that its respective single thread 314 always remains thread-safe. Nevertheless, when the present task request has been processed, processing continues at step 504 to process other task requests as they are received.
The aforedescribed process may be performed whenever a multi-threaded process needs to function with a non-thread-safe object. Nevertheless, when use of the thread-safe interfacing method 500 is no longer needed or desired, the 500 ends.
Although
It should be understood that various operations described herein may be implemented in software executed by logic or processing circuitry, hardware, or a combination thereof. The order in which each operation of a given method is performed may be changed, and various operations may be added, reordered, combined, omitted, modified, etc. It is intended that the invention(s) described herein embrace all such modifications and changes and, accordingly, the above description should be regarded in an illustrative rather than a restrictive sense.
Although the invention(s) is/are described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention(s), as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention(s). Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The terms “coupled” or “operably coupled” are defined as connected, although not necessarily directly, and not necessarily mechanically. The terms “a” and “an” are defined as one or more unless stated otherwise. The terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”) and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a system, device, or apparatus that “comprises,” “has,” “includes” or “contains” one or more elements possesses those one or more elements but is not limited to possessing only those one or more elements. Similarly, a method or process that “comprises,” “has,” “includes” or “contains” one or more operations possesses those one or more operations but is not limited to possessing only those one or more operations.
