Patent Application
20230421950
The present disclosure relates to systems and apparatuses in a daisy-chained network.
As electronic components decrease in size, and as performance expectations increase, more components are included in previously un-instrumented or less-instrumented devices. In some settings, the communication infrastructure used to exchange signals between these components (e.g., in a vehicle) has required thick and heavy bundles of cables.
This disclosure is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.
Disclosed herein are systems and techniques for microphone array calibration, as well as communication systems in which calibrated microphones may be used. When an array of microphones is used for beamforming (e.g., for noise cancellation), production tolerances among the different microphones in the array can cause performance degradation of certain beamforming algorithms. Generally, once microphones are distributed and/or installed, no further calibration is possible. Systems and methods are disclosed for saving calibration coefficients on a microphone for application when the microphone is in use.
According to one aspect, a system for microphone array calibration comprises: a loudspeaker configured to play a test signal; a microphone array configured to receive the test signal and to generate a plurality of microphone array signals; a reference microphone positioned between the loudspeaker and the microphone array, wherein the reference microphone is configured to receive the test signal and to generate a reference signal; and a calibration calculator configured to process the plurality of microphone array signals and the reference signal, generate a set of filter coefficients, and transmit the set of filter coefficients to the microphone array.
According to some implementations, the system further comprises a memory associated with the microphone array configured to store the set of filter coefficients. In some implementations, the memory is positioned on a microphone array module with the microphone array. In some implementations, the memory is a cloud-based memory accessible by the microphone array. In some implementations, the memory is further configured to store microphone information, including at least one of vendor information, product information, version information, model information, capability information, serial number, make information, configuration information, routing information, and authentication information.
According to some implementations, the system further comprises a plurality of memory modules, wherein each of the plurality of memory modules is associated with a respective microphone of the microphone array. In some implementations, the filter coefficients include phase calibration, frequency calibration, and magnitude calibration. In some implementations, the system further comprises a two-wire interface, wherein transmission of the filter coefficients to the microphone array occurs over the two-wire interface. In some implementations, each of the plurality of microphone array signals is unique and each respective microphone of the microphone array is associated with a respective subset of the set of filter coefficients.
According to another aspect, a method for microphone array calibration, comprises: playing a test signal at a loudspeaker; sampling the test signal at a microphone array; generating a plurality of microphone array signals at the microphone array; sampling the test signal at a reference microphone; generating a reference signal at the reference microphone; generating a set of filter coefficients based on the plurality of microphone array signals and the reference signal; and transmitting the set of filter coefficients to the microphone array.
According to some implementations, sampling the test signal at the microphone array comprises sampling the test signal at each respective microphone of the microphone array. In some implementations, generating a set of filter coefficients comprises generating a respective subset of filter coefficients for each respective microphone. According to some implementations, the method further comprises storing the respective subset of filter coefficients on each respective microphone. According to some implementations, the method further comprises storing the set of filter coefficients on the microphone array. In some implementations, transmitting the set of filter coefficients comprises transmitting the set of filter coefficients over a two-wire bus. According to some implementations, the method further comprises pre-calibrating the loudspeaker using the reference microphone.
According to another aspect, a self-calibrating microphone system comprises: a microphone module including: a microphone configured to receive an audio input signal and output a raw microphone output signal, wherein the microphone is pre-calibrated, and a non-volatile memory configured to store microphone calibration coefficients for the microphone; a processor configured to receive the raw microphone signal and the microphone calibration coefficients, and generate a calibrated microphone signal; and a microphone signal sink configured to receive the calibrated microphone signal from the processor and output the calibrated microphone signal.
According to some implementations, the filter coefficients are configured to provide at least one of phase calibration, frequency calibration, and magnitude calibration. In some implementations, the system further comprises a two-wire bus wherein the processor and the microphone signal sink communicate over the two-wire bus. In some implementations, the processor is further configured to perform a convolution of the raw microphone signal and the microphone calibration coefficients to generate the calibrated microphone signal.
The present disclosure is best understood from the following detailed description in conjunction with the accompanying drawings. It is emphasized that, in accordance with the standard practice in the industry, various features are not necessarily drawn to scale, and are used for illustration purposes only. Where a scale is shown, explicitly or implicitly, it provides only one illustrative example. In other embodiments, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings.
For a fuller understanding of the nature and advantages of the present invention, reference is made to the following detailed description of preferred embodiments and in connection with the accompanying drawings, in which:
Disclosed herein are systems and techniques for microphone array calibration, as well as communication systems in which calibrated microphones may be used. When an array of microphones is used for beamforming (e.g., as part of a road noise cancellation, other noise cancellation, or selective broadcast application), production tolerances among the different microphones in the array may cause performance degradation of certain beamforming algorithms. Some conventional calibration procedures attempt to address this degradation by generating filter coefficients for the microphones in order to equalize the differences in the magnitudes of the frequency responses of the microphones. However, conventional calibration procedures neglect to consider the impact of phase tolerances across the microphones in an array.
The systems and techniques disclosed herein may provide both phase and magnitude calibration for microphone arrays, resulting in improved performance for beamforming and other applications. Further, various systems and methods are disclosed herein for local storage of calibration coefficients in the microphone array (e.g., at the time of manufacture and calibration). Further, various systems and methods disclosed herein may include central application of the calibration of a microphone array (e.g., in an edge processor at operation time) to replace uncalibrated microphone signals with calibrated microphone signals further down in the signal chain. Any of the microphone array calibration systems and methods disclosed herein may be implemented by the communication systems (e.g., the systems 100) disclosed herein.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
Various components may be referred to or illustrated herein in the singular (e.g., a “processor,” a “peripheral device,” etc.), but this is simply for ease of discussion, and any element referred to in the singular may include multiple such elements in accordance with the teachings herein.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, the term “circuitry” may refer to, be part of, or include an application-specific integrated circuit (ASIC), an electronic circuit, and optical circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware that provide the described functionality.
The main node 102-1 may communicate with the sub nodes 102-2 over a two-wire bus 106. The bus 106 may include different two-wire bus links between adjacent nodes along the bus 106 to connect the nodes along the bus 106 in a daisy-chain fashion. For example, as illustrated in
The host 110 may include a processor that programs the main node 102-1, and acts as the originator and recipient of various payloads transmitted along the bus 106. In some embodiments, the host 110 may be or may include a microcontroller, for example. In particular, the host 110 may be the master of Inter-Integrated Circuit Sound (I2S) communications that happen along the bus 106. The host 110 may communicate with the main node 102-1 via an I2S/Time Division Multiplex (TDM) protocol, a Serial Peripheral Interface (SPI) protocol, and/or an Inter-Integrated Circuit (I2C) protocol. In some embodiments, the main node 102-1 may be a transceiver (e.g., the node transceiver 120 discussed below with reference to
The main node 102-1 may generate “downstream” signals (e.g., data signals, power signals, etc., transmitted away from the main node 102-1 along the bus 106) and receive “upstream” signals (e.g., transmitted toward the main node 102-1 along the bus 106). The main node 102-1 may provide a clock signal for synchronous data transmission over the bus 106. As used herein, “synchronous data” may include data streamed continuously (e.g., audio signals) with a fixed time interval between two successive transmissions to/from the same node along the bus 106. In some embodiments, the clock signal provided by the main node 102-1 may be derived from an I2S input provided to the main node 102-1 by the host 110. A sub node 102-2 may be an addressable network connection point that represents a possible destination for data frames transmitted downstream on the bus 106 or upstream on the bus 106. A sub node 102-2 may also represent a possible source of downstream or upstream data frames. The system 100 may allow for control information and other data to be transmitted in both directions over the bus 106 from one node to the next. One or more of the sub nodes 102-2 may also be powered by signals transmitted over the bus 106.
In particular, each of the main node 102-1 and the sub nodes 102-2 may include a positive upstream terminal (denoted as “AP”), a negative upstream terminal (denoted as “AN”), a positive downstream terminal (denoted as “BP”), and a negative downstream terminal (denoted as “BN”). The positive and negative downstream terminals of a node may be coupled to the positive and negative upstream terminals of the adjacent downstream node, respectively. As shown in
As discussed in detail below, the main node 102-1 may periodically send a synchronization control frame downstream, optionally along with data intended for one or more of the sub nodes 102-2. For example, the main node 102-1 may transmit a synchronization control frame every 1024 bits (representing a superframe) at a frequency of 48 kHz, resulting in an effective bit rate on the bus 106 of 49.152 Mbps. Other rates may be supported, including, for example, 44.1 kHz. The synchronization control frame may allow the sub nodes 102-2 to identify the beginning of each superframe and also, in combination with physical layer encoding/signaling, may allow each sub node 102-2 to derive its internal operational clock from the bus 106. The synchronization control frame may include a preamble for signaling the start of synchronization, as well as control fields that allow for various addressing modes (e.g., normal, broadcast, discovery), configuration information (e.g., writing to registers of the sub nodes 102-2), conveyance of I2C information, conveyance of SPI information, remote control of certain general-purpose input/output (GPIO) pins at the sub nodes 102-2, and other services. A portion of the synchronization control frame following the preamble and the payload data may be scrambled in order to reduce the likelihood that information in the synchronization control frame will be mistaken for a new preamble, and to flatten the spectrum of related electromagnetic emissions.
The synchronization control frame may get passed between sub node 102-2 (optionally along with other data, which may come from the main node 102-1 but additionally or alternatively may come from one or more upstream sub nodes 102-2 or from a sub node 102-2 itself) until it reaches the last sub node 102-2 (i.e., the sub node 2 in
In some embodiments, one or more of the sub nodes 102-2 in the system 100 may be coupled to and communicate with a peripheral device 108. For example, a sub node 102-2 may be configured to read data from and/or write data to the associated peripheral device 108 using I2S, pulse density modulation (PDM), TDM, SPI, and/or I2C protocols, as discussed below. Although the “peripheral device 108” may be referred to in the singular herein, this is simply for ease of discussion, and a single sub node 102-2 may be coupled with zero, one, or more peripheral devices. Examples of peripheral devices that may be included in the peripheral device 108 may include a digital signal processor (DSP), a field programmable gate array (FPGA), an ASIC, an analog to digital converter (ADC), a digital to analog converter (DAC), a codec, a microphone, a microphone array, a speaker, an audio amplifier, a protocol analyzer, an accelerometer or other motion sensor, an environmental condition sensor (e.g., a temperature, humidity, and/or gas sensor), a wired or wireless communication transceiver, a display device (e.g., a touchscreen display), a user interface component (e.g., a button, a dial, or other control), a camera (e.g., a video camera), a memory device, or any other suitable device that transmits and/or receives data. A number of examples of different peripheral device configurations are discussed in detail herein.
In some embodiments, the peripheral device 108 may include any device configured for I2S communication; the peripheral device 108 may communicate with the associated sub node 102-2 via the I2S protocol. In some embodiments, the peripheral device 108 may include any device configured for I2C communication; the peripheral device 108 may communicate with the associated sub node 102-2 via the I2C protocol. In some embodiments, the peripheral device 108 may include any device configured for SPI communication; the peripheral device 108 may communicate with the associated sub node 102-2 via the SPI protocol. In some embodiments, a sub node 102-2 may not be coupled to any peripheral device 108.
A sub node 102-2 and its associated peripheral device 108 may be contained in separate housings and coupled through a wired or wireless communication connection or may be contained in a common housing. For example, a speaker connected as a peripheral device 108 may be packaged with the hardware for an associated sub node 102-2 (e.g., the node transceiver 120 discussed below with reference to
As discussed above, the host 110 may communicate with and control the main node 102-1 using multi-channel I2S, SPI, and/or I2C communication protocols. For example, the host 110 may transmit data via I2S to a frame buffer (not illustrated) in the main node 102-1, and the main node 102-1 may read data from the frame buffer and transmit the data along the bus 106. Analogously, the main node 102-1 may store data received via the bus 106 in the frame buffer, and then may transmit the data to the host 110 via I2S.
Each sub node 102-2 may have internal control registers that may be configured by communications from the main node 102-1. A number of such registers are discussed in detail below. Each sub node 102-2 may receive downstream data and may retransmit the data further downstream. Each sub node 102-2 may receive and/or generate upstream data and/or retransmit data upstream and/or add data to and upstream transaction.
Communications along the bus 106 may occur in periodic superframes. Each superframe may begin with a downstream synchronization control frame; be divided into periods of downstream transmission (also called “downstream portions”), upstream transmission (also called “upstream portions”), and no transmission (where the bus 106 is not driven); and end just prior to transmission of another downstream synchronization control frame. The main node 102-1 may be programmed (by the host 110) with a number of downstream portions to transmit to one or more of the sub nodes 102-2 and a number of upstream portions to receive from one or more of the sub nodes 102-2. Each sub node 102-2 may be programmed (by the main node 102-1) with a number of downstream portions to retransmit down the bus 106, a number of downstream portions to consume, a number of upstream portions to retransmit up the bus 106, and a number of upstream portions in which the sub node 102-2 may transmit data received from the sub node 102-2 from the associated peripheral device 108. Communication along the bus 106 is discussed in further detail below with reference to
Embodiments of the communication systems 100 disclosed herein are unique among conventional communication systems in that all sub nodes 102-2 may receive output data over the bus 106 within the same superframe (e.g., all sub nodes 102-2 may receive the same audio sample without sample delays between the nodes 102). In conventional communication systems, data is buffered and processed in each node before being passed downstream in the next frame to the next node. Consequently, in these conventional communication systems, the latency of data transmission depends on the number of nodes (with each node adding a delay of one audio sample). In the communication systems 100 disclosed herein, the bus 106 may only add one cycle of latency, no matter if the first or last sub node 102-2 receives the data. The same is true for upstream communication; data may be available at an upstream node 102 in the next superframe, no matter which sub node 102-2 provided the data.
Further, in embodiments of the communication systems 100 disclosed herein, downstream data (e.g., downstream audio data) may be put on the bus 106 by the main node 102-1 or by any of the sub nodes 102-2 that are upstream of the receiving sub node 102-2; similarly, upstream data (e.g., upstream audio data) may be put on the bus 106 by any of the sub nodes 102-2 that are downstream of the receiving node 102 (i.e., the main node 102-1 or a sub node 102-2). Such capability allows a sub node 102-2 to provide both upstream and downstream data at a specific time (e.g., a specific audio sample time). For audio data, this data can be received in the next audio sample at any downstream or upstream node 102 without further delays (besides minor processing delays that fall within the superframe boundary). As discussed further herein, control messages (e.g., in a synchronization control frame (SCF)) may travel to the last node 102 (addressing a specific node 102 or broadcast) and an upstream response (e.g., in a synchronization response frame (SRF)) may be created by the last downstream node 102 within the same superframe. Nodes 102 that have been addressed by the SCF change the content of the upstream SRF with their own response. Consequently, within the same audio sample, a control and a response may be fully executed over multiple nodes 102. This is also in contrast to conventional communication systems, in which sample latencies would be incurred between nodes (for relaying messages from one node to the other).
Each of the main node 102-1 and the sub nodes 102-2 may include a transceiver to manage communication between components of the system 100.
The node transceiver 120 may include an upstream differential signaling (DS) transceiver 122 and a downstream DS transceiver 124. The upstream DS transceiver 122 may be coupled to the positive and negative upstream terminals discussed above with reference to
The upstream DS transceiver 122 and the downstream DS transceiver 124 may communicate with bus protocol circuitry 126, and the bus protocol circuitry 126 may communicate with a phased locked loop (PLL) 128 and voltage regulator circuitry 130, among other components. When the node transceiver 120 is powered up, the voltage regulator circuitry 130 may raise a “power good” signal that is used by the PLL 128 as a power-on reset.
As noted above, one or more of the sub nodes 102-2 in the system 100 may receive power transmitted over the bus 106 concurrently with data. For power distribution (which is optional, as some of the sub nodes 102-2 may be configured to have exclusively local power provided to them), the main node 102-1 may place a DC bias on the bus link between the main node 102-1 and the sub node 0 (e.g., by connecting, through a low-pass filter, one of the downstream terminals to a voltage source provided by a voltage regulator and the other downstream terminal to ground). The DC bias may be a predetermined voltage, such as 5 volts, 8 volts, the voltage of a car battery, or a higher voltage. Each successive sub node 102-2 can selectively tap its upstream bus link to recover power (e.g., using the voltage regulator circuitry 130). This power may be used to power the sub node 102-2 itself (and optionally one or more peripheral device 108 coupled to the sub node 102-2). A sub node 102-2 may also selectively bias the bus link downstream for the next-in-line sub node 102-2 with either the recovered power from the upstream bus link or from a local power supply. For example, the sub node 0 may use the DC bias on the upstream link of the bus 106 to recover power for the sub node 0 itself and/or for one or more associated peripheral device 108, and/or the sub node 0 may recover power from its upstream link of the bus 106 to bias its downstream link of the bus 106.
Thus, in some embodiments, each node in the system 100 may provide power to the following downstream node over a downstream bus link. The powering of nodes may be performed in a sequenced manner. For example, after discovering and configuring the sub node 0 via the bus 106, the main node 102-1 may instruct the sub node 0 to provide power to its downstream link of the bus 106 in order to provide power to the sub node 1; after the sub node 1 is discovered and configured, the main node 102-1 may instruct the sub node 1 to provide power to its downstream link of the bus 106 in order to provide power to the sub node 2 (and so on for additional sub nodes 102-2 coupled to the bus 106). In some embodiments, one or more of the sub nodes 102-2 may be locally powered, instead of or in addition to being powered from its upstream bus link. In some such embodiments, the local power source for a given sub node 102-2 may be used to provide power to one or more downstream sub nodes.
In some embodiments, upstream bus interface circuitry 132 may be disposed between the upstream DS transceiver 122 and the voltage regulator circuitry 130, and downstream bus interface circuitry 131 may be disposed between the downstream DS transceiver 124 and the voltage regulator circuitry 130. Since each link of the bus 106 may carry AC (signal) and DC (power) components, the upstream bus interface circuitry 132 and the downstream bus interface circuitry 131 may separate the AC and DC components, providing the AC components to the upstream DS transceiver 122 and the downstream DS transceiver 124, and providing the DC components to the voltage regulator circuitry 130. AC couplings on the line side of the upstream DS transceiver 122 and downstream DS transceiver 124 substantially isolate the transceivers 122 and 124 from the DC component on the line to allow for high-speed bi-directional communications. As discussed above, the DC component may be tapped for power, and the upstream bus interface circuitry 132 and the downstream bus interface circuitry 131 may include a ferrite, a common mode choke, or an inductor, for example, to reduce the AC component provided to the voltage regulator circuitry 130. In some embodiments, the upstream bus interface circuitry 132 may be included in the upstream DS transceiver 122, and/or the downstream bus interface circuitry 131 may be included in the downstream DS transceiver 124; in other embodiments, the filtering circuitry may be external to the transceivers 122 and 124.
The node transceiver 120 may include a transceiver 127 for I2S, TDM, and PDM communication between the node transceiver 120 and an external device 155. Although the “external device 155” may be referred to in the singular herein, this is simply for ease of illustration, and multiple external devices may communicate with the node transceiver 120 via the I2S/TDM/PDM transceiver 127. As known in the art, the I2S protocol is for carrying pulse code modulated (PCM) information (e.g., between audio chips on a printed circuit board (PCB)). As used herein, “I2S/TDM” may refer to an extension of the I2S stereo (2-channel) content to multiple channels using TDM. As known in the art, PDM may be used in sigma delta converters, and in particular, PDM format may represent an over-sampled 1-bit sigma delta ADC signal before decimation. PDM format is often used as the output format for digital microphones. The I2S/TDM/PDM transceiver 127 may be in communication with the bus protocol circuitry 126 and pins for communication with the external device 155. Six pins, BCLK, SYNC, DTX[1:0], and DRX[1:0], are illustrated in
When the node transceiver 120 is included in the main node 102-1, the external device 155 may include the host 110, and the I2S/TDM/PDM transceiver 127 may provide an I2S slave (regarding BCLK and SYNC) that can receive data from the host 110 and send data to the host 110 synchronously with an I2S interface clock of the host 110. In particular, an I2S frame synchronization signal may be received at the SYNC pin as an input from the host 110, and the PLL 128 may use that signal to generate clocks. When the node transceiver 120 is included in a sub node 102-2, the external device 155 may include one or more peripheral devices 108, and the I2S/TDM/PDM transceiver 127 may provide an I2S clock master (for BCLK and SYNC) that can control I2S communication with the peripheral device 108. In particular, the I2S/TDM/PDM transceiver 127 may provide an I2S frame synchronization signal at the SYNC pin as an output. Registers in the node transceiver 120 may determine which and how many I2S/TDM channels are being transmitted as data slots over the bus 106. A TDM mode (TDMMODE) register in the node transceiver 120 may store a value of how many TDM channels fit between consecutive SYNC pulses on a TDM transmit or receive pin. Together with knowledge of the channel size, the node transceiver 120 may automatically set the BCLK rate to match the number of bits within the sampling time (e.g., 48 kHz).
The node transceiver 120 may include a transceiver 129 for I2C communication between the node transceiver 120 and an external device 157. Although the “external device 157” may be referred to in the singular herein, this is simply for ease of illustration, and multiple external devices may communicate with the node transceiver 120 via the I2C transceiver 129. As known in the art, the I2C protocol uses clock (SCL) and data (SDA) lines to provide data transfer. The I2C transceiver 129 may be in communication with the bus protocol circuitry 126 and pins for communication with the external device 157. Four pins, ADR1, ADR2, SDA, and SCL are illustrated in
The node transceiver 120 may include a transceiver 136 for SPI communication between the node transceiver 120 and an external device 138. Although the “external device 138” may be referred to in the singular herein, this is simply for ease of illustration, and multiple external devices may communicate with the node transceiver 120 via the SPI transceiver 136. As known in the art, the SPI protocol uses slave select (SS), clock (BCLK), master-out-slave-in (MOSI), and master-in-slave-out (MISO) data lines to provide data transfer, and pins corresponding to these four lines are illustrated in
The node transceiver 120 may include an interrupt request (IRQ) pin in communication with the bus protocol circuitry 126. When the node transceiver 120 is included in the main node 102-1, the bus protocol circuitry 126 may provide event-driven interrupt requests toward the host 110 via the IRQ pin. When the node transceiver 120 is included in a sub node 102-2 (e.g., when the MSTR pin is low), the IRQ pin may serve as a GPIO pin with interrupt request capability. The node transceiver 120 may include other pins in addition to those shown in
The system 100 may operate in any of a number of different operational modes. The nodes on the bus 106 may each have a register indicating which operational mode is currently enabled. Descriptions follow of examples of various operational modes that may be implemented. In a standby operational mode, bus activity is reduced to enable global power savings; the only traffic required is a minimal downstream preamble to keep the PLLs of each node (e.g., the PLL 128) synchronized. In standby operational mode, reads and writes across the bus 106 are not supported. In a discovery operational mode, the main node 102-1 may send predetermined signals out along the bus 106 and wait for suitable responses to map out the topology of sub nodes 102-2 distributed along the bus 106. In a normal operational mode, full register access may be available to and from the sub nodes 102-2 as well as access to and from peripheral devices 108 over the bus 106. Normal mode may be globally configured by the host 110 with or without synchronous upstream data and with or without synchronous downstream data.
For example, in some embodiments, communication along the bus 106 may be encoded using a clock first, transition on zero differential Manchester coding scheme. According to such an encoding scheme, each bit time begins with a clock transition. If the data value is zero, the encoded signal transitions again in the middle of the bit time. If the data value is one, the encoded signal does not transition again. The preamble 182 illustrated in
The bus protocol circuitry 126 may include differential Manchester decoder circuitry that runs on a clock recovered from the bus 106 and that detects the synchronization control frame 180 to send a frame sync indicator to the PLL 128. In this manner, the synchronization control frame 180 may be detected without using a system clock or a higher-speed oversampling clock. Consequently, the sub nodes 102-2 can receive a PLL synchronization signal from the bus 106 without requiring a crystal clock source at the sub nodes 102-2.
As noted above, communications along the bus 106 may occur in periodic superframes.
In
The period of upstream transmission 194 may include a synchronization response frame 197 and Y upstream data slots 199, where Y can be zero. In some embodiments, each sub node 102-2 may consume a portion of the downstream data slots 198. The last sub node (e.g., sub node 2 in
As discussed above, the synchronization control frame 180 may begin each downstream transmission. In some embodiments, the synchronization control frame 180 may be 64 bits in length, but any other suitable length may be used. The synchronization control frame 180 may begin with the preamble 182, as noted above. In some embodiments, when the synchronization control frame 180 is retransmitted by a sub node 102-2 to a downstream sub node 102-2, the preamble 182 may be generated by the transmitting sub node 102-2, rather than being retransmitted.
The control data 184 of the synchronization control frame 180 may include fields that contain data used to control transactions over the bus 106. Examples of these fields are discussed below, and some embodiments are illustrated in
In some embodiments, the synchronization control frame 180 may include a count (CNT) field. The CNT field may have any suitable length (e.g., 2 bits) and may be incremented (modulo the length of the field) from the value used in the previous superframe. A sub node 102-2 that receives a CNT value that is unexpected may be programmed to return an interrupt.
In some embodiments, the synchronization control frame 180 may include a node addressing mode (NAM) field. The NAM field may have any suitable length (e.g., 2 bits) and may be used to control access to registers of a sub node 102-2 over the bus 106. In normal mode, registers of a sub node 102-2 may be read from and/or written to based on the ID of the sub node 102-2 and the address of the register. Broadcast transactions are writes which should be taken by every sub node 102-2. In some embodiments, the NAM field may provide for four node addressing modes, including “none” (e.g., data not addressed to any particular sub node 102-2), “normal” (e.g., data unicast to a specific sub node 102-2 specified in the address field discussed below), “broadcast” (e.g., addressed to all sub nodes 102-2), and “discovery.”
In some embodiments, the synchronization control frame 180 may include an I2C field. The I2C field may have any suitable length (e.g., 1 bit) and may be used to indicate that the period of downstream transmission 192 includes an I2C transaction. The I2C field may indicate that the host 110 has provided instructions to remotely access a peripheral device 108 that acts as an I2C slave with respect to an associated sub node 102-2.
In some embodiments, the synchronization control frame 180 may include a node field. The node field may have any suitable length (e.g., 4 bits) and may be used to indicate which sub node is being addressed for normal and I2C accesses. In discovery mode, this field may be used to program an identifier for a newly discovered sub node 102-2 in a node ID register of the sub node 102-2. Each sub node 102-2 in the system 100 may be assigned a unique ID when the sub node 102-2 is discovered by the main node 102-1, as discussed below. In some embodiments, the main node 102-1 does not have a node ID, while in other embodiments, the main node 102-1 may have a node ID. In some embodiments, the sub node 102-2 attached to the main node 102-1 on the bus 106 (e.g., the sub node 0 in
In some embodiments, the synchronization control frame 180 may include a read/write (RW) field. The RW field may have any suitable length (e.g., 1 bit) and may be used to control whether normal accesses are reads (e.g., RW==1) or writes (e.g., RW==0).
In some embodiments, the synchronization control frame 180 may include an address field. The address field may have any suitable length (e.g., 8 bits) and may be used to address specific registers of a sub node 102-2 through the bus 106. For I2C transactions, the address field may be replaced with I2C control values, such as START/STOP, WAIT, RW, and DATA VLD. For discovery transactions, the address field may have a predetermined value (e.g., as illustrated in
In some embodiments, the synchronization control frame 180 may include a data field. The data field may have any suitable length (e.g., 8 bits) and may be used for normal, I2C, and broadcast writes. The RESPCYCS value, multiplied by 4, may be used to determine how many cycles a newly discovered node should allow to elapse between the start of the synchronization control frame 180 being received and the start of the synchronization response frame 197 being transmitted. When the NAM field indicates discovery mode, the node address and data fields discussed below may be encoded as a RESPCYCS value that, when multiplied by a suitable optional multiplier (e.g., 4), indicates the time, in bits, from the end of the synchronization control frame 180 to the start of the synchronization response frame 197. This allows a newly discovered sub node 102-2 to determine the appropriate time slot for upstream transmission.
In some embodiments, the synchronization control frame 180 may include a cyclic redundancy check (CRC) field. The CRC field may have any suitable length (e.g., 16 bits) and may be used to transmit a CRC value for the control data 184 of the synchronization control frame 180 following the preamble 182. In some embodiments, the CRC may be calculated in accordance with the CCITT-CRC error detection scheme.
In some embodiments, at least a portion of the synchronization control frame 180 between the preamble 182 and the CRC field may be scrambled in order to reduce the likelihood that a sequence of bits in this interval will periodically match the preamble 182 (and thus may be misinterpreted by the sub node 102-2 as the start of a new superframe 190), as well as to reduce electromagnetic emissions as noted above. In some such embodiments, the CNT field of the synchronization control frame 180 may be used by scrambling logic to ensure that the scrambled fields are scrambled differently from one superframe to the next. Various embodiments of the system 100 described herein may omit scrambling.
Other techniques may be used to ensure that the preamble 182 can be uniquely identified by the sub nodes 102-2 or to reduce the likelihood that the preamble 182 shows up elsewhere in the synchronization control frame 180, in addition to or in lieu of techniques such as scrambling and/or error encoding as discussed above. For example, a longer synchronization sequence may be used so as to reduce the likelihood that a particular encoding of the remainder of the synchronization control frame 180 will match it. Additionally or alternatively, the remainder of the synchronization control frame may be structured so that the synchronization sequence cannot occur, such as by placing fixed “0” or “1” values at appropriate bits.
The main node 102-1 may send read and write requests to the sub nodes 102-2, including both requests specific to communication on the bus 106 and I2C requests. For example, the main node 102-1 may send read and write requests (indicated using the RW field) to one or more designated sub nodes 102-2 (using the NAM and node fields) and can indicate whether the request is a request for the sub node 102-2 specific to the bus 106, an I2C request for the sub node 102-2, or an I2C request to be passed along to an I2C-compatible peripheral device 108 coupled to the sub node 102-2 at one or more I2C ports of the sub node 102-2.
Turning to upstream communication, the synchronization response frame 197 may begin each upstream transmission. In some embodiments, the synchronization response frame 197 may be 64 bits in length, but any other suitable length may be used. The synchronization response frame 197 may also include a preamble, as discussed above with reference to the preamble 182 of the synchronization control frame 180, followed by data portion. At the end of a downstream transmission, the last sub node 102-2 on the bus 106 may wait until the RESPCYCS counter has expired and then begin transmitting a synchronization response frame 197 upstream. If an upstream sub node 102-2 has been targeted by a normal read or write transaction, a sub node 102-2 may generate its own synchronization response frame 197 and replace the one received from downstream. If any sub node 102-2 does not see a synchronization response frame 197 from a downstream sub node 102-2 at the expected time, the sub node 102-2 will generate its own synchronization response frame 197 and begin transmitting it upstream.
The data portion of the synchronization response frame 197 may include fields that contain data used to communicate response information back to the main node 102-1. Examples of these fields are discussed below, and some embodiments are illustrated in
In some embodiments, the synchronization response frame 197 may include a count (CNT) field. The CNT field may have any suitable length (e.g., 2 bits) and may be used to transmit the value of the CNT field in the previously received synchronization control frame 180.
In some embodiments, the synchronization response frame 197 may include an acknowledge (ACK) field. The ACK field may have any suitable length (e.g., 2 bits), and may be inserted by a sub node 102-2 to acknowledge a command received in the previous synchronization control frame 180 when that sub node 102-2 generates the synchronization response frame 197. Example indicators that may be communicated in the ACK field include wait, acknowledge, not acknowledge (NACK), and retry. In some embodiments, the ACK field may be sized to transmit an acknowledgment by a sub node 102-2 that it has received and processed a broadcast message (e.g., by transmitting a broadcast acknowledgment to the main node 102-1). In some such embodiments, a sub node 102-2 also may indicate whether the sub node 102-2 has data to transmit (which could be used, for example, for demand-based upstream transmissions, such as non-TDM inputs from a keypad or touchscreen, or for prioritized upstream transmission, such as when the sub node 102-2 wishes to report an error or emergency condition).
In some embodiments, the synchronization response frame 197 may include an I2C field. The I2C field may have any suitable length (e.g., 1 bit) and may be used to transmit the value of the I2C field in the previously received synchronization control frame 180.
In some embodiments, the synchronization response frame 197 may include a node field. The node field may have any suitable length (e.g., 4 bits) and may be used to transmit the ID of the sub node 102-2 that generates the synchronization response frame 197.
In some embodiments, the synchronization response frame 197 may include a data field. The data field may have any suitable length (e.g., 8 bits), and its value may depend on the type of transaction and the ACK response of the sub node 102-2 that generates the synchronization response frame 197. For discovery transactions, the data field may include the value of the RESPCYCS field in the previously received synchronization control frame 180. When the ACK field indicates a NACK, or when the synchronization response frame 197 is responding to a broadcast transaction, the data field may include a broadcast acknowledge (BA) indicator (in which the last sub node 102-2 may indicate if the broadcast write was received without error), a discovery error (DER) indicator (indicating whether a newly discovered sub node 102-2 in a discovery transaction matches an existing sub node 102-2), and a CRC error (CER) indicator (indicating whether a NACK was caused by a CRC error).
In some embodiments, the synchronization response frame 197 may include a CRC field. The CRC field may have any suitable length (e.g., 16 bits) and may be used to transmit a CRC value for the portion of the synchronization response frame 197 between the preamble and the CRC field.
In some embodiments, the synchronization response frame 197 may include an interrupt request (IRQ) field. The IRQ field may have any suitable length (e.g., 1 bit) and may be used to indicate that an interrupt has been signaled from a sub node 102-2.
In some embodiments, the synchronization response frame 197 may include an IRQ node (IRQNODE) field. The IRQNODE field may have any suitable length (e.g., 4 bits) and may be used to transmit the ID of the sub node 102-2 that has signaled the interrupt presented by the IRQ field. In some embodiments, the sub node 102-2 for generating the IRQ field will insert its own ID into the IRQNODE field.
In some embodiments, the synchronization response frame 197 may include a second CRC (CRC-4) field. The CRC-4 field may have any suitable length (e.g., 4 bits) and may be used to transmit a CRC value for the IRQ and IRQNODE fields.
In some embodiments, the synchronization response frame 197 may include an IRQ field, an IRQNODE field, and a CRC-4 field as the last bits of the synchronization response frame 197 (e.g., the last 10 bits). As discussed above, these interrupt-related fields may have their own CRC protection in the form of CRC-4 (and thus not protected by the preceding CRC field). Any sub node 102-2 that needs to signal an interrupt to the main node 102-1 will insert its interrupt information into these fields. In some embodiments, a sub node 102-2 with an interrupt pending may have higher priority than any sub node 102-2 further downstream that also has an interrupt pending. The last sub node 102-2 along the bus 106 (e.g., the sub node 2 in
In some embodiments, at least a portion of the synchronization response frame 197 between the preamble 182 and the CRC field may be scrambled in order to reduce emissions. In some such embodiments, the CNT field of the synchronization response frame 197 may be used by scrambling logic to ensure that the scrambled fields are scrambled differently from one superframe to the next. Various embodiments of the system 100 described herein may omit scrambling.
Other techniques may be used to ensure that the preamble 182 can be uniquely identified by the sub nodes 102-2 or to reduce the likelihood that the preamble 182 shows up elsewhere in the synchronization response frame 197, in addition to or in lieu of techniques such as scrambling and/or error encoding as discussed above. For example, a longer synchronization sequence may be used so as to reduce the likelihood that a particular encoding of the remainder of the synchronization response frame 197 will match it. Additionally or alternatively, the remainder of the synchronization response frame may be structured so that the synchronization sequence cannot occur, such as by placing fixed “0” or “1” values at appropriate bits.
When the node transceiver 120 is preparing data for transmission along the bus 106, preamble circuitry 156 may be configured to generate preambles for synchronization frames for transmission, and to receive preambles from received synchronization frames. In some embodiments, a downstream synchronization control frame preamble may be sent by the main node 102-1 every 1024 bits. As discussed above, one or more sub nodes 102-2 may synchronize to the downstream synchronization control frame preamble and generate local, phase-aligned main clocks from the preamble.
CRC insert circuitry 158 may be configured to generate one or more CRCs for synchronization frames for transmission. Frame/compress circuitry 160 may be configured to take incoming data from the I2S/TDM/PDM transceiver 127 (e.g., from a frame buffer associated with the transceiver 127), the I2C transceiver 129, and/or the SPI transceiver 136, optionally compress the data, and optionally generate parity check bits or error correction codes (ECC) for the data. A multiplexer (MUX) 162 may multiplex a preamble from the preamble circuitry 156, synchronization frames, and data into a stream for transmission. In some embodiments, the transmit stream may be scrambled by scrambling circuitry 164 before transmission.
For example, in some embodiments, the frame/compress circuitry 160 may apply a floating point compression scheme. In such an embodiment, the control circuitry 154 may transmit 3 bits to indicate how many repeated sign bits are in the number, followed by a sign bit and N-4 bits of data, where N is the size of the data to be transmitted over the bus 106. The use of data compression may be configured by the main node 102-1 when desired.
In some embodiments, the receive stream entering the node transceiver 120 may be descrambled by the descrambling circuitry 166. A demultiplexer (DEMUX) 168 may demultiplex the preamble, synchronization frames, and data from the receive stream. CRC check circuitry 159 on the receive side may check received synchronization frames for the correct CRC. When the CRC check circuitry 159 identifies a CRC failure in an incoming synchronization control frame 180, the control circuitry 154 may be notified of the failure and will not perform any control commands in the control data 184 of the synchronization control frame 180. When the CRC check circuitry 159 identifies a CRC failure in an incoming synchronization response frame 197, the control circuitry 154 may be notified of the failure and may generate an interrupt for transmission to the host 110 in an interrupt frame. Deframe/decompress circuitry 170 may accept receive data, optionally check its parity, optionally perform error detection and correction (e.g., single error correction—double error detection (SECDED)), optionally decompress the data, and may write the receive data to the I2S/TDM/PDM transceiver 127 (e.g., a frame buffer associated with the transceiver 127), the I2C transceiver 129, and/or the SPI transceiver 136.
As discussed above, upstream and downstream data may be transmitted along the bus 106 in TDM data slots within a superframe 190. The control circuitry 154 may include registers dedicated to managing these data slots on the bus 106, a number of examples of which are discussed below. When the control circuitry 154 is included in a main node 102-1, the values in these registers may be programmed into the control circuitry 154 by the host 110. When the control circuitry 154 is included in a sub node 102-2, the values in these registers may be programmed into the control circuitry 154 by the main node 102-1.
In some embodiments, the control circuitry 154 may include a downstream slots (DNSLOTS) register. When the node transceiver 120 is included in the main node 102-1, this register may hold the value of the total number of downstream data slots. This register may also define the number of data slots that will be used for combined I2S/TDM/PDM receive by the I2S/TDM/PDM transceiver 127 in the main node 102-1. In a sub node 102-2, this register may define the number of data slots that are passed downstream to the next sub node 102-2 before or after the addition of locally generated downstream slots, as discussed in further detail below with reference to LDNSLOTS.
In some embodiments, the control circuitry 154 may include a local downstream slots (LDNSLOTS) register. This register may be unused in the main node 102-1. In a sub node 102-2, this register may define the number of data slots that the sub node 102-2 will use and not retransmit. Alternatively, this register may define the number of slots that the sub node 102-2 may contribute to the downstream link of the bus 106.
In some embodiments, the control circuitry 154 may include an upstream slots (UPSLOTS) register. In the main node 102-1, this register may hold the value of the total number of upstream data slots. This register may also define the number of slots that will be used for I2S/TDM transmit by the I2S/TDM/PDM transceiver 127 in the main node 102-1. In a sub node 102-2, this register may define the number of data slots that are passed upstream before the sub node 102-2 begins to add its own data.
In some embodiments, the control circuitry 154 may include a local upstream slots (LUPSLOTS) register. This register may be unused in the main node 102-1. In a sub node 102-2, this register may define the number of data slots that the sub node 102-2 will add to the data received from downstream before it is sent upstream. This register may also define the number of data slots that will be used for combined I2S/TDM/PDM receive by the I2S/TDM/PDM transceiver 127 in the sub node 102-2.
In some embodiments, the control circuitry 154 may include a broadcast downstream slots (BCDNSLOTS) register. This register may be unused in the main node 102-1. In a sub node 102-2, this register may define the number of broadcast data slots. In some embodiments, broadcast data slots may always come at the beginning of the data field. The data in the broadcast data slots may be used by multiple sub nodes 102-2 and may be passed downstream by all sub nodes 102-2 whether or not they are used.
In some embodiments, the control circuitry 154 may include a slot format (SLOTFMT) register. This register may define the format of data for upstream and downstream transmissions. The data size for the I2S/TDM/PDM transceiver 127 may also be determined by this register. In some embodiments, valid data sizes include 8, 12, 16, 20, 24, 28, and 32 bits. This register may also include bits to enable floating point compression for downstream and upstream traffic. When floating point compression is enabled, the I2S/TDM data size may be 4 bits larger than the data size over the bus 106. All nodes in the system 100 may have the same values for SLOTFMT when data slots are enabled, and the nodes may be programmed by a broadcast write so that all nodes will be updated with the same value.
To begin,
In
At this point, sub node 7 transmits to sub node 6 the SRF followed by its data (see the row labeled SUB 6). Sub node 6 forwards to sub node 5 the SRF along with the data from sub node 7 and its own data, and sub node 5 in turn forwards to sub node 4 the SRF along with the data from sub nodes 7 and 6. Sub node 4 has no data to add, so it simply forwards the data to sub node 3 (see the row labeled SUB 3), which forwards the data along with its own data to sub node 2 (see the row labeled SUB 2), which in turn forwards the data along with its own data to sub node 1. Sub node 1 has no data to add, so it forwards the data to sub node 0, which forwards the data along with its own data. As a result, the main node 102-1 receives the SRF followed by the data from sub nodes 7, 6, 3, 2, and 0 (see the row labeled MAIN).
As discussed above, each sub node 102-2 may remove data from downstream or upstream transmissions and/or may add data to downstream or upstream transmissions. Thus, for example, the main node 102-1 may transmit a separate sample of data to each of a number of sub nodes 102-2, and each such sub node 102-2 may remove its data sample and forward only data intended for downstream sub nodes 102-2. On the other hand, a sub node 102-2 may receive data from a downstream sub node 102-2 and forward the data along with additional data. One advantage of transmitting as little information as needed is to reduce the amount of power consumed collectively by the system 100.
The system 100 may also support broadcast transmissions (and multicast transmissions) from the main node 102-1 to the sub nodes 102-2, specifically through configuration of the downstream slot usage of the sub nodes 102-2. Each sub node 102-2 may process the broadcast transmission and pass it along to the next sub node 102-2, although a particular sub node 102-2 may “consume” the broadcast message, (i.e., not pass the broadcast transmission along to the next sub node 102-2).
The system 100 may also support upstream transmissions (e.g., from a particular sub node 102-2 to one or more other sub nodes 102-2). Such upstream transmissions can include unicast, multicast, and/or broadcast upstream transmissions. With upstream addressing, as discussed above with reference to downstream transmissions, a sub node 102-2 may determine whether or not to remove data from an upstream transmission and/or whether or not to pass an upstream transmission along to the next upstream sub node 102-2 based on configuration of the upstream slot usage of the sub nodes 102-2. Thus, for example, data may be passed by a particular sub node 102-2 to one or more other sub nodes 102-2 in addition to, or in lieu of, passing the data to the main node 102-1. Such sub-sub relationships may be configured, for example, via the main node 102-1.
Thus, in various embodiments, the sub nodes 102-2 may operate as active/intelligent repeater nodes, with the ability to selectively forward, drop, and add information. The sub nodes 102-2 may generally perform such functions without necessarily decoding/examining all of the data, since each sub node 102-2 knows the relevant time slot(s) within which it will receive/transmit data, and hence can remove data from or add data into a time slot. Notwithstanding that the sub nodes 102-2 may not need to decode/examine all data, the sub nodes 102-2 may typically re-clock the data that it transmits/forwards. This may improve the robustness of the system 100.
In some embodiments, the bus 106 may be configured for unidirectional communications in a ring topology. For example,
As described herein, data may be communicated between elements of the system 100 in any of a number of ways. In some embodiments, data may be sent as part of a set of synchronous data slots upstream (e.g., using the data slots 199) by a sub node 102-2 or downstream (e.g., using the data slots 198) by a sub node 102-2 or a main node 102-1. The volume of such data may be adjusted by changing the number of bits in a data slot, or including extra data slots. Data may also be communicated in the system 100 by inclusion in a synchronization control frame 180 or a synchronization response frame 197. Data communicated this way may include I2C control data from the host 110 (with a response from a peripheral device 108 associated with a sub node 102-2); accesses to registers of the sub nodes 102-2 (e.g., for discovery and configuration of slots and interfaces) that may include write access from the host 110/main node 102-1 to a sub node 102-2 and read access from a sub node 102-2 to the host 110/main node 102-1; and event signaling via interrupts from a peripheral device 108 to the host 110. In some embodiments, GPIO pins may be used to convey information from a sub node 102-2 to the main node 102-1 (e.g., by having the main node 102-1 poll the GPIO pins over I2C, or by having a node transceiver 120 of a sub node 102-2 generate an interrupt at an interrupt request pin). For example, in some such embodiments, a host 110 may send information to the main node 102-1 via I2C, and then the main node 102-1 may send that information to the sub node 102-2 via the GPIO pins. Any of the types of data discussed herein as transmitted over the bus 106 may be transmitted using any one or more of these communication pathways. Other types of data and data communication techniques within the system 100 may be disclosed herein.
Embodiments of the present disclosure may be implemented into a system using any suitable hardware and/or software to configure as desired.
Additionally, in various embodiments, the device 1300 may not include one or more of the components illustrated in
The device 1300 may include the node transceiver 120, in accordance with any of the embodiments disclosed herein, for managing communication along the bus 106 when the device 1300 is coupled to the bus 106. The device 1300 may include a processing device 1302 (e.g., one or more processing devices), which may be included in the node transceiver 120 or separate from the node transceiver 120. As used herein, the term “processing device” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1302 may include one or more DSPs, ASICs, central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors, or any other suitable processing devices. The device 1300 may include a memory 1304, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive.
In some embodiments, the memory 1304 may be employed to store a working copy and a permanent copy of programming instructions to cause the device 1300 to perform any suitable ones of the techniques disclosed herein. In some embodiments, machine-accessible media (including non-transitory computer-readable storage media), methods, systems, and devices for performing the above-described techniques are illustrative examples of embodiments disclosed herein for communication over a two-wire bus. For example, a computer-readable media (e.g., the memory 1304) may have stored thereon instructions that, when executed by one or more of the processing devices included in the processing device 1302, cause the device 1300 to perform any of the techniques disclosed herein.
In some embodiments, the device 1300 may include another communication chip 1312 (e.g., one or more other communication chips). For example, the communication chip 1312 may be configured for managing wireless communications for the transfer of data to and from the device 1300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 1312 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The one or more communication chips 1312 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The one or more communication chips 1312 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The one or more communication chips 1312 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1312 may operate in accordance with other wireless protocols in other embodiments. The device 1300 may include an antenna 1322 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 1312 may manage wired communications using a protocol other than the protocol for the bus 106 described herein. Wired communications may include electrical, optical, or any other suitable communication protocols. Examples of wired communication protocols that may be enabled by the communication chip 1312 include Ethernet, controller area network (CAN), I2C, media-oriented systems transport (MOST), or any other suitable wired communication protocol.
As noted above, the communication chip 1312 may include multiple communication chips. For instance, a first communication chip 1312 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1312 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1312 may be dedicated to wireless communications, and a second communication chip 1312 may be dedicated to wired communications.
The device 1300 may include battery/power circuitry 1314. The battery/power circuitry 1314 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the device 1300 to an energy source separate from the device 1300 (e.g., AC line power, voltage provided by a car battery, etc.). For example, the battery/power circuitry 1314 may include the upstream bus interface circuitry 132 and the downstream bus interface circuitry 131 discussed above with reference to
The device 1300 may include a display device 1306 (or corresponding interface circuitry, as discussed above). The display device 1306 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
The device 1300 may include an audio output device 1308 (or corresponding interface circuitry, as discussed above). The audio output device 1308 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
The device 1300 may include an audio input device 1324 (or corresponding interface circuitry, as discussed above). The audio input device 1324 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The device 1300 may include a GPS device 1318 (or corresponding interface circuitry, as discussed above). The GPS device 1318 may be in communication with a satellite-based system and may receive a location of the device 1300, as known in the art.
The device 1300 may include another output device 1310 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. Additionally, any suitable ones of the peripheral devices 108 discussed herein may be included in the other output device 1310.
The device 1300 may include another input device 1320 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1320 may include an accelerometer, a gyroscope, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, or a radio frequency identification (RFID) reader. Additionally, any suitable ones of the sensors or peripheral devices 108 discussed herein may be included in the other input device 1320.
Any suitable ones of the display, input, output, communication, or memory devices described above with reference to the device 1300 may serve as the peripheral device 108 in the system 100. Alternatively or additionally, suitable ones of the display, input, output, communication, or memory devices described above with reference to the device 1300 may be included in a host (e.g., the host 110) or a node (e.g., a main node 102-1 or a sub node 102-2).
The elements of a system 100 may be chosen and configured to provide audio and/or light control over the bus 106. In some embodiments, the system 100 may be configured to serve as a light control system in a vehicle or other environment, with lighting devices (e.g., strip-line light-emitting diodes (LEDs) or other LED arrangements) serving as peripheral devices 108 in communication with nodes 102 along the bus 106; data may be communicated over the bus 106 to control the color, intensity, duty cycle, and/or or other parameters of the lighting devices. In some embodiments, the system 100 may be configured to serve as an audio control system in a vehicle or other environment, with a microphone or other device including an accelerometer that may serve as a peripheral device 108 in communication with a node 102 along the bus 106; data from the accelerometer may be communicated over the bus 106 to control other peripheral devices 108 along the bus 106. For example, large spikes in the acceleration data or other predetermined acceleration data patterns may be used to trigger the generation of a sound effect, such as a cowbell or drum hit, by a processing device coupled to a node 102; that sound effect may be output by a speaker coupled to the processing device and/or by a speaker coupled to another node 102 along the bus 106. Some embodiments of the system 100 may combine any of the lighting control and/or audio control techniques disclosed herein.
Although various ones of the embodiments discussed above describe the system 100 in a vehicle setting, this is simply illustrative, and the system 100 may be implemented in any desired setting. For example, in some embodiments, a “suitcase” implementation of the system 100 may include a portable housing that includes the desired components of the system 100; such an implementation may be particularly suitable for portable applications, such as portable karaoke or entertainment systems.
As noted above, the calibration of microphones in an array (e.g., in embodiments of the system 100 in which one or more of the peripheral devices 108 include microphones) may be important for effective beamforming and other operations.
Microphones modules are generally tested during or following production. In some examples, the speaker 2120 emits a tone, chirp, or a frequency range sweep, which is received at the reference microphone 2130 and at each of the microphones 2141, 2142 of the microphone module 2140. It is then determined whether each of the microphones 2141, 2142 passes a specification. A microphone 2141, 2142 response to the received tone includes frequency, magnitude, and phase measurements. Once it is determined what the received frequency, magnitude, and phase measurements are at a selected microphone 2141, 2142, calibration coefficients can be determined for the respective microphones or the microphone module as a whole. In various examples, magnitude measurements are amplitude measurements. In some examples, some microphone modules do not pass the testing and are scrapped.
Microphone modules that pass the testing can be calibrated using test tone (or test chirp, test frequency sweep, etc.) response measurements, and a frequency and phase plot can be generated for each microphone 2141, 2142. The frequency and phase plots can be used for future microphone 2141, 2142 calibration. For example, calibration information can be generated for each microphone or for the microphone module as a whole and saved for future microphone calibration and/or compensation. In some examples, a transform is generated for each microphone 2141, 2142 which can be stored and used for later microphone compensation and/or calibration. In some examples, the calibration data is stored on a memory on the microphone module itself, such as in read only memory, programmable read only memory (PROM), erasable PROM (EPROM), and electrically erasable programmable read only memory (EEPROM). In some examples, the calibration data for the microphone is stored outside of the microphone. For example, the calibration data can be stored in a cloud storage and made accessible to a digital signal processor (DSP) for calibration before and during microphone use. In some examples, digital-bus networking features can be used to fetch specific microphone calibration data for each microphone.
In some examples, calibration of the microphones 2141, 2142 is accomplished using the reference microphone 2130. For instance, the reference microphone 2130 has a known response. Microphone calibration generates microphone calibration coefficients. The calibration coefficients can be stored on a microphone module, such that the calibration coefficients remain with the microphone regardless of where the microphone module is installed.
According to some implementations, calibration coefficients that are saved for each microphone include phase data, and in some examples, the calibration coefficients include phase tolerances. In some implementations, the calibration coefficients include complex numbers. In some examples, the calibration coefficients include an impulse response. In some examples, the calibration coefficients include a transfer function.
According to various implementations, the reference microphone 2130 is the reference point in space, and the reference microphone 2130 calibrates the sound received from the speaker 2120, accounting for speaker 2120 uncertainties. In various examples, the reference microphone 2130 is pre-calibrated. In some examples, the frequency response of the reference microphone 2130 is pre-calibrated. In some examples, the frequency response of the reference microphone 2130 can be used for the microphone module 2140. In some implementations, phase information is included in the calibration, and saved to the microphone module, such as to a microphone memory 2143. In some examples, a computational device fetches calibration coefficient data stored on the microphone module 2140, and applies the data to the microphones 2141, 2142 to calibrate the microphones 2141, 2142.
In various implementations, the memory on the microphone module 2143 is an EPROM. In some examples, the memory module 2143 is an EEPROM. In some examples, the memory module 2143 is a one time programmable (OTP) EPROM. In some implementations, the memory module 2143 includes additional microphone information such as vendor information, product information, version information, serial number, device capabilities, as well as any other microphone information. In some implementations, the memory is integrated on an MCU or digital networking chip on the microphone module.
According to various implementations, calibration data that is stored on the microphone module itself includes frequency data, magnitude data, and phase data. In various examples, magnitude data includes amplitude data. In some examples, the calibration data is communicated over a 2-wire interface. In some examples, the calibration data is communicated over an audio communication network like a digital networking bus.
According to various implementations, calibration coefficients can be stored for a single microphone and calibration coefficients can be stored for a microphone array. In some examples, a single calibration is stored for the microphone array. For instance, if microphones are off center and the off-centered position of the microphones is discovered during calibration, the same calibration data can be used to calibrate for the off-centeredness of each of the microphone. Properties of the microphone array and microphone module 2140 can be calibrated together. In some examples, each microphone has individual calibration data.
In some examples, gain and phase correction can look like a shifted microphone. It can be known how a signal should appear at arrival, and adjustments can be made if the signal is misplaced. In various examples, a shift can be either a microphone mismatch or a microphone placement mismatch, as both are indistinguishable and can be taken care of simultaneously with the same end result.
In some implementations, microphones in the module 2140 are calibrated for a selected direction, and after a per sensor calibration, the microphones of the array in the microphone module 2140 are calibrated such that the microphones 2141, 2142 have identical frequency and phase responses. In general, once a microphone is calibrated, the calibration coefficients stay with the microphone and thus can be used wherever the microphone is eventually installed.
In some examples, the memory 2143 includes some calibration data that is specific for individual microphones and some calibration data that applies to the microphone module 2140. For example, physical characteristics of the microphone module 2140 such as the spacing between the microphones of a microphone array can be stored in the memory 2143. In some examples, coefficients are provided for a microphone array that is mounted in a vehicle head unit, such that beamforming can be applied to a driver. For example, a head unit may know which angle and/or direction to focus on, but the head unit may not know what kind of microphone array is installed. If the microphone array information is available to the head unit, the head unit can calculate beamforming characteristics. Information about a microphone module that may be stored in the memory 2143 includes the number of microphones in the array, the gain range of the microphones, and physical characteristics of the microphones.
In some particular embodiments of the calibration method discussed above with reference to
In some implementations, microphone data for multiple microphone modules in a system are stored on one memory device in a sub-node. In some implementations, microphone data for all microphone modules in a system are stored on one memory device in a sub-node. For example, calibration data can be stored at a sub node without onboard processing, but with data storage. In some examples, the data is stored after a post installation scenario test and stored in a network bus node having an available and open memory device.
At step 2206, frequency domain signals S(f), M0(f), M1(f), . . . , Mn(f) are determined based on frames of N audio samples of each time domain signal s(t), m0(t), m1(t), . . . , mn(t). In some examples, a Fourier transform of the frames of the N audio samples of each time domain signal s(t), m0(t), m1(t), . . . , mn(t) is used to calculate the frequency domain signals S(f), M0(f), M1(f), . . . , Mn(f). At step 2208, calibration coefficients K1(t), . . . , Kn(t) are calculated for each microphone M1, . . . , Mn (e.g., the microphones 2141, 2142 in the microphone array of the microphone module 2140). In some examples, spectral domain signals M1(f), . . . , Mn(f) and S(f) or M0(f) are used to calculate the calibration coefficients. In some examples, the frequency domain signals calculated at step 2206 are used to determine the calibration coefficients at step 2208. In some examples, the reference microphone audio signal m0(t) is used to determine the calibration coefficients for the microphones 2141, 2142 of the microphone array in the microphone module 2140. At step 2210, the calibration coefficients K1(t), . . . , Kn(t) are stored in a non-volatile memory associated with the microphone array (e.g., the calibration coefficients K1(τ), . . . Kn(τ) are stored in the memory 2143 of the microphone module 2140).
H
x(f)=exp(i2πfd/c)√{square root over (M0(f)M0*(f)/Mx(f)M0*(f))}
In some examples, the calibration transfer functions are calculated using the sampled microphone audio signals m0(t), m1(t), . . . mn(t). At step 2224, an inverse Fourier transform of Hx(f) is used to calculate the calibration coefficients K1(τ), . . . Kn(τ) using the calibration transfer functions H1 . . . Hn. At step 2226, the calibration coefficients are stored in a non-volatile memory of the microphone module (e.g., the memory 2143 of the microphone module 2140).
In the embodiment of
H
L(f)=√{square root over (M0(f)S*(f))}/√{square root over (S*(f)S(f))}
At step 2244, the calibration transfer functions Hx(f), (x=1 . . . n), are calculated. In particular:
x(f)=exp(i2πfd/c)√{square root over (HL(f)S(f)HL*(f)S*(f))}/√{square root over (Mx(f)HL*(f)S*(f))}
In some examples, the reference microphone M0 is then not used for calculation of the calibration transfer functions Hx at step 2244. For instance, the reference microphone signal may be calculated as the product of HL(f) and S(f). The calculation of filter coefficients may then be performed as described above. In particular, at step 2246, the calibration coefficients Kx(t), (x=1 . . . n) are determined by means of an inverse Fourier transform of Hx(f), (x=1 . . . n). At step 2248, the calibration coefficients are stored in a microphone array memory. In yet another embodiment, the first step of the calibration in the method 2240 may be omitted, and a loudspeaker may be utilized for outputting the test signal s(t) (e.g., a point-source with flat frequency response), and HL(f) may be set to 1 for all frequencies.
where x=1 . . . n, y=1 . . . m
In some examples, the calibration coefficients K are applied as FIR filters. At step 2506, the original microphone signals mxy(t) are replaced with calibrated microphone signals nxy(t) in the microphone signal processing unit 2430. In some examples, the original microphone signals are replaced with calibrated microphone signals further down the data interface. At step 2508, calibrated microphone signals nxy(t) are forwarded to a microphone sink 2440 on the data interface 2450 in place of the original microphone signals mxy(t), x=1 . . . n, y=1 . . . m.
In some examples, the main node 2602 is a head unit. In some examples, digital audio signals from the second 2606 and third 2608 sub-nodes are sent to the first sub-node 2604. In various examples, any of the first 2604, second 2606, and third 2608 sub-nodes can include an audio-processing node. Similarly, the main node 2602 can include an audio-processing node. In various examples, an audio processing node can be a main node, a microphone node, an amplifier node, an emergency call node, or many other types of nodes. Although the setting of
In some embodiments, the calibration of a microphone module may not take place in a factory at production time but may take place when the microphones are installed in their intended setting. For example,
At step 2702, the bus system is discovered and configured. The bus system can be any type of bus system, such as those described herein. At step 2704, a test signal is played from a reference speaker. In some examples, the test signal is a chirp. The reference speaker can be connected to the bus system. In some examples, the reference speaker is not connected to the bus system but is otherwise connected to the microphone system. At step 2706, while the test signal is applied, microphone nodes are sampled. Additionally, if there is a measurement microphone and/or reference microphone, at step 2706, the measurement microphone and/or reference microphone is sampled. At step 2708, calibration coefficients for each microphone node are calculated, along with any other calibration data. At step 2710, calibration information for each microphone node is stored in each microphone node.
Example 1 provides a system for microphone module calibration, comprising: a loudspeaker configured to play a test signal; a microphone module configured to receive the test signal and to generate a plurality of microphone array signals; a reference microphone positioned between the loudspeaker and the microphone module, wherein the reference microphone is configured to receive the test signal and to generate a reference signal; and a calibration calculator configured to process the plurality of microphone array signals and the reference signal, generate a set of filter coefficients, and transmit the set of filter coefficients to the microphone module.
Example 2 provides a system according to any of the preceding and/or following examples, further comprising a memory associated with the microphone array configured to store the set of filter coefficients.
Example 3 provides a system according to any of the preceding and/or following examples, wherein the memory is positioned on a microphone array module with the microphone array.
Example 4 provides a system according to any of the preceding and/or following examples, wherein the memory is a cloud-based memory accessible by the microphone array.
Example 5 provides a system according to any of the preceding and/or following examples, wherein the memory is further configured to store microphone information, including at least one of vendor information, product information, version information, model information, capability information, serial number, make information, configuration information, routing information, and authentication information.
Example 6 provides a system according to any of the preceding and/or following examples, further comprising a plurality of memory modules, wherein each of the plurality of memory modules is associated with a respective microphone of the microphone array.
Example 7 provides a system according to any of the preceding and/or following examples, wherein the filter coefficients include phase calibration, frequency calibration, and magnitude calibration.
Example 8 provides a system according to any of the preceding and/or following examples, further comprising a two-wire interface, wherein transmission of the filter coefficients to the microphone array occurs over the two-wire interface.
Example 9 provides a system according to any of the preceding and/or following examples, wherein each of the plurality of microphone array signals is unique and each respective microphone of the microphone array is associated with a respective subset of the set of filter coefficients.
Example 10 provides a method for microphone array calibration, comprising: playing a test signal at a loudspeaker; sampling the test signal at a microphone array; generating a plurality of microphone array signals at the microphone array; sampling the test signal at a reference microphone; generating a reference signal at the reference microphone; generating a set of filter coefficients based on the plurality of microphone array signals and the reference signal; and transmitting the set of filter coefficients to the microphone array.
Example 11 provides a method according to any of the preceding and/or following examples, wherein sampling the test signal at the microphone array comprises sampling the test signal at each respective microphone of the microphone array.
Example 12 provides a method according to any of the preceding and/or following examples, wherein generating a set of filter coefficients comprises generating a respective subset of filter coefficients for each respective microphone.
Example 13 provides a method according to any of the preceding and/or following examples, further comprising storing the respective subset of filter coefficients on each respective microphone.
Example 14 provides a method according to any of the preceding and/or following examples, further comprising storing the set of filter coefficients on the microphone array.
Example 15 provides a method according to any of the preceding and/or following examples, wherein transmitting the set of filter coefficients comprises transmitting the set of filter coefficients over a two-wire bus.
Example 16 provides a method according to any of the preceding and/or following examples, further comprising pre-calibrating the loudspeaker using the reference microphone.
Example 17 provides a self-calibrating microphone system, comprising: a microphone module including: a microphone configured to receive an audio input signal and output a raw microphone output signal, wherein the microphone is pre-calibrated, and a non-volatile memory configured to store microphone calibration coefficients for the microphone; a processor configured to receive the raw microphone signal and the microphone calibration coefficients, and generate a calibrated microphone signal; and a microphone signal sink configured to receive the calibrated microphone signal from the processor and output the calibrated microphone signal.
Example 18 provides a system according to any of the preceding and/or following examples, wherein the microphone calibration coefficients are configured for at least one of phase calibration, frequency calibration, and magnitude calibration.
Example 19 provides a system according to any of the preceding and/or following examples, wherein the processor is further configured to use the microphone calibration coefficients for phase calibration of the raw microphone signal.
Example 20 provides a system according to any of the preceding and/or following examples, further comprising a two-wire bus wherein the processor and the microphone signal sink communicate over the two-wire bus.
Example 21 provides a system according to any of the preceding and/or following examples, wherein the processor is further configured to perform a convolution of the raw microphone signal and the microphone calibration coefficients to generate the calibrated microphone signal.
Example 22 include any of the phase and frequency response calibration systems and techniques disclosed herein.
Example 23 includes the subject matter according to any of the preceding and/or following examples, and further includes storage of the calibration coefficients local to the microphone array.
Example 24 includes the subject matter according to any of the preceding and/or following examples, and further includes the central application of calibration coefficients to uncalibrated microphone data from multiple microphone arrays.
Example 25 includes the subject matter according to any of the preceding and/or following examples, and further includes the replacement of original microphone signals with calibrated microphone signals.
Example 26 includes the subject matter according to any of the preceding and/or following examples, and further specifies that a microphone array is a peripheral device in any of the two-wire communication systems disclosed herein.
Example 27 provides a method according to any of the preceding and/or following examples, wherein the microphone array includes a single microphone.
Example 28 provides a system according to any of the preceding and/or following examples, wherein the microphone array includes a single microphone.
Example 29 provides a system according to any of the preceding and/or following examples, further comprising a two-wire bus, wherein the memory is positioned on a network bus sub-node.
Variations and Implementations
Having thus described several aspects and embodiments of the technology of this application, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those of ordinary skill in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described in the application. For example, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the embodiments described herein.
Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, kits, and/or methods described herein, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the scope of the present disclosure.
The foregoing outlines features of one or more embodiments of the subject matter disclosed herein. These embodiments are provided to enable a person having ordinary skill in the art (PHOSITA) to better understand various aspects of the present disclosure. Certain well-understood terms, as well as underlying technologies and/or standards may be referenced without being described in detail. It is anticipated that the PHOSITA will possess or have access to background knowledge or information in those technologies and standards sufficient to practice the teachings of the present disclosure.
The PHOSITA will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes, structures, or variations for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. The PHOSITA will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
The above-described embodiments may be implemented in any of numerous ways. One or more aspects and embodiments of the present application involving the performance of processes or methods may utilize program instructions executable by a device (e.g., a computer, a processor, or other device) to perform, or control performance of, the processes or methods.
In this respect, various inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other tangible computer storage medium) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement one or more of the various embodiments described above.
The computer readable medium or media may be transportable, such that the program or programs stored thereon may be loaded onto one or more different computers or other processors to implement various ones of the aspects described above. In some embodiments, computer readable media may be non-transitory media.
Note that the activities discussed above with reference to the FIGURES which are applicable to any integrated circuit that involves signal processing (for example, gesture signal processing, video signal processing, audio signal processing, analog-to-digital conversion, digital-to-analog conversion), particularly those that can execute specialized software programs or algorithms, some of which may be associated with processing digitized real-time data.
In some cases, the teachings of the present disclosure may be encoded into one or more tangible, non-transitory computer-readable mediums having stored thereon executable instructions that, when executed, instruct a programmable device (such as a processor or DSP) to perform the methods or functions disclosed herein. In cases where the teachings herein are embodied at least partly in a hardware device (such as an ASIC, IP block, or SoC), a non-transitory medium could include a hardware device hardware-programmed with logic to perform the methods or functions disclosed herein. The teachings could also be practiced in the form of Register Transfer Level (RTL) or other hardware description language such as VHDL or Verilog, which can be used to program a fabrication process to produce the hardware elements disclosed.
In example implementations, at least some portions of the processing activities outlined herein may also be implemented in software. In some embodiments, one or more of these features may be implemented in hardware provided external to the elements of the disclosed figures, or consolidated in any appropriate manner to achieve the intended functionality. The various components may include software (or reciprocating software) that can coordinate in order to achieve the operations as outlined herein. In still other embodiments, these elements may include any suitable algorithms, hardware, software, components, modules, interfaces, or objects that facilitate the operations thereof.
Any suitably-configured processor component can execute any type of instructions associated with the data to achieve the operations detailed herein. Any processor disclosed herein could transform an element or an article (for example, data) from one state or thing to another state or thing. In another example, some activities outlined herein may be implemented with fixed logic or programmable logic (for example, software and/or computer instructions executed by a processor) and the elements identified herein could be some type of a programmable processor, programmable digital logic (for example, an FPGA, an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM)), an ASIC that includes digital logic, software, code, electronic instructions, flash memory, optical disks, CD-ROMs, DVD ROMs, magnetic or optical cards, other types of machine-readable mediums suitable for storing electronic instructions, or any suitable combination thereof.
In operation, processors may store information in any suitable type of non-transitory storage medium (for example, random access memory (RAM), read only memory (ROM), FPGA, EPROM, electrically erasable programmable ROM (EEPROM), etc.), software, hardware, or in any other suitable component, device, element, or object where appropriate and based on particular needs. Further, the information being tracked, sent, received, or stored in a processor could be provided in any database, register, table, cache, queue, control list, or storage structure, based on particular needs and implementations, all of which could be referenced in any suitable timeframe.
Any of the memory items discussed herein should be construed as being encompassed within the broad term ‘memory.’ Similarly, any of the potential processing elements, modules, and machines described herein should be construed as being encompassed within the broad term ‘microprocessor’ or ‘processor.’ Furthermore, in various embodiments, the processors, memories, network cards, buses, storage devices, related peripherals, and other hardware elements described herein may be realized by a processor, memory, and other related devices configured by software or firmware to emulate or virtualize the functions of those hardware elements.
Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer, as non-limiting examples. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a personal digital assistant (PDA), a smart phone, a mobile phone, an iPad, or any other suitable portable or fixed electronic device.
Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that may be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that may be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible formats.
Such computers may be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, and intelligent network (IN) or the Internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks or wired networks.
Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that performs particular tasks or implement particular abstract data types. Typically, the functionality of the program modules may be combined or distributed as desired in various embodiments.
The terms “program” or “software” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that may be employed to program a computer or other processor to implement various aspects as described above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present application need not reside on a single computer or processor, but may be distributed in a modular fashion among a number of different computers or processors to implement various aspects of the present application.
Also, data structures may be stored in computer-readable media in any suitable form. For simplicity of illustration, data structures may be shown to have fields that are related through location in the data structure. Such relationships may likewise be achieved by assigning storage for the fields with locations in a computer-readable medium that convey relationship between the fields. However, any suitable mechanism may be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationship between data elements.
When implemented in software, the software code may be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.
Computer program logic implementing all or part of the functionality described herein is embodied in various forms, including, but in no way limited to, a source code form, a computer executable form, a hardware description form, and various intermediate forms (for example, mask works, or forms generated by an assembler, compiler, linker, or locator). In an example, source code includes a series of computer program instructions implemented in various programming languages, such as an object code, an assembly language, or a high-level language such as OpenCL, RTL, Verilog, VHDL, Fortran, C, C++, JAVA, or HTML for use with various operating systems or operating environments. The source code may define and use various data structures and communication messages. The source code may be in a computer executable form (e.g., via an interpreter), or the source code may be converted (e.g., via a translator, assembler, or compiler) into a computer executable form.
In some embodiments, any number of electrical circuits of the FIGURES may be implemented on a board of an associated electronic device. The board can be a general circuit board that can hold various components of the internal electronic system of the electronic device and, further, provide connectors for other peripherals. More specifically, the board can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processors (inclusive of digital signal processors, microprocessors, supporting chipsets, etc.), memory elements, etc. can be suitably coupled to the board based on particular configuration needs, processing demands, computer designs, etc.
Other components such as external storage, additional sensors, controllers for audio/video display, and peripheral devices may be attached to the board as plug-in cards, via cables, or integrated into the board itself. In another example embodiment, the electrical circuits of the FIGURES may be implemented as standalone modules (e.g., a device with associated components and circuitry configured to perform a specific application or function) or implemented as plug-in modules into application-specific hardware of electronic devices.
Note that with the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electrical components. However, this has been done for purposes of clarity and example only. It should be appreciated that the system can be consolidated in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, and elements of the FIGURES may be combined in various possible configurations, all of which are clearly within the broad scope of this disclosure.
In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows by only referencing a limited number of electrical elements. It should be appreciated that the electrical circuits of the FIGURES and its teachings are readily scalable and can accommodate a large number of components, as well as more complicated/sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of the electrical circuits as potentially applied to a myriad of other architectures.
Also, as described, some aspects may be embodied as one or more methods. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
Interpretation of Terms
All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms. Unless the context clearly requires otherwise, throughout the description and the claims:
“comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to”.
“connected,” “coupled,” or any variant thereof, means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, or a combination thereof.
“herein,” “above,” “below,” and words of similar import, when used to describe this specification shall refer to this specification as a whole and not to any particular portions of this specification.
“or,” in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
the singular forms “a”, “an” and “the” also include the meaning of any appropriate plural forms.
Words that indicate directions such as “vertical”, “transverse”, “horizontal”, “upward”, “downward”, “forward”, “backward”, “inward”, “outward”, “vertical”, “transverse”, “left”, “right”, “front”, “back”, “top”, “bottom”, “below”, “above”, “under”, and the like, used in this description and any accompanying claims (where present) depend on the specific orientation of the apparatus described and illustrated. The subject matter described herein may assume various alternative orientations. Accordingly, these directional terms are not strictly defined and should not be interpreted narrowly.
The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”
The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and/or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined.
Elements other than those specifically identified by the “and/or” clause may optionally be present, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and/or B”, when used in conjunction with open-ended language such as “comprising” may refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.
As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified.
Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and/or B”) may refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.
As used herein, the term “between” is to be inclusive unless indicated otherwise. For example, “between A and B” includes A and B unless indicated otherwise.
Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” “containing,” “involving,” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively.
Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the appended claims.
In order to assist the United States Patent and Trademark Office (USPTO) and, additionally, any readers of any patent issued on this application in interpreting the claims appended hereto, Applicant wishes to note that the Applicant: (a) does not intend any of the appended claims to invoke 35 U.S.C. § 112(f) as it exists on the date of the filing hereof unless the words “means for” or “steps for” are specifically used in the particular claims; and (b) does not intend, by any statement in the disclosure, to limit this disclosure in any way that is not otherwise reflected in the appended claims.
The present invention should therefore not be considered limited to the particular embodiments described above. Various modifications, equivalent processes, as well as numerous structures to which the present invention may be applicable, will be readily apparent to those skilled in the art to which the present invention is directed upon review of the present disclosure.
This application claims benefit of and priority to U.S. Provisional Application Ser. No. 63/112,967, titled “Systems and Techniques for Microphone Array Calibration”, which is hereby incorporated by reference in its entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2021/081514 | 11/12/2021 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 63112967 | Nov 2020 | US |
