The present disclosure is generally related to systems, devices and methods of charge-based storage elements.
Advances in technology have resulted in smaller and/or more powerful computing devices, with ever growing power, performance, area and cost (PPAC) demands. For example, a variety of portable personal computing devices, including wireless telephones, such as mobile and smart phones, tablets and laptop computers are small, lightweight, and easily carried by users. These devices can communicate voice and data packets over wireless networks. Further, many such devices incorporate additional functionality, such as a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such devices can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these devices can include significant computing and networking capabilities. Accordingly, there is an ongoing need in the art for memory optimization, and improvement in power, performance, area and cost for various memory operations.
The present technique(s) will be described further, by way of example, with reference to embodiments thereof as illustrated in the accompanying drawings. It should be understood, however, that the accompanying drawings illustrate only the various implementations described herein and are not meant to limit the scope of various techniques, methods, systems, circuits or apparatuses described herein.
Reference is made in the following detailed description to accompanying drawings, which form a part hereof, wherein like numerals may designate like parts throughout that are corresponding and/or analogous. It will be appreciated that the figures have not necessarily been drawn to scale, such as for simplicity and/or clarity of illustration and many of the units are normalized to showcase relative trends. For example, dimensions of some aspects may be exaggerated relative to others. Further, it is to be understood that other embodiments may be utilized. Furthermore, structural and/or other changes may be made without departing from claimed subject matter. References throughout this specification to “claimed subject matter” refer to subject matter intended to be covered by one or more claims, or any portion thereof, and are not necessarily intended to refer to a complete claim set, to a particular combination of claim sets (e.g., method claims, apparatus claims, etc.), or to a particular claim. It should also be noted that directions and/or references, for example, such as up, down, top, bottom, and so on, may be used to facilitate discussion of drawings and are not intended to restrict application of claimed subject matter. While certain diagrams as illustrated herein are shown in two-dimensions, aspects of the diagrams as provided herein are to be understood to be three-dimensional having X, Y and Z axes. Therefore, the following detailed description is not to be taken to limit claimed subject matter and/or equivalents.
Particular implementations of the present disclosure are described below with reference to the drawings. In the description, common features are designated by common reference numbers throughout the drawings.
According to one implementation of the present disclosure, a circuit structure is configured to store charge in a charge-based storage element, where the charge-based storage element is disposed at least partially in a shallow-trench-isolation (STI) region of the circuit.
According to one implementation of the present disclosure, a method includes: providing a circuit structure disposed on a substrate and a shallow-trench-isolation (STI) region of a circuit; forming an opening of the substrate and the STI region by removing a portion of the substrate and STI region; placing a first liner material in the opening and on remaining portions of the substrate and the STI region; and depositing a first metal layer in the opening on the first liner material, where the substrate is coupled to ground, and where an input voltage is coupled to the circuit structure.
According to one implementation of the present disclosure, a method includes: providing a memory cell structure disposed on a substrate and a shallow-trench-isolation (STI) region; forming one or more charge-based storage elements in the substrate and the STI region to store data of the memory cell structure; and manufacturing, or causing to be manufactured, a memory device having the memory cell structure with the one or more charge-based storage element formed in the substrate and the STI region or fin-cut region.
Traditionally, static-random access memory (SRAM)-based memory has been preferred due its speed and reliability in memory devices. Another alternative for memory design includes the usage of eDRAM (i.e., embedded of dynamic random-access-memory). However, at room temperature operation, eDRAM may not be attractive. As a characteristic, eDRAM leaks current rapidly, and thus its retention time (i.e., the capacity to hold memory data) would be a short timeframe in microseconds. Hence, challenges to the implementation of eDRAM include the frequent requirement for refresh operations, and that such operations for refresh or dynamic refresh may be energy intensive. In comparison to SRAM, eDRAM is smaller and thus, would utilize less transistors (e.g., three transistors or less for eDRAM, while SRAM would require six transistors). Further, as another feature, in eDRAM, there are separate read and write transistors, allowing for read and write operations to be performed separately. In certain implementations, the use of eDRAM (i.e., embedded of dynamic random-access-memory) (e.g., a gain cell DRAM) for memory in computing devices can be attractive because it utilizes lower energy, lower static power, and sometimes lower dynamic power as well.
As may be appreciated, for CMOS-compatible technology, trenches that contain conductor material including barrier/liner (for the protection of surrounding dielectric material) have been utilized for power and ground wires (in order to reduce IR drop). In addition, for advance node technologies, shallow-trench-isolation (STI) regions between transistors may be utilized to create a trench for buried power rails. Moreover, recently, gain-cell (GC) eDRAMs have increased in popularity due to their low area requirements in comparison to SRAMs, but are also CMOS-technology compatible (e.g., such memory can reside on a same die it would not require deep trench capacitors or any other special capacitors for off-chip DRAM memories).
Advantageously, taking the above considerations into account, inventive aspects of the present invention allow for enhanced memory reliability while implementing buried rail technology. For example, such inventive aspects of the present invention include circuits, systems, and methods to provide for an increase of stored charge (i.e., SN) for memory, latches, and flip-flops by utilizing buried rail technology. Specifically, the increase in stored charge is by including locations where stored charge may be added to boost (i.e., enhance) stored charge.
In certain implementations, shallow-trench-isolation (STI) regions for depositing metal-dielectric-metal can be utilized to enhance stored charge for memory (e.g., eDRAM) that suffers from low retention time due to utilizing on-chip capacitors to store charge. Advantageously, such inventive aspects would enhance retention times. In certain implementations, fin-cut regions (typically used for cutting the diffusion/active region) may be utilized for depositing metal-dielectric-metal to form capacitors (e.g., eDRAM) that suffer with low retention time due to utilizing on-chip capacitors to store charge. Advantageously, such inventive aspects, as well, would enhance retention times. In certain implementations, STI regions and the gate-cut regions in combination may be utilized for further enhancement of capacitance. In addition, the STI and fin-cut regions may be implemented to deposit charge-based storage elements (e.g., capacitors) through CMOS-compatible methods in order to enhance soft-error rate (SER) robustness for both SRAM and eDRAM.
Advantageously, schemes and techniques described herein provide the benefit of a “2×” increase in storage node capacitance such that a “2×” improvement or more in retention time may be realized for an eDRAM. Moreover, a realized “2×” increase in storage node charge (e.g., in SRAM) would also improve SER by greater than “2×” (e.g. as the SER would be exponentially dependent on stored charge Q as described herein).
With reference to
Referring to
With reference to
With reference to
Correspondingly, such charge would largely leak through the write transistor (WTr) 164, even when the bit-cell is not in use, leaving the write transistor (WTr) 164 to leak at subthreshold, and the storage node SN 152 would, thus, remain reliable only for a period of time called “retention time”.
As illustrated, the write transistor (WTr) 164 can be configured to act as a pass gate to write a value on a write bitline (WBL) to the storage node (SN) 152 (e.g., the gate node of the read transistor (RTr) 162) when the write word line (WWL) is activated. As may be appreciated, the greater a charge on the storage node (SN) 152, the higher the “retention time” (i.e., the more time available until a stored charge would be destroyed). Hence, advantageously, inventive aspects as described herein provide for the capability to increase the charge capacity on various storage node locations.
Also, in certain implementations, in
Referring to
As illustrated, in
For example, in certain implementations, the charge-base storage element 210 comprises one or more capacitors, where at least one capacitor of the one or more capacitors can be formed (e.g., disposed, located) in at least one of a buried rail trench 210 (e.g., typically in the perpendicular direction to the fin-cut or a gate-cut region (corresponding at least partially to the shallow-trench-isolation (STI) region). In certain examples, as illustrated, the at least one capacitor is formed on a storage node (SN) 210, 212, 214 of the circuit, where the storage node is positioned in one or both of the buried rail trench 210 and the fin-cut region of the circuit. As may be appreciated, the fin-cut region includes a region between active fin shapes (where “active” refers to where a transistor would be made). In certain other examples, the at least one capacitor is formed in the STI region and a silicon substrate region of the circuit.
In certain cases, for example, the at least one capacitor is formed perpendicular to a gate layer (i.e., transistor-gate layer) configured to form respective gates of first transistor and second transistors. In other cases, for example, wherein the at least one capacitor is formed parallel to a gate layer (i.e., transistor-gate layer) configured to form respective gates of first transistor and second transistors. In certain implementations, the circuit structure configured for charging in a charge-based storage element may be a memory bit-cell such as: an eDRAM gain-cell (e.g., 2T or 3T) or an SRAM.
Referring to
Referring to
As may be appreciated, advantageously, the circuit layout 400 may be implemented to include a trench 404 of metal material and would be protected from the surrounding silicon bulk layer 401 using the oxide/barrier liner material 403 (e.g., as described with reference to the process in
Advantageously, in an example implementation, an approximate estimation of capacitance (e.g., parallel plate capacitor) (e.g., in addition to a gate capacitance of a read transistor (RTr) of the circuit structure 400 may be computed with the following equation below where: Tmetal_si corresponds to a thickness of metal conductor 404 overlap with the silicon substrate layer 401; Wmetal corresponds to a width of the metal conductor 404; Lmetal corresponds to a length of the metal conductor 404; and to tliner corresponds to a thickness of the dielectric barrier-liner 403.
Referring to
As may be appreciated, advantageously, the circuit layout 500 may be implemented to include a trench of two metal conductors and two dielectric layers to allow for increased capacitance in the storage node (SN) as permitted by manufacturing process (e.g., with reference to
Advantageously, first and second conductors 506, 504 would be protected from the surrounding silicon bulk layer 501 using the first and second oxide/barrier liner materials 505, 503 (as described with reference to the process in
Referring to
As may be appreciated, advantageously, the circuit layout 600 (i.e., circuit structure) may be implemented to include a trench of two metal conductors and two dielectric layers to allow for increased capacitance in the storage node (SN) as permitted by manufacturing process. However, in contrast to the circuit layout
Advantageously, first and second conductors (i.e., outer and inner conductors) 606, 604 would be protected from the surrounding silicon bulk layer 601 using the first and second oxide/barrier liner materials 603, 605 (as described with reference to the process in
Referring to
At block 710, the method 700 includes: providing a circuit structure (e.g., a memory cell structure) disposed on a substrate and a shallow-trench-isolation (STI) region of a circuit. For example, with reference to implementations in
At block 720, the method 700 includes: forming an opening (e.g., a trench) of the substrate and the STI region by removing (etching, cutting) a portion of the substrate and STI region. For example, with reference to implementations in
At block 730, the method 700 includes: placing (e.g., inserting) a first liner material (e.g., oxide/barrier liner material, a first dielectric layer) in the opening and on remaining portions of the substrate and the STI region. For example, with reference to implementations in
At block 740, the method 700 includes: depositing a first metal layer in the opening on the first liner material, wherein the substrate is coupled to ground, and where an input voltage is coupled to (transistors of) the circuit structure. For example, with reference to implementations in
In some implementations, forming of the opening (e.g., trench opening) includes removing a portion of a field effect transistor (FET) (e.g., fin-FET) (e.g., 222a, 222b, 322a, 322b). For example, with reference to implementations in
In certain implementations, with reference to
In some implementations, with reference to
Referring to
At block 810, the method 800 includes: providing a circuit structure (e.g., a memory cell structure) disposed on a substrate and a shallow-trench-isolation (STI) region of a circuit. For example, with reference to implementations in
At block 820, the method 800 includes: forming one or more capacitors in the substrate and the STI region to store data of the memory cell structure. For example, with reference to implementations in
At block 830, the method 700 includes: manufacturing, or causing to be manufactured, a memory device having the memory cell structure with the one or more capacitors formed or buried or disposed in the substrate and the STI region or fin-cut region. For example, with reference to implementations in
As may be appreciated, such steps as described herein may performed by various lithography and circuit generation methods and be performed by a manufacturing, lithography tool 924 as described with reference to
In certain cases, the electronic tool 924 may provide generated computer-aided physical layout designs for memory architecture. The procedures 700, 800 (and other procedures discussed throughout the disclosure) may be stored as program code as instructions 917 in the computer readable medium of the storage device 916 (or alternatively, in memory 914) that may be executed by the computer 910, or networked computers 920, 930, other networked electronic devices (not shown) or a combination thereof. In certain implementations, each of the computers 910, 920, 930 may be any type of computer, computer system, or other programmable electronic device. Further, each of the computers 910, 920, 930 may be implemented using one or more networked computers, e.g., in a cluster or other distributed computing system.
In certain implementations, the system 900 may be used with semiconductor integrated circuit (IC) designs that contain all standard cells, all blocks or a mixture of standard cells and blocks. In a particular example implementation, the system 900 may include in its database structures: a collection of cell libraries, one or more technology files, a plurality of cell library format files, a set of top design format files, one or more Open Artwork System Interchange Standard (OASIS/OASIS.MASK) files, and/or at least one EDIF file. The database of the system 900 may be stored in one or more of memory 914 or storage devices 916 of computer 910 or in networked computers 920, 930.
In certain implementations, the system 900 may perform the following functions automatically or with variable user input: determination of read current requirements/thresholds (i.e., Iread), determination of leakage current requirements/thresholds (i.e., Ileak), identification of logic designs (i.e., periphery circuit designs (i.e., logic threshold voltages, threshold voltage implant layers)), determination of a desired threshold voltage-combination, determination of minimum voltage assist requirements (i.e., Vmin assist), identification of bit-cell types, determination of memory specific optimization modes (memory optimization mode), floor-planning, including generation of cell regions sufficient to place all standard cells; standard cell placement; power and ground net routing; global routing; detail routing and pad routing. In some instances, such functions may be performed substantially via user input control. Additionally, such functions can be used in conjunction with the manual capabilities of the system 900 to produce the target results that are required by a designer. In certain implementations, the system 900 may also provide for the capability to manually perform functions such as: cell region creation, block placement, pad and cell placement (before and after automatic placement), net routing before and after automatic routing and layout editing. Moreover, verification functions included in the system 900 may be used to determine the integrity of a design after, for example, manual editing, design rule checking (DRC) and layout versus schematic comparison (LVS).
In one implementation, the computer 900 includes a central processing unit (CPU) or graphical processing unit (GPU) 912 having at least one hardware-based processor coupled to a memory 914. The memory 914 may represent random access memory (RAM) devices of main storage of the computer 910, supplemental levels of memory (e.g., cache memories, non-volatile or backup memories (e.g., programmable or flash memories), read-only memories, or combinations thereof. In addition to the memory 914, the computer system 900 may include other memory located elsewhere in the computer 910, such as cache memory in the CPU 912, as well as any storage capacity used as a virtual memory (e.g., as stored on a storage device 916 or on another computer coupled to the computer 910).
The computer 910 may further be configured to communicate information externally. To interface with a user or operator (e.g., a circuit design engineer), the computer 910 may include a user interface (I/F) 918 incorporating one or more user input devices (e.g., a keyboard, a mouse, a touchpad, and/or a microphone, among others) and a display (e.g., a monitor, a liquid crystal display (LCD) panel, light emitting diode (LED), display panel, and/or a speaker, among others). In other examples, user input may be received via another computer or terminal. Furthermore, the computer 910 may include a network interface (I/F) 915 which may be coupled to one or more networks 940 (e.g., a wireless network) to enable communication of information with other computers and electronic devices. The computer 910 may include analog and/or digital interfaces between the CPU 912 and each of the components 914, 915, 916, and 918. Further, other non-limiting hardware environments may be used within the context of example implementations.
The computer 910 may operate under the control of an operating system 926 and may execute or otherwise rely upon various computer software applications, components, programs, objects, modules, data structures, etc. (such as the programs associated with the procedures e.g., 700, 800, and related software). The operating system 928 may be stored in the memory 914. Operating systems include, but are not limited to, UNIX® (a registered trademark of The Open Group), Linux® (a registered trademark of Linus Torvalds), Windows® (a registered trademark of Microsoft Corporation, Redmond, WA, United States), AIX® (a registered trademark of International Business Machines (IBM) Corp., Armonk, NY, United States) i5/OS® (a registered trademark of IBM Corp.), and others as will occur to those of skill in the art. The operating system 926 in the example of
In example implementations, circuit macro diagrams have been provided in certain figures described herein, whose redundant description has not been duplicated in the related description of analogous circuit macro diagrams. It is expressly incorporated that the same cell layout diagrams with identical symbols and/or reference numerals are included in each of embodiments based on its corresponding figure(s).
Although one or more of
Aspects of the present disclosure may be incorporated in a system, a method, and/or a computer program product. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to carry out aspects of the present disclosure. The computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer-readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire. For example, the memory 1514, the storage device 1516, or both, may include tangible, non-transitory computer-readable media or storage devices.
Computer-readable program instructions described herein can be downloaded to respective computing/processing devices from a computer-readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing/processing device.
Computer-readable program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and procedural programming languages, such as the “C” programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some implementations, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.
Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus. The machine is an example of means for implementing the functions/acts specified in the flowchart and/or block diagrams. The computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the functions/acts specified in the flowchart and/or block diagrams.
The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to perform a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagrams.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various implementations of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in a block in a diagram may occur out of the order noted in the figures. For example, two blocks shown in succession may be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowcharts, and combinations of blocks in the block diagrams and/or flowcharts, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
In the following description, numerous specific details are set forth to provide a thorough understanding of the disclosed concepts, which may be practiced without some or all of these particulars. In other instances, details of known devices and/or processes have been omitted to avoid unnecessarily obscuring the disclosure. While some concepts will be described in conjunction with specific examples, it will be understood that these examples are not intended to be limiting.
Unless otherwise indicated, the terms “first”, “second”, etc. are used herein merely as labels, and are not intended to impose ordinal, positional, or hierarchical requirements on the items to which these terms refer. Moreover, reference to, e.g., a “second” item does not require or preclude the existence of, e.g., a “first” or lower-numbered item, and/or, e.g., a “third” or higher-numbered item.
Reference herein to “one example” means that one or more feature, structure, or characteristic described in connection with the example is included in at least one implementation. The phrase “one example” in various places in the specification may or may not be referring to the same example.
Illustrative, non-exhaustive examples, which may or may not be claimed, of the subject matter according to the present disclosure are provided below. Different examples of the device(s) and method(s) disclosed herein include a variety of components, features, and functionalities. It should be understood that the various examples of the device(s) and method(s) disclosed herein may include any of the components, features, and functionalities of any of the other examples of the device(s) and method(s) disclosed herein in any combination, and all of such possibilities are intended to be within the scope of the present disclosure. Many modifications of examples set forth herein will come to mind to one skilled in the art to which the present disclosure pertains having the benefit of the teachings presented in the foregoing descriptions and the associated drawings.
Therefore, it is to be understood that the present disclosure is not to be limited to the specific examples illustrated and that modifications and other examples are intended to be included within the scope of the appended claims. Moreover, although the foregoing description and the associated drawings describe examples of the present disclosure in the context of certain illustrative combinations of elements and/or functions, it should be appreciated that different combinations of elements and/or functions may be provided by alternative implementations without departing from the scope of the appended claims. Accordingly, parenthetical reference numerals in the appended claims are presented for illustrative purposes only and are not intended to limit the scope of the claimed subject matter to the specific examples provided in the present disclosure.