Patent Application
20170012866
This disclosure relates generally to telecommunications networks and more specifically, but not exclusively, to data forwarding in telecommunications networks.
Modern communication and data networks comprise network nodes, such as routers, switches, bridges, and other devices that transport data through the network. Over the years, the telecommunication industry has made significant improvements to the network nodes to support an increasing number of protocols and specifications standardized by the Internet Engineering Task Force (IETF). Creating and coupling the complex network nodes to form networks that support and implement the various IETF standards (e.g. virtual private networks requirements) has inadvertently cause modern networks to become labyrinth-like and difficult to manage. As a result, vendors and third-party operators continually struggle to customize, optimize, and improve the performance of the interwoven web of network nodes.
Software defined networking (SDN) is an emerging network technology that addresses customization and optimization concerns within convoluted networks. SDN simplifies modern networks by decoupling the data-forwarding capability (e.g. a data plane) from routing, resource, and other management functionality (e.g. a control plane) previously performed in the network nodes. Network nodes that support SDN (e.g., that are SDN compliant) may be configured to implement the data plane functions, while the control plane functions may be provided by a SDN controller. Open application programming interface (API) services, such as the OpenFlow protocol, may manage the interactions between the data plane and control plane and allow for the implementation of non-vendor specific combinations of networking nodes and SDN controllers within a network. As a result, SDN in conjunction with an Open API service may provide numerous benefits to modern networks that include increased network virtualization, flexible control and utilization of the network, and customization of networks for scenarios with specific requirements.
Modern networks, such as data center networks, enterprise networks, and carrier networks, may gradually adopt SDN because of the numerous potential benefits. The deployment of SDN into large-scale distributed networks may be implemented incrementally. In other words, a network administrator for a large-scale network, such as an autonomous system (AS), may partition the entire network into multiple smaller sub-networks. Some of the sub-networks may be SDN compatible, in which case a sub-network may be referred to as a SDN domain, while other sub-networks may not be SDN compatible. Unfortunately, network services, such as application layer traffic optimization (ALTO), may encounter integration problems when implementing SDN within a large-scale network.
Specifically, optimization of data flow paths may be one of the problems. Suppose, for example, a network consisting of following flow programmable nodes (such as switches or routers), when a flow needs to traverse this network, all nodes in the path needs to be programmer with a flow entry to forward the flow to the next hop. In a small network, it might be possible to pre-program all the flows in all the nodes but in a large network where the total number of flows in the network is greater than the total number of flow per node, pre-programming is not a viable solution.
Accordingly, there is a need for systems, apparatus, and methods that improve upon conventional approaches including the improved methods, system and apparatus provided hereby.
The following presents a simplified summary relating to one or more aspects and/or examples associated with the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview relating to all contemplated aspects and/or examples, nor should the following summary be regarded to identify key or critical elements relating to all contemplated aspects and/or examples or to delineate the scope associated with any particular aspect and/or example. Accordingly, the following summary has the sole purpose to present certain concepts relating to one or more aspects and/or examples relating to the apparatus and methods disclosed herein in a simplified form to precede the detailed description presented below.
In one aspect, a method implemented by a software defined network (SDN) controller, the method comprising: receiving, at a first network node, a request for a data flow path through a telecommunications network, the request including information identifying a source node and a destination node; determining, by the first network node, if a flow entry exists for the data flow path; forwarding a data flow from the first network node to a second network node when the flow entry exists in the first network node; sending, by the first network node, a flow page miss to a controller requesting the data flow path for the data flow when the flow entry does not exists in the first network node; determining, by the controller, the data flow path; and sending, by the controller, the determined data flow path to the first network node and the second network node.
In another aspect, a network node includes at least one transceiver configured to: receive a request for a data flow path from a source through the software defined network to a destination, the request including information identifying the source and the destination; determine if information about the data flow path is stored in the first network node; forward data from the first network node to a second network node when the information about the data flow path is stored in the first network node; send a path request to a controller requesting the data flow path when the information about the data flow path is not stored in the first network node; and receive from the controller the information about the data flow path.
In still another aspect, a controller includes at least one transceiver configured to: receive, from one of a plurality network nodes, a request for a data flow path from a source through the software defined network to a destination, the request including information identifying the source and the destination; determine the data flow path; and send information about the data flow path to the plurality of network nodes.
Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description.
A more complete appreciation of aspects of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings which are presented solely for illustration and not limitation of the disclosure, and in which:
In accordance with common practice, the features depicted by the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily expanded or reduced for clarity. In accordance with common practice, some of the drawings are simplified for clarity. Thus, the drawings may not depict all components of a particular apparatus or method. Further, like reference numerals denote like features throughout the specification and figures.
The exemplary methods, apparatus, and systems disclosed herein advantageously address the industry needs, as well as other previously unidentified needs, and mitigate shortcomings of the conventional methods, apparatus, and systems.
Each of the plurality of nodes 110-170 may be configured to implement data plane functions, such as the data-forwarding capability, while the controller 105 may be configured to implement the control plane functions, such as routing, resource, and other management functionality. For example, when a data flow 102 (F1) from a source node (e.g. a customer node or device, not shown) intended for a destination node (e.g. another customer node or device, not shown) is received at the first node 110, the first node 110 may access a local lookup table or flow information database to determine if a match exists for the destination node. If a match exists (e.g. the flow information database has a pre-determined route through the network 100), the first node 110 may know the next node in the route through the network 100 and will forward the data flow 102 to the next node in the route, such as the second node 120. If a match does not exists, the first node 110 may query the controller 105 (flow paging). The flow paging may be done by forwarding the initial packet of data flow 102 to the controller 105 or the first node 110 may sent a route request with the necessary source node and destination node information to the controller 105. The communication between a node, such as the first node 110, and the controller 105 may use packet_out and packet_in messages. For example, when the first node 110 sends a message to the controller 105, the message is sent as a packet_in message. When the controller 105 receives the route request or initial packet of data flow 102, the controller 105 will determine a route through the network 100 for the data flow 102. For example, the controller 105 may determine the optimal path through the network 100 for data flow 102 is from the first node 110 to the second node 120 then to the third node 130 followed by the fourth node 140 and onward to the destination node.
In such an example, the controller 105 may send the route information for data flow 102 to the nodes along the intended route (i.e. the first node 110, the second node 120, the third node 130, and the fourth node 140). Each node in the route will receive information for its respective, local lookup table or flow information database that enables the node to determine which node is next in the intended route for a given data flow, data flow 102 in this case. The controller 105 may send the route information to each of the nodes 110-140 in reverse order (i.e. to fourth node 140 then to the third node 130 followed by the second node 120 and finally the first node 110). By sending the route information to the last node in the path first (reverse order), the controller 105 may avoid a situation where the first node 110 gets the information to forward the data flow 102 to the second node 120, sends the data flow 102 packets to the second node 120 before the second node 120 receives the route information for data flow 102 from the controller 105, which may cause the second node 120 to initiate another flow paging to the controller 105 unnecessarily and increase network congestion. In addition, when the controller 105 programs the flow lookup tables for each of the nodes in the path instead of just the requesting node, the controller 105 reduces the amount of route requests (flow pages) to reduce network congestion by avoiding multiple requests and route information exchanges for the same flow path.
Flow paging may be initiated in other circumstances beside a new data flow arriving at a node without a current flow entry for the new data flow. For example, flow paging may be triggered by flow miss on a node, it may be future flow prediction based on certain criteria, for example if a client or customer visits a portal like yahoo.com, the controller 105 may make a prediction of what other flows may be triggered and program those flow entries for future data flows along with the flow entry for the initial data flow, and it may be based on analytical data (heuristics or quality of service issues, for example) the controller 105 may have collected about traffic congestion or patterns etc. that will allow the controller 105 to program flow entries for future data flows to avoid network congestions or anticipated traffic patterns.
In such an example, the controller 105 sends the route information for data flow 102 to the fourth node 140 first instructing the fourth node 140 to forward data packets from data flow 102 to the destination node 190. Then, the controller 105 sends route information for data flow 102 to the third node 130 second instructing the third node 130 to forward data packets from data flow 102 to the fourth node 140. Next, the controller 105 sends route information for data flow 102 to the second node 120 third instructing the second node 120 to forward data packets from data flow 102 to the third node 130. Next, the controller 105 sends route information for data flow 102 to the first node 110 fourth instructing the first node 110 to forward data packets from data flow 102 to the second node 120.
Line module 301 may include hardware components, or a combination of hardware and software components, that may provide network interface operations. Line module 301 may receive a multi-wavelength optical signal and/or transmit a multi-wavelength optical signal. A multi-wavelength optical signal may include a number of optical signals of different optical wavelengths. In some implementations, line module 301 may perform retiming, reshaping, regeneration, time division multiplexing, and/or recoding services for each optical wavelength. Line module 301, associated with an ingress node, may also multiplex multiple signals into a super signal for transmission to one or more other core nodes.
Tributary module 302 may include hardware components, or a combination of hardware and software components, that may support flexible adding-dropping of multiple services, such as SONET/SDH services, gigabit Ethernet (Gbe) services, optical transport network (OTN) services, and/or fiber channel (FC) services. For example, tributary module 302 may include an optical interface device, such as a fiber optics module, a small-form pluggable (SFP) module, a tributary interface module (TIM), and/or some other type of optical interface device.
Switch fabric 303 may include hardware components, or a combination of hardware and software components, that may provide switching functions to transfer data between line modules 301 and/or tributary modules 302. In some implementations, switch fabric 303 may provide fully non-blocking transfer of data. Each switching plane 304 may be programmed to transfer data from a particular input to a particular output.
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Bus 305 may include a path that permits communication among the components of device 300. Processor 310 may include a processor, a microprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or another type of processor that interprets and executes instructions. Main memory 315 may include a random access memory (RAM) or another type of dynamic storage device that stores information or instructions for execution by processor 310. ROM 320 may include a ROM device or another type of static storage device that stores static information or instructions for use by processor 310. Storage device 325 may include a magnetic storage medium, such as a hard disk drive, or a removable memory, such as a flash memory.
Input device 330 may include a component that permits an operator to input information to device 300, such as a control button, a keyboard, a keypad, or another type of input device. Output device 335 may include a component that outputs information to the operator, such as a light emitting diode (LED), a display, or another type of output device. Communication interface 340 may include any transceiver-like mechanism that enables device 300 to communicate with other devices or networks. In some implementations, communication interface 340 may include a wireless interface, a wired interface, or a combination of a wireless interface and a wired interface.
Device 300 may perform certain operations, as described in detail below. Device 300 may perform these operations in response to processor 310 executing software instructions contained in a computer-readable medium, such as main memory 315. A computer-readable medium may be defined as a non-transitory memory device. A memory device may include memory space within a single physical storage device or memory space spread across multiple physical storage devices.
The software instructions may be read into main memory 315 from another computer-readable medium, such as storage device 325, or from another device via communication interface 340. The software instructions contained in main memory 315 may direct processor 310 to perform processes described above. Alternatively, hardwired circuitry may be used in place of or in combination with software instructions to implement processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software. In some implementations, device 300 may include additional components, fewer components, different components, or differently arranged components.
The network node 400 may further comprise a memory 422, which may be a memory configured to store a flow table, or a cache memory configured to store a cached flow table. The network node 400 may also comprise one or more egress ports 430 coupled to a transmitter 432 (Tx), which may be configured for transmitting packets or frames, objects, options, and/or TLVs to other network components. Note that, in practice, there may be bidirectional traffic processed by the network node 400, thus some ports may both receive and transmit packets. In this sense, the ingress ports 410 and the egress ports 430 may be co-located or may be considered different functionalities of the same ports that are coupled to transceivers (Rx/Tx). The processor 420, the memory 422, the receiver 412, and the transmitter 432 may also be configured to implement or support any of the schemes and methods described above, such as the protocol 300.
It is understood that by programming and/or loading executable instructions onto the network node 400, at least one of the processor 420 and the memory 422 are changed, transforming the network node 400 in part into a particular machine or apparatus (e.g. a SDN switch having the functionality taught by the present disclosure). The executable instructions may be stored on the memory 422 and loaded into the processor 420 for execution. It is fundamental to the electrical engineering and software engineering arts that functionality that can be implemented by loading executable software into a computer can be converted to a hardware implementation by well-known design rules. Decisions between implementing a concept in software versus hardware typically hinge on considerations of stability of the design and numbers of units to be produced rather than any issues involved in translating from the software domain to the hardware domain. Generally, a design that is still subject to frequent change may be preferred to be implemented in software, because re-spinning a hardware implementation is more expensive than re-spinning a software design. Generally, a design that is stable that will be produced in large volume may be preferred to be implemented in hardware, for example in an application specific integrated circuit (ASIC), because for large production runs the hardware implementation may be less expensive than the software implementation. Often a design may be developed and tested in a software form and later transformed, by well-known design rules, to an equivalent hardware implementation in an application specific integrated circuit that hardwires the instructions of the software. In the same manner, as a machine controlled by a new ASIC is a particular machine or apparatus, likewise a computer that has been programmed and/or loaded with executable instructions may be viewed as a particular machine or apparatus.
The system and schemes described above may be implemented on a network component or computer system, such as a computer or network component with sufficient processing power, memory resources, and network throughput capability to handle the necessary workload placed upon it.
The computer system 500 includes a processor 502 that is in communication with memory devices including secondary storage 504, read only memory (ROM) 506, random access memory (RAM) 508, input/output (I/O) devices 510, and transmitter/receiver 512. Although illustrated as a single processor, the processor 502 is not so limited and may comprise multiple processors. The processor 502 may be implemented as one or more central processor unit (CPU) chips, cores (e.g., a multi-core processor), field-programmable gate arrays (FPGAs), ASICs, and/or digital signal processors (DSPs). The processor 502 may be configured to implement any of the schemes described herein, including the protocol 300. The processor 502 may be implemented using hardware or a combination of hardware and software.
The secondary storage 504 is typically comprised of one or more disk drives or tape drives and is used for non-volatile storage of data and as an over-flow data storage device if the RAM 508 is not large enough to hold all working data. The secondary storage 504 may be used to store programs that are loaded into the RAM 508 when such programs are selected for execution. The ROM 506 is used to store instructions and perhaps data that are read during program execution. The ROM 506 is a non-volatile memory device that typically has a small memory capacity relative to the larger memory capacity of the secondary storage 504. The RAM 508 is used to store volatile data and perhaps to store instructions. Access to both the ROM 506 and the RAM 508 is typically faster than to the secondary storage 504.
The transmitter/receiver 512 (sometimes referred to as a transceiver) may serve as an output and/or input device of the computer system 500. For example, if the transmitter/receiver 512 is acting as a transmitter, it may transmit data out of the computer system 500. If the transmitter/receiver 512 is acting as a receiver, it may receive data into the computer system 500. Further, the transmitter/receiver 512 may include one or more optical transmitters, one or more optical receivers, one or more electrical transmitters, and/or one or more electrical receivers. The transmitter/receiver 512 may take the form of modems, modem banks, Ethernet cards, universal serial bus (USB) interface cards, serial interfaces, token ring cards, fiber distributed data interface (FDDI) cards, and/or other well-known network devices. The transmitter/receiver 512 may enable the processor 502 to communicate with an Internet or one or more intranets. The I/O devices 510 may be optional or may be detachable from the rest of the computer system 500. The I/O devices 510 may include a video monitor, liquid crystal display (LCD), touch screen display, or other type of display. The I/O devices 510 may also include one or more keyboards, mice, or track balls, or other well-known input devices.
Similar to the network node 400, it is understood that by programming and/or loading executable instructions onto the computer system 500, at least one of the processor 502, the secondary storage 504, the RAM 508, and the ROM 506 are changed, transforming the computer system 500 in part into a particular machine or apparatus (e.g. a controller 105 or client devices 180 and 190). The executable instructions may be stored on the secondary storage 504, the ROM 506, and/or the RAM 508 and loaded into the processor 502 for execution.
Any processing of the present disclosure may be implemented by causing a processor (e.g., a general purpose CPU) to execute a computer program. In this case, a computer program product can be provided to a computer or a network device using any type of non-transitory computer readable media. The computer program product may be stored in a non-transitory computer readable medium in the computer or the network device. Non-transitory computer readable media include any type of tangible storage media. Examples of non-transitory computer readable media include magnetic storage media (such as floppy disks, magnetic tapes, hard disk drives, etc.), optical magnetic storage media (e.g. magneto-optical disks), compact disc ROM (CD-ROM), compact disc recordable (CD-R), compact disc rewritable (CD-R/W), digital versatile disc (DVD), Blu-ray (registered trademark) disc (BD), and semiconductor memories (such as mask ROM, programmable ROM (PROM), erasable PROM, flash ROM, and RAM). The computer program product may also be provided to a computer or a network device using any type of transitory computer readable media. Examples of transitory computer readable media include electric signals, optical signals, and electromagnetic waves. Transitory computer readable media can provide the program to a computer via a wired communication line (e.g. electric wires, and optical fibers) or a wireless communication line. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any details described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other examples. Likewise, the term “examples” does not require that all examples include the discussed feature, advantage or mode of operation. Use of the terms “in one example,” “an example,” “in one feature,” and/or “a feature” in this specification does not necessarily refer to the same feature and/or example. Furthermore, a particular feature and/or structure can be combined with one or more other features and/or structures. Moreover, at least a portion of the apparatus described hereby can be configured to perform at least a portion of a method described hereby.
The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of examples of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof
It should be noted that the terms “connected,” “coupled,” or any variant thereof, mean any connection or coupling, either direct or indirect, between elements, and can encompass a presence of an intermediate element between two elements that are “connected” or “coupled” together via the intermediate element.
Any reference herein to an element using a designation such as “first,” “second,” and so forth does not limit the quantity and/or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and/or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must necessarily precede the second element. Also, unless stated otherwise, a set of elements can comprise one or more elements.
Further, many examples are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects of the disclosure may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the examples described herein, the corresponding form of any such examples may be described herein as, for example, “logic configured to” perform the described action.
Nothing stated or illustrated depicted in this application is intended to dedicate any component, step, feature, benefit, advantage, or equivalent to the public, regardless of whether the component, step, feature, benefit, advantage, or the equivalent is recited in the claims.
Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The methods, sequences and/or algorithms described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
Although some aspects have been described in connection with a device, it goes without saying that these aspects also constitute a description of the corresponding method, and so a block or a component of a device should also be understood as a corresponding method step or as a feature of a method step. Analogously thereto, aspects described in connection with or as a method step also constitute a description of a corresponding block or detail or feature of a corresponding device. Some or all of the method steps can be performed by a hardware apparatus (or using a hardware apparatus), such as, for example, a microprocessor, a programmable computer or an electronic circuit. In some examples, some or a plurality of the most important method steps can be performed by such an apparatus.
In the detailed description above it can be seen that different features are grouped together in examples. This manner of disclosure should not be understood as an intention that the claimed examples require more features than are explicitly mentioned in the respective claim. Rather, the situation is such that inventive content may reside in fewer than all features of an individual example disclosed. Therefore, the following claims should hereby be deemed to be incorporated in the description, wherein each claim by itself can stand as a separate example. Although each claim by itself can stand as a separate example, it should be noted that-although a dependent claim can refer in the claims to a specific combination with one or a plurality of claims-other examples can also encompass or include a combination of said dependent claim with the subject matter of any other dependent claim or a combination of any feature with other dependent and independent claims. Such combinations are proposed herein, unless it is explicitly expressed that a specific combination is not intended. Furthermore, it is also intended that features of a claim can be included in any other independent claim, even if said claim is not directly dependent on the independent claim.
It should furthermore be noted that methods disclosed in the description or in the claims can be implemented by a device comprising means for performing the respective steps or actions of this method.
Furthermore, in some examples, an individual step/action can be subdivided into a plurality of sub-steps or contain a plurality of sub-steps. Such sub-steps can be contained in the disclosure of the individual step and be part of the disclosure of the individual step.
While the foregoing disclosure shows illustrative examples of the disclosure, it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the examples of the disclosure described herein need not be performed in any particular order. Additionally, well-known elements will not be described in detail or may be omitted so as to not obscure the relevant details of the aspects and examples disclosed herein. Furthermore, although elements of the disclosure may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
