Patent Application
20090064075
The present invention relates generally to design, development and manufacturing of integrated circuits (ICs) on semiconductor chips, for use in automated computing systems. More particularly, the present invention relates to an integrated circuit (IC) schematic editing method and tool.
When conducting hierarchical design and physical development of ICs, circuit designers often face the problem of having voluminous smaller designs at various levels of the IC topological design hierarchy. A circuit designer often uses a schematic editor to edit the circuits in the various levels of the IC topological design hierarchy, and the designer usually has to maneuver through this hierarchy in an elementary fashion, only being able to move up or down one level of hierarchy at a time. Furthermore, while attempting to edit circuit schematics that traverse numerous design hierarchies within the same design window, all the viewable hierarchical design levels distract and may confuse the circuit designer conducting the editing process involving only a few targeted hierarchical levels. Although current electronic design automation tools offer methods of traversing design hierarchies within the same design window, none of these electronic design automation tools offer an easy interface to allow the user to traverse and edit multiple levels of design hierarchies and maintain a history of recently viewed schematics.
Therefore, the need exists for a hierarchical design navigation method and a navigation apparatus for use in schematic editing including device sizing, device editing, and other schematic modifications that are typical for those of ordinary skill in the art.
An additional need exists for a convenient design hierarchy method and device, which can save time and effort in viewing, editing and modifying design elements.
Furthermore, the need exists for a scroll mechanism to traverse design hierarchical design levels allowing circuit designers to control a definable viewable scope at different levels of design hierarchy quickly, which in turn will aid the editing process.
Further, the need exists for an editing tool that will maintain a history of recently viewed schematics during the editing process.
A schematic editor multi-window enhancement method and an apparatus are disclosed for displaying on a computer display device, a viewable scope of an at least one hierarchical level of design from a plurality of hierarchical levels of design of an integrated circuit. The user using an input device of a computer, opens a main window of the viewable scope of the at least one hierarchical level of design, and the main window includes a main editor screen. Using the input device, the user assigns a side window that is adjacent to the main editor screen, wherein the side-window holds and displays information about a set of schematics previously viewed; wherein the set of schematics previously viewed includes thumbnail views of a set of most recently viewed levels of hierarchy of the plurality of hierarchical levels of design from a circuit book. Again using the input device, the user descends and/or scrolls, using an input device, through the main editor screen into the at least one hierarchical level of design. The system populates the side window with a schematic that was last viewed in the main editor screen and the thumbnail view of the at least one hierarchical level of design that the user descended/scrolled through is surrounded by a highlighted border, thereby, enabling the user to view schematic elements underneath the at least one hierarchical level of design that the user descended/scrolled through and also enabling the user to see the thumbnail view of the top-level schematic that is contained in the at least one hierarchical level of design. When the user using the input device descends/scrolls through the main editor screen, into one of an other hierarchical level of design of the plurality of hierarchical levels of design, the main editor screen is refreshed by the system and associated thumbnail views are refreshed with a set of schematics that are underneath the other hierarchical level of design, wherein the user, using the input device, moves the input device between multiple levels of hierarchy at a time through the side window, and visual feedback of what schematics have been either viewed or edited is provided to the user. In addition, the side window includes a quantity of one or more windows, and these one or more are user configurable by the user using clicking the input device. Plus, the items in the side window are clickable, and are selected by the user clicking on the items, using the input device and thereby bringing the selected item back into the at least one hierarchical level of design in the main editor screen, and whereby the user controls the input device to perform a useful, concrete and tangible result of traversing the viewable scope of the at least one hierarchical level of design and conducting an editing operation of the integrated circuit under test, without distractions from voluminous levels of IC topological information, of the plurality of hierarchical levels of design.
The subject matter that is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings, which are meant to be exemplary, and not limiting, wherein:
Exemplary embodiments of a method and an apparatus are disclosed for display of hierarchical navigation in the design automation process of the design, physical development and manufacturing of integrated circuits including head and tail pointers used to define the viewable scope of the desired design hierarchy to be traversed. The disclosed exemplary embodiments are intended to be illustrative only, since numerous modifications and variations therein will be apparent to those of ordinary skill in the art. In reference to the drawings, like numbers will indicate like parts continuously throughout the view. Further, the terms “a”, “an”, “first”, and “third” herein do not denote limitations of quantity, but rather denote the presence of one or more of the referenced item(s).
A schematic editor multi-window enhancement display method 70 (herein referred to as “method 70”) and a schematic editor multi-window enhancement display system 20 (herein referred to as “system 20”) implementing method 70 are illustrated in
Referring to
In the exemplary embodiment, system 20 includes a combination of controllers including display controller 23, memory controller 25 and input/output (I/O) controller 27 and a combination of computer peripheral devices cooperatively coupled to system 20 including display 21, a set of input devices including keyboard 60 and mouse 29, network interface 28, and output device 34, via standard interface connectivity. Network interface 28 cooperatively couples computer workstation processor 22 via network 50 to integrated circuit test cradle 51. An integrated circuit simulator 52 is plugged into integrated circuit test cradle 51 to undergo testing and debugging exercises, as well as schematic design editing.
The schematic of the integrated circuit simulator 52 has a three dimensional layered topology of viewable design data comprising a plurality of hierarchical levels of design P53, including hierarchical levels of design L1, L2 up to Ln. Display 21 displays the plurality of hierarchical levels of design P53, when no limited viewable scope of hierarchical levels of design have been defined and set for viewing by the operator/user. In the alternative, display 21 displays only the viewable scope of hierarchical levels of design, which have been defined and set for viewing by the operator/user. By not displaying the viewable scope of the plurality of hierarchical levels of design, operator/user fatigue is reduced, causing the operator/user to make fewer mistakes in editing the schematics of the plurality of hierarchical levels of design of the IC under test 52, during the IC design and development process.
Referring to
At operation 73, using either of the input devices, i.e., either keyboard 60 or mouse 29 to input side window parameters into program 41, the user assigns side window parameters input into program 41, thereby enabling program 41, when executed by computer workstation processor 22 to open the plurality of side windows 195 adjacent to the main editor screen 102, wherein the plurality of side windows 195 hold and display information about a set of schematics previously viewed, and wherein the set of schematics previously viewed include thumbnail views of a set of most recently viewed levels of hierarchy of the plurality of hierarchical levels of design from a circuit book. In the exemplary embodiment illustrated in
At operation 74, using an input device, such as either keyboard 60 or mouse 29, the user interacts with program 41 which enables the user to scroll through the main editor screen 102 into the at least one hierarchical level of design of the plurality of hierarchical levels of design P53 of the integrated circuit simulator 52.
At operation 75, in association with the user scrolling through the main editor screen 102, program 41 causes the system to populate the side windows 195 with thumbnail views of a schematic S1 of the at least one hierarchical level of design that was last viewed in the main editor screen 102 and also causes the thumbnail view of the schematic A of the at least one hierarchical level of design L2 that the user scrolled through to be surrounded by a highlighted border and appears larger in size, thereby, enabling the user to view schematic elements underneath the at least one hierarchical level of design L2 that the user scrolled through and also enabling the user to see the thumbnail view of the top-level schematic S2 that is contained in the at least one hierarchical level of design L2.
At operation 76, using an input device, such as either keyboard 60 or mouse 29, the user interacts with program 41 which enables the user to scroll through the main editor screen 102 into one of another hierarchical level of design of the plurality of hierarchical levels of design L1, L2 up to Ln. When the user using the input device, scrolls through the main editor screen 102, into one of an other hierarchical level of design of the plurality of hierarchical levels of design L1, L2 up to Ln, the main editor screen 102 is refreshed by method 70 and associated thumbnail views are refreshed with a set of schematics that are underneath the other hierarchical level of design, wherein the user, using the input device, such as either keyboard 60 or mouse 29, moves the input device between multiple levels of hierarchy at a time through side window 104, and visual feedback of what schematics have been either viewed or edited is provided to the user. In the exemplary embodiment, the plurality of side windows 195 includes a quantity of one or more side windows 104, 105 and 106, and these one or more windows 104, 105 and 106 are user configurable by the user clicking the input device, such as either keyboard 60 or mouse 29. Thus, the cells A, B, C and D in side window 104 are clickable, and are selected by the user clicking on the elements/items, using the input device, such as either keyboard 60 or mouse 29 and thereby bringing cell items A1, A2 and A3 of the selected cell A back into the at least one hierarchical level of design L2 in the main editor screen 102, and whereby the user controls the input device, such as either keyboard 60 or mouse 29 to perform a useful, concrete and tangible result of traversing the viewable scope of the at least one hierarchical level of design and conducting an editing operation of the integrated circuit schematic being viewed, without distractions from voluminous levels of IC topological information, of the plurality of hierarchical levels of design L1, L2 up to Ln.
At return/end operation 77, method 70 repeatedly returns to operation 72 where the viewable scope of additional hierarchical levels of design of the plurality of hierarchical levels of design L1, L2 up to Ln can be defined by further assigning of side windows including side windows 105 and 106 containing additional schematics from the set of schematics, where additional iterations of the scrolling through the main editor screen 102 into an at least one hierarchical level of design of the plurality of hierarchical levels of design L1, L2 up to Ln and populating the plurality of side windows 195 are performed by the operator/user. Alternatively in the exemplary embodiment, at return/end operation 77, in accordance with method 70, the user can end the operation of method 70, by deactivating program 41 and ending the IC design navigation and editing session.
While the disclosure has been described with reference to an exemplary method and system embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the disclosure not be limited to the particular exemplary embodiment disclosed as the best mode contemplated for carrying out this disclosure, but that the disclosure will include all embodiments falling within the scope of the appended claims.
