Claims
- 1. An apparatus comprising:
a first system comprising a first plurality of interface circuits, each of the first plurality of interface circuits configured to couple to a separate interface; and a second system comprising a second plurality of interface circuits, each of the second plurality of interface circuits configured to couple to a separate interface; wherein a first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface, and wherein the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.
- 2. The apparatus as recited in claim 1 wherein the first system further comprises a first packet direct memory access (DMA) circuit, a first memory bridge, and a first interconnect to which the first packet DMA circuit and the first memory bridge are coupled, and wherein a third interface circuit of the first plurality of interface circuits is coupled to receive a packet on a second interface to which the third interface circuit is coupled, and wherein the third interface circuit is configured to transmit the packet to the first packet DMA circuit, and wherein the first packet DMA circuit is configured to generate one or more write transactions on the interconnect, and wherein the packet DMA circuit is programmable to generate addresses of the one or more write transactions that identify memory locations in a memory coupled to the second system.
- 3. The apparatus as recited in claim 2 wherein the first memory bridge is configured to detect the write transactions on the first interconnect and is configured to generate corresponding write commands in response to the write transactions, and wherein the first memory bridge is configured to transmit the write commands to the first interface circuit.
- 4. The apparatus as recited in claim 3 wherein the first interface circuit is configured to transmit the write commands on the first interface to the second interface circuit.
- 5. The apparatus as recited in claim 4 wherein the second system further comprises a second memory bridge, a second interconnect, and a memory controller, wherein the second memory bridge and the memory controller are coupled to the second interconnect, and wherein the second memory bridge is coupled to receive the write commands from the second interface circuit and to generate corresponding write transactions on the second interconnect to the memory controller, the memory controller configured to couple to the memory and to update the memory in response to the write transactions received on the second interconnect.
- 6. The apparatus as recited in claim 1 wherein the first system further comprises a memory controller, a packet direct memory access (DMA) circuit, and an interconnect, wherein the memory controller and the packet DMA circuit are coupled to the interconnect, and wherein the memory controller is coupled to a memory, and wherein the packet DMA circuit is configured to generate one or more read transactions to read a packet from the memory.
- 7. The apparatus as recited in claim 6 wherein the packet DMA circuit is configured to transmit the packet to the first interface circuit, and wherein the first interface circuit is configured to transmit the packet on the first interface to the second interface circuit.
- 8. The apparatus as recited in claim 7 wherein the second interface circuit is configured to transmit the packet to a third interface circuit of the second plurality of interface circuits, and wherein the third interface circuit is coupled to a second interface on which the third interface circuit is configured to transmit the packet.
- 9. The apparatus as recited in claim 8 further comprising a packet circuit coupled to the second interface and configured to receive the packet.
- 10. The apparatus as recited in claim 1 wherein a third interface circuit of the first plurality of interface circuits is coupled to a second interface, and wherein the first system further comprises a first packet direct memory access (DMA) circuit, and wherein the third interface circuit is coupled to receive a first packet and a second packet on the second interface, and wherein the third interface circuit is configured to transmit the first packet to the first packet DMA circuit and the second packet to the first interface circuit.
- 11. The apparatus as recited in claim 10 wherein the first system further comprises a first memory controller and a first interconnect, wherein the first packet DMA circuit and the first memory controller are coupled to the first interconnect, and wherein the first packet DMA circuit is configured to transmit one or more write transactions on the first interconnect to write the first packet to a first memory to which the first memory controller is coupled.
- 12. The apparatus as recited in claim 10 wherein the first interface circuit is configured to transmit the second packet on the first interface to the second interface circuit.
- 13. The apparatus as recited in claim 12 wherein the second system further comprises a second packet DMA circuit, a second interconnect, and a second memory controller, and wherein the second packet DMA circuit and the second memory controller are coupled to the second interconnect, and wherein the second interface circuit is configured to transmit the second packet to the second packet DMA circuit, and wherein the second packet DMA circuit is configured to transmit one or more write transactions on the second interconnect to write the second packet to a second memory to which the second memory controller is coupled.
- 14. The apparatus as recited in claim 1 wherein the first system further comprises a processor, an interconnect, and a memory bridge, wherein the processor and the memory bridge are coupled to the interconnect, and wherein the processor is configured to generate a noncoherent write transaction on the interconnect, and wherein the memory bridge is configured to generate a noncoherent write command in response to the noncoherent write transaction.
- 15. The apparatus as recited in claim 14 wherein the memory bridge is configured to transmit the noncoherent write command to the first interface circuit, and wherein the first interface circuit is configured to transmit the noncoherent write command on the first interface.
- 16. The apparatus as recited in claim 15 wherein the second interface circuit is configured to receive the noncoherent write command and to transmit the noncoherent write command to a third interface circuit of the second plurality of interface circuits, and wherein the third interface circuit is configured to transmit the noncoherent write command on a second interface to which the third interface circuit is coupled.
- 17. The apparatus as recited in claim 16 further comprising an input/output (I/O) circuit coupled to the third interface and configured to receive the noncoherent write command.
- 18. The apparatus as recited in claim 1 wherein the first system further comprises a processor, an interconnect, and a memory bridge, wherein the processor and the memory bridge are coupled to the interconnect, and wherein the processor is configured to generate a read transaction on the interconnect, and wherein the memory bridge is configured to generate a read command in response to the read transaction.
- 19. The apparatus as recited in claim 18 wherein the memory bridge is configured to transmit the read command to the first interface circuit, and wherein the first interface circuit is configured to transmit the read command on the first interface.
- 20. The apparatus as recited in claim 19 wherein the read command is a noncoherent read, and wherein the second interface circuit is configured to receive the read command and to transmit the read command to a third interface circuit of the second plurality of interface circuits, and wherein the third interface circuit is configured to transmit the read command on a second interface to which the third interface circuit is coupled.
- 21. The apparatus as recited in claim 20 further comprising an input/output (I/O) circuit coupled to the third interface and configured to receive the read command and respond with read data.
- 22. The apparatus as recited in claim 19 wherein the read command is a coherent read command, and wherein the second interface circuit is configured to receive the read command and to transmit the read command to a second memory bridge in the second system.
- 23. The apparatus as recited in claim 22 wherein the second memory bridge is configured to transmit a second read transaction on a second interconnect in the second system, and to generate a fill command include read data corresponding to the read command in response to a coherent completion of the second read transaction.
- 24. The apparatus as recited in claim 23 wherein the second memory bridge is configured to transmit the fill command to the second interface circuit, and wherein the second interface circuit is configured to transmit the fill command on the first interface.
- 25. The apparatus as recited in claim 24 wherein the first interface circuit is configured to receive the fill command and to route the fill command to the memory bridge in the first system, and wherein the memory bridge is configured to return the data to the processor as data for the read transaction.
- 26. A method comprising:
transmitting packets on an interface between a first system and a second system; transmitting coherency commands on the interface; and transmitting noncoherent commands on the interface.
Parent Case Info
[0001] This application claims benefit of priority to U.S. Provisional Patent Application Serial No. 60/380,740, filed May 15, 2002. This application claims benefit of priority to U.S. Provisional Patent Application Serial No. 60/331,789, filed Nov. 20, 2001. This application claims benefit of priority to U.S. Provisional Patent Application Serial No. 60/344,713, filed Dec. 24, 2001. This application claims benefit of priority to U.S. Provisional Patent Application Serial No. 60/348,777, filed Jan. 14, 2002. This application claims benefit of priority to U.S. Provisional Patent Application Serial No. 60/348,717, filed Jan. 14, 2002.
Provisional Applications (5)
|
Number |
Date |
Country |
|
60380740 |
May 2002 |
US |
|
60331789 |
Nov 2001 |
US |
|
60344713 |
Dec 2001 |
US |
|
60348777 |
Jan 2002 |
US |
|
60348717 |
Jan 2002 |
US |