T-switch buffer, in particular for FPGA architectures

Abstract

An embodiment of the invention relates to a T-switch for connecting first, second and third lines and comprising an input section in turn including first, second and third input pass transistors, each connecting a respective line with a first internal node of the T-switch, an output section in turn including first, second and third output pass transistors, each connecting a respective line with a second internal node of the T-switch, and a single buffer stage connected to a first and a second voltage reference and inserted between the first and second internal node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Characteristics and advantages of the T-switch according to one or more embodiments of the invention will be apparent from the following description of embodiment(s) thereof given by way of indicative and non limiting example with reference to the annexed drawings.

FIG. 1A schematically shows a FPGA architecture realized according to a known design;

FIG. 1B schematically shows in an island style a FPGA architecture realized according to a known design;

FIGS. 2A and 2B schematically show a switch configuration and a T-switch buffer for FPGA architectures, respectively, realized according to the prior art; and

FIG. 3 schematically shows a T-switch for FPGA architectures realized according to an embodiment of the present invention.

DETAILED DESCRIPTION

With reference to such figures, and in particular to FIG. 3, a T-switch realized according to an embodiment of the invention is schematically shown and globally indicated as 35.

As already described, the T-switch 35 realizes the connection between a first line L0, a second line L1 and a third line L2 and includes an input section 31 connected to the lines L0-L1 and to a first internal node int0; in particular, the input section 31 of the T-switch 35 comprises:

a first pass-transistor N0 connected between the first line L0 and the first internal node int0;a second pass-transistor N1 connected between the second line L1 and the first internal node int0; anda third pass-transistor N2 connected between the third line L2 and the first internal node int0.

In a similar manner, the T-switch 35 comprises an output section 32 connected to the lines L0-L1 and to a second internal node intO0 and comprising:

a third pass-transistor NO0 connected between the first line L0 and the second internal node intO0;a second pass-transistor N01 connected between the second line L1 and the second internal node intO0; anda third pass-transistor NO2 connected between the third line L2 and the second internal node intO0.

According to an embodiment of the invention, the T-switch 35 comprises a buffer stage 33 connected to a first and a second voltage reference, in particular a supply voltage reference VDD and ground GND and inserted between the first int0 and second internal node intO0.

When comparing the design of the T-switch 35 with the prior art solutions, in particular the switch 25 shown in FIG. 2A, it is thus noted that one additional input pass transistor (N0) and two additional output pass transistors (NO1 and NO2) have been added while only one buffer stage 33 is used instead of the three buffers comprised in the above indicate known solution.

As will be clear in the following description, according to an embodiment of the invention, the added pass transistors are configured to implement all the possible switching configurations among the lines L0-L2.

Moreover, the use of only one buffer stage 33 reduces both area occupation and leakage power.

Further according to an embodiment of the invention, the buffer stage 33 has been designed to reduce the leakage current through its components.

In particular, as shown in FIG. 3, the buffer stage 33 comprises:

a first pull up transistor P0 inserted between the supply voltage reference VDD and the first internal node int0 and having a gate terminal connected to a third internal node int1;

a first internal transistor P1 inserted between the supply voltage reference VDD and the third internal node int1 and having a gate terminal connected to the first internal node int0; and

a second internal transistor N4 inserted between a fourth internal node int2 and ground GND.

Moreover, the buffer stage 33 further comprises a third N3 and fourth internal transistor P2, inserted, in parallel to each other, between the third internal node int1 and the fourth internal node int2.

In the embodiment shown in FIG. 3, the first pull up transistor P0 is a High Voltage or HV MOS transistor of the P type, the first internal transistor P1 is a standard MOS transistor of the P type, the second internal transistor N4 is a standard MOS transistor of the N type, the third internal transistor N3 is High Voltage or HV MOS transistor of the N type, and the fourth internal transistor P2 is a High Voltage or HV MOS transistor of the P type. In particular, it should be noted that the third and fourth internal transistors, N3 and P2, form a high threshold CMOS stage 36.

The buffer stage 33 according to an embodiment of the invention further comprises:

a second pull up transistor P3 inserted between the supply voltage reference VDD and the third internal node int1; and

a pull down transistor N5 inserted between the fourth internal node int2 and ground GND.

In the embodiment shown in FIG. 3, the second pull up transistor P3 and the pull down transistor N5 are High Voltage or HV MOS transistors of the P and N type, respectively.

Finally, the buffer stage 33 comprises an inverter 34, inserted between the supply voltage reference VDD and ground GND and further comprising a first P4 and a second inverter transistor N6, in series to each other and having common drain terminals connected to the second internal node intO0.

More particularly, the first inverter transistor P4 has a gate terminal connected to the third internal node int1 and the second inverter transistor N6 has a gate terminal connected to the fourth internal node int2.

In the embodiment shown in FIG. 3, the first P5 and second inverter transistor N6 are standard MOS transistors of the P and N type, respectively.

The operation of the T-switch 35 according to an embodiment of the invention will be now briefly discussed.

In an idle state, i.e. when the switch is off, the second pull up transistor P3 and the pull down transistor N5 are turned on, while the other transistors are turned off (in particular, the first internal transistor P1 and the second internal transistor N4 have a drain-source voltage value Vds=0), keeping the second internal node intO0 in a high impedance condition.

In this condition, the second internal node intO0 assumes an intermediate voltage value between the supply voltage reference VDD and ground GND which is determined by the leakage current through the inverter transistors P4 and N6, and the output pass transistors N7, N8 and N9. In other words, such intermediate voltage value is determined by the voltage signals of the lines L0-L2.

Considering that the subthreshold current of a MOS transistor depends exponentially on its drain-source voltage value Vds, the intermediate voltage value of the second internal node intO0 greatly reduces the leakage consumption through the inverter transistors P4 and N6 and the output pass transistors N7, N8 and N9. In this way the T-switch 35 according to an embodiment of the invention implements the so called self reverse biasing technique.

It should be remarked that the leakage consumption through the above indicated transistors is the main contribution to the total leakage power dissipation of the T-switch 35, since the output stage 32 of the T-switch 35 has the widest transistors.

Similarly, the first internal node int0 is in the high impedance condition, thus reducing the leakage power of the input pass transistors N0, N1 and N2 as well.

Moreover, in a standby mode, the current path between the third internal node int1 (fixed to the supply voltage reference VDD) and fourth internal node int2 (fixed to ground GND) passes only through High Voltage transistors, more particularly the third internal transistor N3 and the fourth internal transistor P2, minimizing the leakage power dissipation of the input section 31 of the T-switch 35. In this way the T-switch 35 according to an embodiment of the invention implements the so called dual-threshold technique.

It should be however remarked that, from a timing performance point of view, the T-switch 35 according to an embodiment of the invention increases the signal delay compared to the switch 25 described with reference to prior art and shown in FIGS. 2A and 2B. This delay increase is mainly due to the introduction—in the signal path of the buffer stage 33—of the high threshold CMOS stage 36 comprising the internal transistors N3 and P3.

Moreover, since the T-switch 35 has a single buffer stage 33, its propagation delay is also affected by the fan-out, which can be one or two in the PiCoGA routing architecture.

According to an embodiment of the invention, the possibility to independently drive the input pass transistors N0, N1 and N2 of the T-switch 35 provides support for a software technique which reduces active leakage consumption.

In particular, the T-switch 35 may be exploited to propagate a signal between two lines by turning on a corresponding pass transistors in the input stage 31.

In FIG. 3, an unbuffered path connecting the first line L0 to the third line L2 is shown with a dashed line which passes through a series of two nMOS transistors, i.e. the first and third input pass transistors N0 and N2.

When the T-switch 35 is configured to operate in unbuffered mode, the corresponding buffer stage 33 can be completely switched off, turning off the output pass transistors NO0, NO1 and NO2 and the buffer stage 33.

As a result, the buffering part of the T-switch 35 has a same leakage current as obtained in the standby condition, even though the T-switch 35 is effectively used. In this case, the active leakage can be reduced by one order of magnitude.

The possibility of exploiting the T-switch 35 in the unbuffered mode is strictly related to the performance degradation deriving from the propagation of signals through a series of pass transistors instead of buffers.

In order to evaluate such a delay increase, an analysis has been carried out on a set of MCNC benchmark using VPR as described by Bets et al. in “Architecture and CAD for Deep-Submicron FPGAs”, Kluwer Academic Publishers, 1999, which is incorporated by reference.

A routing architecture with only unbuffered switches (modeled by cMOS pass-transistors) achieves the minimum active leakage power, since the buffering stage is completely avoided. However in this configuration the average critical path shows increases of about 20% on 80% of the studied benchmark and of 64% on the largest algorithms.

Since the routing architecture according to the T-switch 35 is based on nMOS pass transistors instead of cMOS ones, the degradation of a signal crossing a series of more than four switches may make this solution unacceptable both in terms of signal delay and of dynamic power dissipation.

Therefore, when using a T-switch 35 according to an embodiment of the invention, the substitution of buffered switches with unbuffered ones may be made only in the case the critical path is not increased.

In this regard, it should be noted that, in order to avoid excessive signal degradation, only series of at most two pass transistors should be allowed.

It should be remarked that, according to an embodiment of the invention, the input stage 31 of the T-switch 35 is used as an output stage in case of an unbuffered switch.

In order to avoid such a delay increase, an embodiment of the present invention relates to a configuration method that, starting from a routed circuit, considers the substitution of buffered switches with unbuffered ones only in the case the critical path is not modified.

According to an embodiment of the invention, the configuration method has been also developed to substitute the buffered switches with unbuffered ones in a circuit mapped on a FPGA architecture. The method comprises the following steps:

1) Timing analysis of the graph of nodes representing routing and logic resources of the FPGA architecture used by the mapped circuit. The slack obtained for each net represents the delay which can be added without modifying the critical path.

2) Substitution of a buffered switch with an unbuffered one starting from the input nodes of the analyzed circuit.

3) Verification that the critical path delay has not been modified through timing analysis.

4) If the substitution is done, all slacks are recalculated, returning to step 2.

The substitution of a buffered switch with an unbuffered one increases the delay of the related path. However, if the net is multi-fanout, its load capacitance may also increase, introducing an additional delay. Therefore step 3 may be necessary to correctly take in consideration this case.

As result, the proposed configuration method could substitute about 39% of buffered switches with unbuffered ones in one example, obtaining a corresponding reduction of active leakage power dissipation without performance degradation.

In order to avoid excessive signal degradation, a maximum number (in particular two) of pass transistors is allowed in the unbuffered mode, i.e. when the switch is active but no buffer stage is used.

As a result of the carried out analysis, it can be verified that in one example the above indicated algorithm could replace about 39% of buffered switches with unbuffered ones, obtaining a reduction of active leakage power dissipation without performance degradation.

A performance analysis of the T-switch 35 according to an embodiment of the invention has been performed, taking into account timing performance, area occupation, and leakage power consumption, which is a key issue, in particular with respect to the known solution shown in FIGS. 2A and 2B.

In both T-switches, the final inverter 32 and 21, respectively, has been designed with a same driving capability and then it has been tuned for each buffer in order to minimize signal propagation delay and to balance both the rise and fall paths.

The new T-switch 35 and known T-switch 25 have been analyzed comparing both an average standby and an active leakage power dissipation. In particular, the average values have been calculated considering each possible combination of signal at the lines (L0-L2), and, in the case of the active leakage, for two possible fan-out configurations of the switch.

The combination of the hardware techniques described (dual-threshold and self reverse biasing) used by the T-switch 35 reduces the average standby leakage power of 89% and the active leakage power of 47% with respect to the known T-switch 25.

It can be seen that the T-switch 35 used in unbuffered mode reduces the active subthreshold current of almost one order of magnitude with respect to the buffered mode.

However, since only 39% of the total switches can be changed from buffered to unbuffered mode without performance degradation in one example, a global reduction of the average active leakage power of 63% may be obtained in one example.

The analysis of the active leakage power has been carried out for each possible configurations of the switches, considering the signal values at the lines L0-L2. If we assume that a switch block consumes 58% of the leakage power of an entire tile, a 52% standby and 37% active leakage power reduction for an FPGA device can be achieved.

The T-switch 35 occupies 45% less area than the known T-switch 25, which leads to a 18% area reduction for the entire FPGA tile.

Moreover the T-switch 35 needs seven memory cells instead of nine to implement a full connectivity for the switch architecture analyzed.

It can be also verified that the T-switch 35 according to an embodiment of the invention has a signal propagation delay which is from 10% (fan out=1) to 25% (fan out=2) more than the one of the known solutions.

In summary, a T-switch 35 has been designed having a low leakage and also reducing area occupation of a standard implementation.

More particularly, by combining hardware and software techniques, both active and standby leakage power in FPGAs may be reduced.

In particular the use of the described software approach, which is related to the proposed switch architecture which provides for a single driving of the pass transistors, is useful to minimize active subthreshold current.

At the same time the hardware design of the switch buffer allows minimizing both the standby leakage current and the active one using a combination of dual threshold and self reverse biasing techniques.

Furthermore, advantageously according to an embodiment of the invention the area occupation of the proposed switch architecture has been reduced by about 50%.

Finally, a reduction of the number of switch configuration SRAMs has been also provided, requiring only a limited signal delay increasing (of about 10%).

The T-switch 35 of FIG. 3 may be incorporated in a first integrated circuit (IC) such as an FPGA, which may be incorporated into a system in which the first IC is coupled to a second IC such as a controller.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Claims

1. A T-switch for connecting first, second and third lines and comprising: an input section in turn including first, second, and third input pass transistors, each connecting a respective line with a first internal node of said T-switch;an output section in turn including first, second and third output pass transistors, each connecting a respective line with a second internal node of said T-switch; anda single buffer stage connected to a first and a second voltage reference and inserted between said first and second internal node.

2. The T-Switch of claim 1, wherein said buffer stage in turn comprises: a first pull up transistor inserted between said first voltage reference and said first internal node and having a gate terminal connected to a third internal node of said buffer stage;a first internal transistor inserted between said first voltage reference and said third internal node and having a gate terminal connected to said first internal node; anda second internal transistor inserted between a fourth internal node of said buffer stage and said second voltage reference.

3. The T-Switch of claim 2, wherein said buffer stage further comprises: a high threshold stage inserted between said third internal node and a fourth internal node of said buffer stage.

4. The T-Switch of claim 3, wherein said high threshold stage in turn comprises internal transistors inserted, in parallel to each other, between said third internal node and said fourth internal node.

5. The T-Switch of claim 3, wherein said buffer stage further comprises: a second pull up transistor inserted between said first voltage reference and said third internal node; anda pull down transistor inserted between said fourth internal node and said second voltage reference.

6. The T-Switch of claim 2, wherein said first pull up transistor is a High Voltage MOS transistor of the P type, said first internal transistor is a standard MOS transistor of the P type and said second internal transistor is a standard MOS transistor of the N type.

7. The T-Switch of claim 4, wherein said internal transistors of said high threshold stage are High Voltage MOS transistors of the N and P type, respectively.

8. The T-Switch of claim 5, wherein said second pull up transistor and said pull down transistor are High Voltage MOS transistors of the P and N type, respectively.

9. The T-Switch of claim 5, wherein said buffer stage further comprises an inverter, inserted between said first and second voltage references and further comprising a first and a second inverter transistors, in series to each other and having common drain terminals connected to said second internal node and respective gate terminals connected to said third internal node and said fourth internal node.

10. The T-Switch of claim 9, wherein said first and second inverter transistors are standard MOS transistors of the P and N type, respectively.

11. The T-Switch of claim 1, wherein said input section acts as an output stage when the T-switch is in an unbuffered configuration.

12. A configuration method of a FPGA architecture comprising a plurality of switch blocks, the method being applied to a circuit mapped on said FPGA architecture and comprising the following steps: 1) timing analysis of a graph of nodes representing routing and logic resources of said FPGA architecture used by said mapped circuit, the slack obtained for each net representing a delay which can be added without modifying a critical path;2) substitution of a buffered switch with an unbuffered one starting from input nodes of said analyzed circuit;3) verification that said critical path delay has not been modified through timing analysis;4) if a substitution is done, recalculation of all slacks, returning to step 2.

13. A pass gate, comprising: first and second input nodes;first and second output nodes;a single buffer having a buffer input node and a buffer output node;first and second input transistors respectively coupled between the first and second input nodes and the buffer input nodes; andfirst and second output transistors respectively coupled between the buffer output node and the first and second output nodes.

14. The pass gate of claim 13 wherein the buffer further comprises: a first reference node;a second reference node;a first transistor of a first type having a control node coupled to the buffer input node, a first conduction node coupled to the first reference node, and a second conduction node;a second transistor of the first type having a first conduction node coupled to the second conduction node of the first transistor and having a second conduction node;a third transistor of a second type having a first conduction node coupled to the second conduction node of the first transistor and having a second conduction node coupled to the second conduction node of the second transistor; anda fourth transistor of the second type having a control node coupled to the buffer input node, a first conduction node coupled to the second conduction node of the third transistor, and a second conduction node coupled to the second reference node.

15. The pass gate of claim 13 wherein the buffer further comprises: a first reference node;a second reference node;a first transistor of a first type having a control node coupled to the buffer input node, a first conduction node coupled to the first reference node, a second conduction node, and a first threshold magnitude;a second transistor of the second type having a first conduction node coupled to the second conduction node of the first transistor, a second conduction node, and a second threshold magnitude that is greater than the first threshold magnitude;a third transistor of a second type having a first conduction node coupled to the second conduction node of the first transistor, a second conduction node coupled to the second conduction node of the second transistor, and a third threshold magnitude; anda fourth transistor of the second type having a control node coupled to the buffer input node, a first conduction node coupled to the second conduction node of the third transistor, a second conduction node coupled to the second reference node, and a fourth threshold magnitude that less than the third threshold magnitude.

16. The pass gate of claim 13 wherein the buffer further comprises: a first reference node;a second reference node;a first transistor of a first type having a control node coupled to the buffer input node, a first conduction node coupled to the first reference node, and a second conduction node;a second transistor of the first type having a first conduction node coupled to the second conduction node of the first transistor and having a second conduction node;a third transistor of a second type having a first conduction node coupled to the second conduction node of the first transistor and having a second conduction node coupled to the second conduction node of the second transistor;a fourth transistor of the second type having a control node coupled to the buffer input node, a first conduction node coupled to the second conduction node of the third transistor, and a second conduction node coupled to the second reference node; anda fifth transistor of the first type having a control node coupled to the second conduction node of the first transistor, a first conduction node coupled to the first reference node, and a second conduction node coupled to the buffer input node.

17. The pass gate of claim 13 wherein the buffer further comprises: a first reference node;a second reference node;a first transistor of a first type having a control node coupled to the buffer input node, a first conduction node coupled to the first reference node, a second conduction node, and a first threshold magnitude;a second transistor of the second type having a first conduction node coupled to the second conduction node of the first transistor, a second conduction node, and a second threshold magnitude that is greater than the first threshold magnitude;a third transistor of a second type having a first conduction node coupled to the second conduction node of the first transistor, a second conduction node coupled to the second conduction node of the second transistor, and a third threshold magnitude;a fourth transistor of the second type having a control node coupled to the buffer input node, a first conduction node coupled to the second conduction node of the third transistor, a second conduction node coupled to the second reference node, and a fourth threshold magnitude that less than the third threshold magnitude; anda fifth transistor of the first type having a control node coupled to the second conduction node of the first transistor, a first conduction node coupled to the first reference node, a second conduction node coupled to the buffer input node, and a fifth threshold magnitude that is greater than the first threshold magnitude.

18. The pass gate of claim 13 wherein the buffer further comprises: a first reference node;a second reference node;a first transistor of a first type having a first conduction node coupled to the first reference node and having a second conduction node;a second transistor of the first type having a control node coupled to the second conduction node of the first transistor, a first conduction node coupled to the first reference node, and a second conduction node coupled to the buffer output node;a third transistor of a second type having a control node, a first conduction node coupled to the buffer output node, and a second conduction node coupled to the second reference node; anda fourth transistor of the second type having a first conduction node coupled to the control node of the third transistor and having a second conduction node coupled to the second reference node.

19. The pass gate of claim 13 wherein the buffer further comprises: a first reference node;a second reference node;a first transistor of a first type having a first conduction node coupled to the first reference node, a second conduction node, and a first threshold magnitude;a second transistor of the first type having a control node coupled to the second conduction node of the first transistor, a first conduction node coupled to the first reference node, a second conduction node coupled to the buffer output node, and a second threshold magnitude that is less than the first threshold;a third transistor of a second type having a control node, a first conduction node coupled to the buffer output node, a second conduction node coupled to the second reference node, and a third threshold magnitude; anda fourth transistor of the second type having a first conduction node coupled to the control node of the third transistor, a second conduction node coupled to the second reference node, and a fourth threshold magnitude that is greater than the third threshold magnitude.

20. The pass gate of claim 13, further comprising: a third input node;a third output node;a third input transistor coupled between the third input node and the buffer input node; anda third output transistor coupled between the buffer output node and the third output node.

21. An integrated circuit, comprising: a first circuit;a second circuit; anda programmable pass gate operable to couple the first circuit to the second circuit, the pass gate comprising, first and second input nodes,first and second output nodes,a single buffer having a buffer input node and a buffer output node,first and second input transistors respectively coupled between the first and second input nodes and the buffer input nodes, andfirst and second output transistors respectively coupled between the buffer output node and the first and second output nodes.

22. A system, comprising: a first circuit;a second circuit;a programmable pass gate operable to couple the first circuit to the second circuit, the pass gate comprising, first and second input nodes,first and second output nodes,a single buffer having a buffer input node and a buffer output node,first and second input transistors respectively coupled between the first and second input nodes and the buffer input nodes, andfirst and second output transistors respectively coupled between the buffer output node and the first and second output nodes; anda controller coupled to the first circuit.

23. The system of claim 22 wherein the first circuit, second circuit, pass gate, and controller are disposed on a same die.

24. The system of claim 22 wherein: the first circuit, second circuit, and pass gate are disposed on a first die; andthe controller is disposed on a second die.

25. The system of claim 22 wherein the first circuit, second circuit, and pass gate are disposed on an FPGA.

26. A method, comprising: routing a circuit for instantiation on an FPGA;determining delays through all paths that include a routing switch assuming that the routing switch has an unbuffered configuration;comparing the respective delay for each path to a respective pre-established maximum delay for the path; andassigning to the routing switch the unbuffered configuration if none of the delays respectively exceed the pre-established maximum delays.

27. The method of claim 26, further comprising assigning to the routing switch a buffered configuration if one of the delays exceeds the respective pre-established maximum delay.

28. The method of claim 26, further comprising generating firmware that represents the routed circuit after assigning a configuration to the routing switch.

29. The method of claim 26 wherein routing the circuit comprises routing the circuit with a routing tool running on a computer.

30. The method of claim 26, further comprising instantiating the circuit on the FPGA after assigning a configuration to the routing switch.