Patent Application
20240302996
This application relates to the field of communications technologies, and in particular, to a table entry reading method and apparatus, a network device, and a computer-readable storage medium.
With development of network technologies, routing table lookups for routers are facing a challenge of high reliability. A double data rate (Double Data Rate, DDR) synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM) is characterized by a large capacity and low costs, and is usually used to store routing tables.
In the foregoing solution, the interface modules, the DDR controllers, and the DDR SDRAMs are in a one-to-one correspondence. If a DDR controller fails, a read command sent by a corresponding interface module cannot be processed, affecting table lookup access. In addition, bandwidth cannot be shared between DDR interfaces.
Embodiments of this application provide a table entry reading method and apparatus, a network device, and a computer-readable storage medium.
According to a first aspect, an embodiment of this application provides a table entry reading method, where the table entry reading method is applied to a table entry reading device, and the table entry reading device includes a crossing module, a plurality of interface modules communicatively connected to the crossing module, a plurality of controllers communicatively connected to the crossing module, and a plurality of memories respectively corresponding to the plurality of controllers; where the plurality of interface modules include a first interface module, the plurality of controllers include a first controller, the plurality of memories include a first memory, and the first controller corresponds to the first memory; and
Based on the foregoing solution, because the interface modules, the controllers, and the memories can cross-transmit read commands and table entries, if a controller fails, other controllers may be used, so that reliability of table entry reading can be improved. In addition, because the interface modules, the controllers, and the memories are not in a one-to-one correspondence, interface bandwidth can be shared between the interface modules and the controllers, so that bandwidth utilization can be improved. This resolves a problem in the conventional technology that reliability is low and bandwidth utilization cannot be maximized during multi-interface DDR table lookup access.
In a possible implementation, the recording a correspondence between the first interface module and the first controller includes:
In a possible implementation, before the step of sending the first read command to the target controller, the method further includes:
In a possible implementation, the plurality of interface modules further include a second interface module, and the method further includes:
In a possible implementation, the command cache queue corresponding to the first controller includes a plurality of command cache sub-queues respectively corresponding to the plurality of interface modules, the first interface module corresponds to a first command cache sub-queue, and the second interface module corresponds to a second command cache sub-queue; and
In a possible implementation, the plurality of controllers further include a second controller, and the plurality of memories further include a second memory corresponding to the second controller; and
sending the third read command to the second controller, so that the second controller obtains, from the corresponding second memory, a third table entry corresponding to the third read command; and
In a possible implementation, the table entry storage queue includes a first table entry storage sub-queue and a second table entry storage sub-queue, the first table entry storage sub-queue corresponds to the first interface module, and the second table entry storage sub-queue corresponds to the second interface module;
In a possible implementation, the method further includes:
In a possible implementation, the determining the first controller from the plurality of controllers as a target controller according to a preset polling rule includes:
In a possible implementation, the determining the first controller from the plurality of controllers as a target controller according to a preset polling rule further includes:
In a possible implementation, the preset polling rule is:
In a possible implementation, when the first controller is in a busy state and/or an abnormal state, state information of the first controller is an unavailable state; and/or
In a possible implementation, the method in the foregoing embodiment is applied to a crossing module included in a table entry reading device of a network device, the table entry reading device further includes at least two interface modules, at least two controllers, and a memory corresponding to each controller, and the method includes:
Based on the foregoing solution, the candidate controller is determined according to the preset polling rule; then the state information of the command cache sub-queue that is in the command cache queue of the candidate controller and that corresponds to the any interface module is determined; and finally, the target controller is determined based on whether the state information is busy or non-busy. In this way, a non-busy controller is selected from the candidate controller as the target controller, so that efficiency of table entry reading can be improved.
In a possible implementation, the determining state information of a command cache sub-queue that is in a command cache queue of the candidate controller and that corresponds to the any interface module specifically includes:
Based on the foregoing solution, a quantity of read commands stored in the command cache sub-queue that is in the command cache queue of the candidate controller and that corresponds to the any interface module is compared with the first specified threshold, and whether the state information of the command cache sub-queue is the non-busy state or the busy state is determined based on a comparison result. Because the first specified threshold is preset, the state information of the command cache sub-queue can be set flexibly.
In a possible implementation, before the determining the candidate controller as a target controller of this time, the method further includes:
Based on the foregoing solution, before the candidate controller is determined as the target controller of this time, the target controller is determined based on whether the state information of the candidate controller is abnormal or normal, to avoid using an abnormal alternative controller as the target controller. This makes the determined target controller more accurate, and improves reliability of table entry reading.
In a possible implementation, the determining state information of the candidate controller specifically includes:
Based on the foregoing solution, a quantity of the obtained error information that is obtained by verifying the obtained table entry and that is sent by the candidate controller is compared with the second specified threshold, and whether the candidate controller is normal or abnormal is determined based on a comparison result. Because the second specified threshold is preset, flexibility of determining the state information of the candidate controller can be improved.
In a possible implementation, the according to an order in which controller identifiers in a controller identifier cache queue corresponding to each interface module are added, sending, to a corresponding interface module, a table entry in a table entry cache sub-queue that is in each table entry cache queue of each interface module and that corresponds to each controller includes:
Based on the foregoing solution, a table entry stored in a table entry cache sub-queue that is in each table entry cache queue of each interface module and that corresponds to the previously stored controller identifier is first sent to a corresponding interface module. This can ensure ordered output of table entries, and improve reliability of table entry reading.
In a possible implementation, after the adding the table entry to a first table entry cache sub-queue that is in a table entry cache queue of an interface module corresponding to the target module identifier and that corresponds to the any controller, the method further includes:
Based on the foregoing solution, a previously stored module identifier and a previously stored controller identifier are first deleted, to ensure ordered output of table entries next time, and improve reliability of table entry reading.
According to a second aspect, an embodiment of this application further provides a table entry reading apparatus, applied to a crossing module included in a table entry reading device of a network device, where the table entry reading device further includes at least two interface modules, at least two controllers, and a memory corresponding to each controller, and the table entry reading apparatus includes a command crossing unit and a data crossing unit.
The command crossing unit is configured to: after a read command sent by any one of the at least two interface modules is received, determine a target controller according to a preset polling rule and based on state information of a command cache sub-queue that is in a command cache queue of each controller and that corresponds to the any interface module, add a controller identifier for the target controller to a controller identifier cache queue corresponding to the any interface module, and add the read command to a command cache sub-queue that is in a command cache queue of the target controller and that corresponds to the any interface module; and send, to a corresponding controller according to a load balancing principle, a read command in each command cache sub-queue included in each command cache queue of each controller, and add a module identifier for an interface module corresponding to a command cache sub-queue in which the sent read command is located to a module identifier cache queue of a controller corresponding to the sent read command, so that each controller obtains, from a corresponding memory, a table entry corresponding to the received read command.
The data crossing unit is configured to: after a table entry returned by any one of the at least two controllers is received, first obtain a previously stored target module identifier from a module identifier cache queue corresponding to the any controller, and add the received table entry to a table entry cache sub-queue that is in a table entry cache queue of an interface module corresponding to the target module identifier and that corresponds to the any controller; and according to an order in which controller identifiers in a controller identifier cache queue corresponding to each interface module are added, send, to a corresponding interface module, a table entry in a table entry cache sub-queue that is in each table entry cache queue of each interface module and that corresponds to each controller.
In a possible implementation, the command crossing unit is specifically configured to:
In a possible implementation, the command crossing unit is specifically configured to:
In a possible implementation, before the determining the candidate controller as a target controller of this time, the command crossing unit is further configured to:
In a possible implementation, the command crossing unit is specifically configured to:
In a possible implementation, the data crossing unit is specifically configured to:
In a possible implementation, after the adding the received table entry to a table entry cache sub-queue that is in a table entry cache queue of an interface module corresponding to the target module identifier and that corresponds to the any controller, the data crossing unit is further configured to:
According to a third aspect, an embodiment of this application further provides a network device, including a table entry reading device, where the table entry reading device includes at least two interface modules, at least two controllers, a memory corresponding to each controller, and the table entry reading apparatus according to any one of the implementations of the second aspect.
According to a fourth aspect, an embodiment of this application further provides a computer-readable storage medium, where
For the aspects of the second aspect to the fourth aspect and technical effects that can be achieved in the aspects, refer to the descriptions of the technical effects that can be achieved in the first aspect or the possible solutions of the first aspect. Details are not repeated herein again.
To describe the technical solutions in this application more clearly, the following briefly describes the accompanying drawings for describing the embodiments. Clearly, the accompanying drawings in the following descriptions show merely some embodiments of this application, and persons of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.
To make the objectives, technical solutions, and advantages clearer, the following clearly and completely describes the technical solutions in the embodiments of this application with reference to the accompanying drawings. Clearly, the described embodiments are merely some but not all of the embodiments of this application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of this application shall fall within the protection scope of this application.
To improve reliability of table entry reading and improve utilization of interface bandwidth, an embodiment of this application provides a table entry reading method, applied to a crossing module 200 included in a table entry reading device of a network device. As shown in
S301: After a read command sent by any one of at least two interface modules is received, determine a target controller according to a preset polling rule and based on state information of a command cache sub-queue that is in a command cache queue of each controller and that corresponds to the any interface module, add a controller identifier for the target controller to a controller identifier cache queue corresponding to the any interface module, and add the read command to a command cache sub-queue that is in a command cache queue of the target controller and that corresponds to the any interface module. The command cache sub-queue is added. Even if a current controller is in an operating state, a read command can still be allocated to the controller, to improve processing efficiency of a processor.
S302: Send, to a corresponding controller according to a load balancing principle, a read command in each command cache sub-queue included in each command cache queue of each controller, and add a module identifier for an interface module corresponding to a command cache sub-queue in which the sent read command is located to a module identifier cache queue of a controller corresponding to the sent read command, so that each controller obtains, from a corresponding memory, a table entry corresponding to the received read command.
S303: After a table entry returned by any one of the at least two controllers is received, first obtain a previously stored target module identifier from a module identifier cache queue corresponding to the any controller, and add the received table entry to a table entry cache sub-queue that is in a table entry cache queue of an interface module corresponding to the target module identifier and that corresponds to the any controller. The table entry cache queue is set. Even if an interface module is busy, a read table entry can be stored, so that a controller can continue to process a next read command, and reading efficiency is improved. In addition, table entries belonging to one interface module may be cached in one table entry cache queue, to simplify logic of subsequent sending.
S304: According to an order in which controller identifiers in a controller identifier cache queue corresponding to each interface module are added, send, to a corresponding interface module, a table entry in a table entry cache sub-queue that is in each table entry cache queue of each interface module and that corresponds to each controller. Table entries in a table entry cache sub-queue are sent according to an order in which controller identifiers in a controller identifier cache queue are added. In this way, table entries received by each interface module can be consistent with an order in which read commands are sent, to ensure that each interface module receives table entries correctly in an ordered manner.
In the table entry reading method provided in this embodiment of this application, because the interface modules, the controllers, and the memories can cross-transmit read commands and table entries, if a controller fails, other controllers may be used, so that reliability of table entry reading can be improved. In addition, because the interface modules, the controllers, and the memories are not in a one-to-one correspondence, interface bandwidth can be shared between the interface modules and the controllers, so that bandwidth utilization can be improved.
In a specific implementation, the table entry reading device may be a field programmable logic gate array (English: Field Programmable Gate Array, FPGA for short) or another programmable device, and the crossing module in this embodiment of this application may be an FPGA, another programmable device, an application-specific integrated circuit (English: Application Specific Integrated Circuit, ASIC for short) chip, or the like. The controller in this embodiment of this application may be a DDR controller, the memory may be a DDR SDRAM, the crossing module may be a DDR crossing module, and the cache queue may be a first in first out (English: First Input First Output, FIFO for short) queue.
An embodiment of this application further provides a table entry reading method, where the method is applied to a table entry reading device, and the table entry reading device includes a crossing module, a plurality of interface modules communicatively connected to the crossing module, a plurality of controllers communicatively connected to the crossing module, and a plurality of memories respectively corresponding to the plurality of controllers; where the plurality of interface modules include a first interface module, the plurality of controllers include a first controller, the plurality of memories include a first memory, the first controller corresponds to the first memory, and the table entry reading method includes the following steps.
S401: Receive a first read command sent by the first interface module. It can be understood that the first interface module herein may be any one of the plurality of interface modules.
S402: Determine the first controller from the plurality of controllers as a target controller according to a preset polling rule, and determine a correspondence between the first interface module and the first controller. It can be understood that the first controller herein may be any one of the plurality of controllers that meets a condition, and the target controller herein corresponds to the first read command. It can also be understood that after the correspondence between the first interface module and the first controller is determined, the correspondence can be recorded.
S403: Send the first read command to the first controller, so that the first controller obtains, from the corresponding first memory, a first table entry corresponding to the first read command.
S404: Receive the first table entry returned by the first controller, and send the first table entry to the first interface module based on the correspondence between the first interface module and the first controller.
This embodiment of this application is described below by using a DDR crossing module, a DDR controller, and a DDR SDRAM as examples, and by using an example in which a cache queue is FIFO and quantities of interface modules and controllers are both 6.
Based on the diagram of the table entry reading architecture shown in
It can be understood that, before a table entry is read, to parse CPU configuration commands, the table entry configuration module may configure table entries into a plurality of sets of DDR memories. In a possible implementation, table entries are configured into all DDR memories.
In this embodiment of this application, each interface module corresponds to one module identifier. For example, a module identifier corresponding to an interface module 0 is 0, and a module identifier corresponding to an interface module 1 is 1. Each DDR controller corresponds to one controller identifier. For example, a controller identifier corresponding to a DDR controller 0 is 0, a controller identifier corresponding to a DDR controller 1 is 1, and a controller identifier corresponding to a DDR controller 2 is 2.
As shown in
The FIFO3 is a command cache queue, and each DDR controller corresponds to one command cache queue FIFO3. For example, a command cache queue corresponding to the DDR controller 0 is a FIFO30, and a command cache queue corresponding to the DDR controller 1 is a FIFO31. Each command cache queue includes a command cache sub-queue corresponding to an interface module. For example, the command cache queue FIFO30 corresponding to the DDR controller 0 includes a command cache sub-queue FIFO30_0 corresponding to the interface module 0, a command cache sub-queue FIFO30_1 corresponding to the interface module 1, a command cache sub-queue FIFO30_2 corresponding to an interface module 2, a command cache sub-queue FIFO30_3 corresponding to an interface module 3, a command cache sub-queue FIFO30_4 corresponding to an interface module 4, and a command cache sub-queue FIFO30_5 corresponding to an interface module 5.
The FIFO4 is a table entry cache queue, and each interface module corresponds to one table entry cache queue FIFO4. For example, a table entry cache queue corresponding to the interface module 0 is a FIFO40, and a table entry cache queue corresponding to the interface module 1 is a FIFO41. Each table entry cache queue includes a table entry cache sub-queue corresponding to a DDR controller. For example, the table entry cache queue FIFO40 corresponding to the interface module 0 includes a table entry cache sub-queue FIFO40_0 corresponding to the DDR controller 0, a table entry cache sub-queue FIFO40_1 corresponding to the DDR controller 1, a table entry cache sub-queue FIFO40_2 corresponding to the DDR controller 2, a table entry cache sub-queue FIFO40_3 corresponding to a DDR controller 3, a table entry cache sub-queue FIFO40_4 corresponding to a DDR controller 4, and a table entry cache sub-queue FIFO40_5 corresponding to a DDR controller 5.
The table entry reading method provided in the embodiments of this application is described in detail below with reference to
The DDR command crossing unit 4021 receives a read command sent by any interface module 103. The DDR command crossing unit 4021 determines a target DDR controller according to a preset polling rule and based on state information of a command cache sub-queue that is in a command cache queue FIFO3 of each DDR controller 104 and that corresponds to the any interface module, adds a controller identifier for the target DDR controller to a controller identifier cache queue FIFO1 corresponding to the any interface module 103, and adds the read command to a command cache sub-queue that is in a command cache queue FIFO3 of the target DDR controller and that corresponds to the any interface module 103.
For example, as shown in
In a specific implementation, the determining a target DDR controller may be: determining a candidate DDR controller after a last determined target DDR controller according to the preset polling rule; then determining state information of a command cache sub-queue that is in a command cache queue of the candidate DDR controller and that corresponds to any interface module; and if it is determined that the state information of the command cache sub-queue corresponding to the any interface module is busy, updating the candidate DDR controller to a DDR controller after the candidate DDR controller, and performing the step of determining state information of a command cache sub-queue that is in a command cache queue of the candidate DDR controller and that corresponds to the any interface module; or if it is determined that the state information of the command cache sub-queue corresponding to the any interface module is non-busy, determining the candidate DDR controller as a target DDR controller of this time.
For example, the preset polling rule is to sequentially performing polling based on controller identifiers of DDR controllers. With reference to
Specifically, the determining state information of a command cache sub-queue may be: obtaining a first quantity of read commands stored in the command cache sub-queue that is in the command cache queue of the candidate DDR controller and that corresponds to the any interface module; determining whether the first quantity is less than a first specified threshold; and if the first quantity is less than the first specified threshold, determining that the state information of the command cache sub-queue corresponding to the any interface module is a non-busy state; or if the first quantity is not less than the first specified threshold, determining that the state information is a busy state.
For example, with reference to
In an implementation, during determining of the target DDR controller, in addition to state information of a command cache sub-queue that is in a command cache queue of a DDR controller and that corresponds to the interface module sending the read command, state information, that is, an abnormal or normal state, of the DDR controller further needs to be determined. The DDR controller can be used as the target DDR controller only if the state information of the DDR controller is the normal state.
Specifically, during table entry configuration, CRC is calculated based on content of a table entry, and is denoted as CRC_WR. The CRC_WR is placed in an unused most significant bit of the table entry.
When a table entry is returned, after obtaining the table entry, a DDR controller calculates table entry content of the table entry by using a same algorithm that is used to calculate the CRC_WR, to obtain CRC_RD. The DDR controller obtains the CRC_WR from the table entry, compares the CRC_WR with the CRC_RD. If the CRC_WR is the same as the CRC_RD, it is determined that the table entry returned this time is correct; otherwise, it is determined that the returned table entry is incorrect. If it is determined that the returned table entry is incorrect, one count is performed, and the count value may be sent to the DDR crossing module.
The DDR crossing module monitors the received count value; and if the count value is greater than a second specified threshold, determines that the state information of the DDR controller is abnormal; or if the count value is not greater than the second specified threshold, determines that the state information of the DDR controller is normal.
In a specific implementation, if the state information of the candidate DDR controller is normal, and the state information of the command cache sub-queue that is in the command cache queue and that corresponds to the interface module sending the read command is a non-busy state, the candidate DDR controller is used as the target DDR controller; or if the state information of the candidate DDR controller is abnormal, and the state information of the command cache sub-queue that is in the command cache queue and that corresponds to the interface module sending the read command is a non-busy state, the candidate DDR controller is updated to a DDR controller after the candidate DDR controller, and the step of determining state information of a command cache sub-queue that is in the command cache queue of the candidate DDR controller and that corresponds to the interface module sending the read command is performed.
For example, with reference to
The DDR command crossing unit 4021 determines the target DDR controller, adds a controller identifier for the target DDR controller to a controller identifier cache queue FIFO1 corresponding to the interface module sending the read command, and adds the read command to a command cache sub-queue that is in a command cache queue FIFO3 of the target DDR controller and that corresponds to the interface module sending the read command; and sends, to a corresponding DDR controller according to a load balancing principle, a read command in each command cache sub-queue included in a command cache queue FIFO3 corresponding to each DDR controller, and adds a module identifier for an interface module corresponding to a command cache sub-queue in which the read command is located to a module identifier cache queue FIFO2 of a controller corresponding to the sent read command, so that each DDR controller obtains, from a corresponding DDR SDRAM, a table entry corresponding to a received read command.
With reference to
The processes of sending a read command, obtaining a table entry, storing a controller identifier, and storing a module identifier are described above, and the following describes how to send a table entry to an interface module.
As shown in
For example, with reference to
After adding a received table entry to a corresponding table entry cache sub-queue, according to an order in which DDR controller identifiers in a controller identifier cache queue FIFO1 corresponding to each interface module are added, the DDR data crossing unit 4022 sends, to a corresponding interface module, a table entry in a table entry cache sub-queue that is in each table entry storage queue FIFO4 of each interface module and that corresponds to each DDR controller.
Specifically, the DDR data crossing unit 4022 obtains a first stored controller identifier from a controller identifier cache queue corresponding to each interface module, and then sends, to a corresponding interface module, a table entry stored in a table entry cache sub-queue that is in each table entry cache queue FIFO4 of each interface module and that corresponds to the first stored controller identifier.
For example, with reference to
In an embodiment, after a table entry is added to a table entry cache sub-queue that is in a table entry cache queue of an interface module corresponding to a target module identifier and that corresponds to any DDR, the target module identifier is deleted from a module identifier cache queue corresponding to the any DDR controller; and after a table entry in a table entry cache sub-queue that is in each table entry cache queue of each interface module and that corresponds to each DDR controller is sent to a corresponding interface module, a first stored controller identifier is deleted from a controller identifier cache queue corresponding to each interface module.
For example, with reference to
In the foregoing embodiment, it can be ensured that a table entry can be output in an ordered manner next time, to improve accuracy of table entry reading.
In the table entry reading method provided in the embodiments of this application, the DDR crossing module is used to select a DDR controller from at least two DDR controllers as a target DDR controller. Compared with a mode in the conventional technology in which an interface module and a DDR controller are in a one-to-one correspondence, this is more flexible, and can improve reliability of table entry reading and dynamically balance and share bandwidth between DDR interfaces.
Based on a same inventive concept, an embodiment of this application further provides a table entry reading apparatus, applied to a table entry reading device of a network device, where the table entry reading device includes a crossing module, at least two interface modules, at least two controllers, and a memory corresponding to each controller, and the table entry reading apparatus includes a command crossing unit and a data crossing unit.
The command crossing unit is configured to: after a read command sent by any one of the at least two interface modules is received, determine a target controller according to a preset polling rule and based on state information of a command cache sub-queue that is in a command cache queue of each controller and that corresponds to the any interface module, add a controller identifier for the target controller to a controller identifier cache queue corresponding to the any interface module, and add the read command to a command cache sub-queue that is in a command cache queue of the target controller and that corresponds to the any interface module; and send, to a corresponding controller according to a load balancing principle, a read command in each command cache sub-queue included in each command cache queue of each controller, and add a module identifier for an interface module corresponding to a command cache sub-queue in which the sent read command is located to a module identifier cache queue of a controller corresponding to the sent read command, so that each controller obtains, from a corresponding memory, a table entry corresponding to the received read command.
The data crossing unit is configured to: after a table entry returned by any one of the at least two controllers is received, first obtain a previously stored target module identifier from a module identifier cache queue corresponding to the any controller, and add the received table entry to a table entry cache sub-queue that is in a table entry cache queue of an interface module corresponding to the target module identifier and that corresponds to the any controller; and according to an order in which controller identifiers in a controller identifier cache queue corresponding to each interface module are added, send, to a corresponding interface module, a table entry in a table entry cache sub-queue that is in each table entry cache queue of each interface module and that corresponds to each controller.
Optionally, the command crossing unit is specifically configured to:
Optionally, the command crossing unit is specifically configured to:
Optionally, before the determining the candidate controller as a target controller of this time, the command crossing unit is further configured to:
Optionally, the command crossing unit is specifically configured to:
Optionally, the data crossing unit is specifically configured to:
Optionally, after the adding the received table entry to a table entry cache sub-queue that is in a table entry cache queue of an interface module corresponding to the target module identifier and that corresponds to the any controller, the data crossing unit is further configured to:
Based on a same inventive concept, an embodiment of this application further provides a network device, including a table entry reading device, where the table entry reading device includes at least two interface modules, at least two controllers, a memory corresponding to each controller, and the table entry reading apparatus according to any one of the foregoing implementations.
It should be noted that, although the DDR is used as an example for description in the embodiments of this application, application scenarios of this application are not limited to the DDR, and this application is also applicable to different storage media such as a RAM for multi-port access, a flash memory (FLASH), and a high bandwidth memory (English: High Bandwidth Memory, HBM for short).
Further, an embodiment of this application further provides a computer-readable storage medium, where the computer-readable storage medium stores computer instructions, and when the computer instructions run on a computer, the computer is enabled to perform the steps of any one of the foregoing methods.
Persons of ordinary skill in the art can understand that all or some of the steps of the method embodiments may be implemented by a program instructing related hardware. The program may be stored in a computer-readable storage medium. When the program is executed, the steps of the method embodiments are performed. The storage medium includes any medium that can store program code, for example, a ROM, a RAM, a magnetic disk, or an optical disc.
Although the foregoing describes specific embodiments of this application, persons skilled in the art should understand that these embodiments are merely examples, and the protection scope of this application is limited by the appended claims. Persons skilled in the art may make various changes or modifications to these embodiments without departing from the principle and the essence of this application, and these changes and modifications fall within the protection scope of this application. Although example embodiments of this application have been described, persons skilled in the art can make additional changes and modifications to these embodiments once they learn the basic inventive concept. Therefore, the appended claims are intended to be construed as including the example embodiments and all changes and modifications that fall within the scope of this application.
Clearly, persons skilled in the art can make various modifications and variations to this application without departing from the scope of this application. This application is intended to cover these modifications and variations of this application provided that they fall within the scope of the claims of this application and equivalent technologies thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210351147.X | Apr 2022 | CN | national |
This application is a continuation of International Patent Application No. PCT/CN2023/085545 filed on Mar. 31, 2023, which claims priority to Chinese patent application No. 202210351147.X, filed with the China National Intellectual Property Administration on Apr. 2, 2022, and entitled “TABLE ENTRY READING METHOD AND APPARATUS, AND NETWORK DEVICE”, both of which are incorporated herein by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2023/085545 | Mar 2023 | WO |
| Child | 18431046 | US |
