Tamper resistant device

Information

  • Patent Grant
  • 11087301
  • Patent Number
    11,087,301
  • Date Filed
    Tuesday, December 19, 2017
    6 years ago
  • Date Issued
    Tuesday, August 10, 2021
    2 years ago
Abstract
Aspects of the technology provide systems, devices and methods for filling design voids within an assembled electronic device with tamper solids in order to prevent and/or detect a tampering with the electronic device to gain unauthorized access to the electronic device to steal information.
Description
BACKGROUND
1. Technical Field

The subject application relates to detection of tampering with a device having circuitry configured to receive personal information from other devices for purposes of conducting a financial transaction.


2. Introduction

A point of sale (“POS”) device can include various components, such as a processor, a card reader, a network connection interface, and a receipt printer. Another variation of such POS device can include a handheld device (e.g., a mobile phone, a tablet, a laptop, etc.) coupled to a card reader (typically via an audio jack of the handheld device and/or a receipt printer. Card readers are typically built to read transaction information from cards, such as credit cards or debit cards.


When such POS devices are assembled, it is common that the resulting assembly would have air-filled voids in between the components (e.g., various circuitry) inside the assembly. For example, a card reader assembly would have various components such as a microcontroller, a wake-up circuit, an near field communication (NFC) reader, etc., installed on a printed circuit board and one or more areas between such components and the housing of the card reader can be air-filled/void.


Such air-filled portions/areas present a chance to hackers to insert bugs therein to turn the device into a skimmer and obtain financial/personal information of customers.





BRIEF DESCRIPTION OF THE DRAWINGS

Certain features of the subject technology are set forth in the appended claims. However, the accompanying drawings, which are included to provide further understanding, illustrate disclosed aspects and together with the description serve to explain the principles of the subject technology. In the drawings:



FIG. 1 illustrates architecture of a payment communication system, according to an aspect of the present disclosure;



FIG. 2 illustrates a payment object reader/transmitter device, according to an aspect of the present disclosure;



FIG. 3 illustrates components a payment object reader, according to an aspect of the present disclosure;



FIG. 4 illustrates a configuration of a security housing around a PCB, according to an aspect of the present disclosure;



FIG. 5A illustrates a placement of a PCB inside a security housing, according to an aspect of the present disclosure;



FIG. 5B illustrates a cross section of a security housing with a PCB placed therein, according to an aspect of the present disclosure;



FIG. 6 is an example of a tamper solid for filling design voids, according to an aspect of the present disclosure;



FIG. 7A illustrates a transparent view of a security housing with a tamper solid installed therein for filling design voids, according to an aspect of the present disclosure;



FIG. 7B illustrates a cross section of a security housing with a tamper solid installed therein, according to an aspect of the present disclosure;



FIG. 7C illustrates an example of filling design voids with inter material, according to an aspect of the present disclosure



FIG. 8 illustrates a process of detecting a tampering event, according to an aspect of the present disclosure; and



FIG. 9 illustrates an example computing system to implement the POS device of FIG. 1 and/or FIGS. 4 and 5, according to an aspect of the present disclosure.





DETAILED DESCRIPTION

The detailed description set forth below is intended as a description of various configurations of the subject technology and is not intended to represent the only configurations in which the technology can be practiced. The appended drawings are incorporated herein and constitute a part of the detailed description, which includes specific details for the purpose of providing a more thorough understanding of the subject technology. However, it will be clear and apparent that the subject technology is not limited to the specific details set forth herein and may be practiced without these specific details. In some instances, structures and components are shown in block diagram form in order to avoid obscuring the concepts of the subject technology.


As described above, assembled POS devices and components thereof are susceptible to malicious surveillance in an attempt to extract sensitive user information such as transaction card information, passwords, and personal identification numbers (“PINs”).


The subject technology relates to reducing and/or eliminating air-filled gaps (which may be referred to as design voids) such that any attempted tampering with such POS devices and/or any one of components thereof (e.g., a card reader) by inserting a malicious instrument into a design void can be detected and prevented.


Hereinafter, several embodiments of POS devices and systems they are used in will be described with reference to FIGS. 1 and 2. Thereafter, examples for reducing and/or eliminating vulnerabilities from design voids will be described with reference to FIGS. 3-8. Lastly, FIG. 9 and the accompanying description provide a description of system components that be implemented as a POS device. We now turn to the discussion of example POS devices and systems.



FIG. 1 illustrates architecture of a payment communication system, according to an aspect of the present disclosure. More specifically, FIG. 1 illustrates example architecture of payment communication system 100 for enabling point-of-sale (POS) transactions between merchants 122 and buyers 126. In the example of FIG. 1, buyer 126 can use any of a variety of payment objects, such as payment cards 130, 132, user device 128 or cash 134 when participating in POS transaction 124 with a merchant 122. A buyer 126 can typically have payment cards 130, 132 such as credit cards, debit cards, prepaid cards, and the like, that buyer 126 can use for conducting POS transaction 124. In some embodiments, payment cards 130 can include one or more magnetic stripes for providing payment object and buyer information when swiped in a payment object reader 120 communicatively coupled to merchant device 116. In some embodiments, other types of payment objects can be used, for example smart cards 132 having a built in integrated circuit including a memory chip (e.g. EMV payment objects), a radio frequency identification tag (e.g. near field communication enabled objects), and the like. In some embodiments, user 126 can use user device 128 (e.g., a mobile device, a tablet, etc.) to conduct NFC payment transactions through communication between the user device 128 and the payment object reader/transmitter device 120.


The payment communication system 100 in the example of FIG. 1 illustrates a merchant device 116 associated with the merchant 122 that participates in the payment service provided by the service provider of payment processing system 102. The merchant device 116 can be a computing device (e.g., a mobile computing device) able to communicate with the payment processing system 102, and with various other computing devices, through suitable communication protocols, interfaces, and networks, including network 114. Further, the merchant device 106 can be any appropriate device operable to send and receive requests, messages, or other types of information over the network 114. Additionally, while only a single merchant device 116 is illustrated in the example of FIG. 1, in some embodiments there can be additional merchant devices depending on the number of merchants participating in the payment service, or a plurality of components arranged as a POS system.


Merchant device 116 can include an instance of a merchant application 118 executed on merchant device 116. Merchant application 118 can provide POS functionality to enable the merchant 122 to accept payments at a POS location using merchant device 116. In some types of businesses, the POS location can correspond to a store or other place of business of the merchant, and thus, can be a fixed location that typically does not change on a day-to-day basis. In other types of businesses, however, the POS location can change from time to time, such as in the case that merchant 122 operates a food truck, is a street vendor, a cab driver, or has an otherwise mobile business, e.g., in the case of merchants who sell items at buyers' homes, buyers' places of business, etc.


Merchant device 116 is communicatively coupled to a payment object reader 120, either by direct connection, for example through an audio jack of the mobile phone connected to an audio plug of the payment object reader 120, or through wireless connection, such as WiFi, BlueTooth, BLE (Bluetooth low energy), NFC, or other appropriate short-range communication. Short-range communication as used herein refers to communication protocols having a generally short range of communication (less than 100 meters in some embodiments), such as NFC communication, RFID (radio frequency identification) tags, or Wi-Fi, etc. The payment object reader can read data from a magnetic stripe card or an EMV chip-type card and communicate the data to merchant device 116. The payment object reader can also read data from an NFC device and communicate the data to merchant device 116.


As used herein, a financial transaction is a transaction that is conducted between a customer and a merchant at a point-of-sale. When paying for a financial transaction, the customer can provide the merchant with cash, a check, or a debit or credit card for the amount that is due. The merchant can interact with a point-of-sale device, e.g., merchant device, to process the financial transaction. During financial transactions, the point-of-sale device can collect data describing the financial transaction, including, for example, the amount of payment received from customers.


Accordingly, merchant 122 and buyer 126 can conduct a POS transaction 124 by which buyer 126 acquires an item or service from merchant 122 at a POS location. The merchant application 118 on merchant device 116 can send transaction information to payment processing system 102, e.g., as the transaction is being conducted at the POS location. In some embodiments, such as if a particular merchant device 116 is not connected to the network 114 and is therefore processing transactions offline, the transaction information can be sent in a batch at a subsequent point in time or using other suitable techniques. In some embodiments, the transaction information can be sent via SMS, MMS, or a voice call.


In some examples, payment processing system 102 is configured to send and receive data to and from the user device and merchant device 116. For example, the payment processing system 102 can be configured to send data describing merchants to the user device using, for example, the information stored in the merchant account information database 106. The data describing merchants can include, for example, a merchant name, geographic location, contact information, and an electronic catalogue, e.g., a menu that describes items that are available for purchase from the merchant.


In some examples, payment processing system 102 can also be configured to communicate with a computer system of card payment network 112, e.g., MasterCard®, VISA®, etc., over the network, or over a different network, for example, to conduct electronic financial transactions. The computer system of the card payment network can communicate with a computer system of financial institution system 110, e.g., a bank. There can be computer systems of other entities, e.g., the card acquirer, between payment processing system 102 and the computer system of the card issuer.


Payment processing system 102 can then communicate with the computer system of a card payment network 112 to complete an electronic financial transaction for the total amount to be billed to the customer's financial account. Once the electronic financial transaction is complete, payment processing system 102 can communicate data describing the payment transaction to the user device, e.g., an electronic receipt, which can, for example, notify the customer of the total amount billed to the user for the payment transaction with the particular merchant.


In some examples, payment processing system 102 can also include payment card profiles stored with user accounts in user information database 104. Such payment card profile can be utilized for card-less payment transactions wherein a user 122 is not required to present a payment card, and instead can authorize the payment processing system to process a payment to a merchant using a device such as device 128.


To accept electronic payments using the POS system 100, the merchant 122 typically creates a merchant account with payment processing system 102 by providing information describing the merchant including, for example, merchant name, contact information (e.g., telephone numbers, the merchant's address, and one or more financial accounts to which funds collected from buyers will be deposited). This merchant information can be securely stored by payment processing system 102, for example, as merchant account information 106 in a secure database. Further, the merchant information can include a merchant profile created for each merchant. The merchant profile can include information about merchant 122 and transaction information associated with transactions conducted by the merchant.


Payment processing system 102 enables a service provider to provide a payment service in which merchants 122 are able to conduct POS transactions 124 with a plurality of buyers 126, such as for selling services and/or products to the buyers 126. The payment processing system 102 can include one or more servers that are configured to process secure electronic financial transactions, e.g., payment during a POS transaction 124, by communicating with the merchant device 116, card payment networks 112, and bank or other financial institution payment systems 110. Payment processing system 102 includes payment processing module 108 that receives transaction information for processing payments made through merchant application 118. For example, the payment processing module 108 can receive transaction information, such as an amount of the transaction, and can verify that particular payment card 130, 132 can be used to pay for the transaction, such as by contacting a card clearinghouse of card payment network 112. Furthermore, in some examples, payment processing module 108 can redirect payment information for transactions to be made using payment cards 130, 132 to a bank, or other financial institution system 110. In other embodiments, merchant device 116 can communicate directly with an appropriate card payment network 112 or financial institution system 110 for approving or denying a transaction using a particular payment card 130, 132 for a POS transaction 124.


Network 114 can be a conventional type, wired or wireless, and can have numerous different configurations including a star configuration, token ring configuration, or other configurations. Furthermore, network 114 can include an intranet, a local area network (LAN), a wide area network (WAN) (e.g., the Internet), and/or other interconnected data paths across which multiple devices can communicate. In some embodiments, network 114 can be a peer-to-peer network. Network 114 can also be coupled with or include portions of a telecommunications network for sending data using a variety of different communication protocols. In some embodiments, network 114 can include Bluetooth (or Bluetooth low energy) communication networks or a cellular communications network for sending and receiving data including via short messaging service (SMS), multimedia messaging service (MMS), hypertext transfer protocol (HTTP), direct data connection, WAP, email, etc. Although the example of FIG. 1 illustrates one network 114 coupled to the merchant device, payment processing system, card payment network, and bank, more than one network 114 can connect these entities. The payment system, the merchant device, and the user device can communicate over the network using wired or wireless connections, or combinations thereof.


In some examples, payment processing system 102 is configured to accept card-less payment transactions from customers (e.g. customer 126). As used herein, a card-less payment transaction is a transaction conducted between the customer and a merchant at the point-of-sale during which a financial account of the customer is charged without the customer having to physically present a financial payment card to the merchant at the point-of-sale. In some forms of card-less payment transactions, the merchant receives at the point-of-sale details of the financial account via mobile device 128 presenting payment information to merchant 122 by communicating with payment object reader 120, e.g. NFC transactions. In other forms of card-less payment transactions, the merchant need not receive any details about the financial account at the point-of-sale, e.g., the credit card issuer or credit card number, for the transaction to be processed. Instead, such details can be stored at user information 104 of payment processing system 102 and provided to merchant 122 (such card-less payment transactions herein are referred to as card-on-file transactions). Generally, when a customer and a merchant enter into an electronic financial transaction, the transaction is processed by transferring funds from a financial account associated with the user account to a financial account associated with the merchant account.



FIG. 2 illustrates a payment object reader/transmitter device, according to an aspect of the present disclosure. Payment object reader 200 can be the same as payment object reader 120 of FIG. 1. Payment object reader 200 can include microcontroller 202 configured to manage functions between various components within the payment object reader 200. Coupled to microcontroller 202 is integrated circuit payment object interface 204. Integrated circuit payment object interface 204 is connected to payment object detect switch 206 and payment object contacts 208. Payment object contacts 208 is configured to provide electrical connectivity between the contact pads of an integrated circuit enabled payment object and integrated circuit payment object interface 204. Furthermore, payment object detect switch 206 is configured to indicate when a payment object is inserted into payment object reader 200. Payment object detect switch 206 may be any suitable switch, electrical, mechanical, or otherwise, and in some embodiments may be integrated with payment object contacts 208. In situations where payment object detect switch 206 indicates that a payment object has been inserted into payment object reader 200, integrated circuit payment object interface 204 creates a pathway between microcontroller 202 and payment object contacts 208. As such microcontroller 202 can read data from the payment object contacting payment object contacts 208.


In some examples, microcontroller 202 transmits the data read from the payment object contacting payment object contacts 208, by using the NFC antenna 218 under the control of the NFC microcontroller 210.


Payment device 200 may also include a near field communication (NFC) microcontroller 210. NFC microcontroller 210 is configured to manage the transmission and reception of near field communications through control of driving circuit 212, NFC modulator 214, NFC RX module 216, NFC antenna monitoring circuit 217, and NFC antenna 218. In some embodiments, driving circuit 212 may include an H-bridge, an amplifier, a filter and/or a matching circuit. A switch 213 can be coupled on a first pole of the switch to the antenna 218 and on the second pole to the driving circuit, such that when the device is in the first receiver mode, the switch 213 is closed and the antenna is driven by the driving circuit. When switch 213 is open, the antenna 218 is not driven by driving circuit 212 and operates in a transmission mode. In some embodiments, switch 213 can be replaced with a switch within driving circuit 212, such as a JFET or MOSFET switch under the control of the microcontroller 202 or NFC microcontroller 210. Furthermore, in some embodiments NFC RX module 216 may include an op-amp, a filtering and conditioning circuit and/or a rectifier, such as a full wave bridge rectifier. Additionally, NFC modulator 214 may be, for example, a type-B modulator. In instances where it is desired to read a NFC enabled payment object, or a NFC enabled payment object is determined to be in proximity to payment object reader 200, NFC microcontroller 210 may be configured to drive NFC antenna 218 via driving circuit 212 to induce a magnetic field capable of being modulated by the NFC enabled payment object. From here, the modulated magnetic field signal may be converted into a digital signal that NFC microcontroller 210 can interpret via NFC RX module 216. On the other hand, when it is desired to transmit data via NFC antenna 218, NFC microcontroller 210 may be configured to disable driving circuit 212 and transmit data using the NFC protocol by instructing NFC modulator 214 to modulate the magnetic field to which NFC antenna 218 is operatively coupled. In some embodiments, there can be a switch within NFC modulator 214 to turn on or off the load applied to the antenna. The switch can be under the control of microcontroller 202.


Microcontroller 202 receives payment data read by integrated circuit payment object interface 204 via payment object contacts 208, or alternatively from a magnetic stripe reader reading payment data from a magnetic stripe card. The payment data received at microcontroller 202 is stored, either temporarily or permanently, in memory of payment device 200. The payment data stored in memory can then be transmitted via NFC antenna 218. In some embodiments, microcontroller 202 can receive and permanently store payment information so that payment object reader 200 acts as a payment object that does not require a payment card or other payment object to be present. Payment device 200 is capable of communicating using Bluetooth, and is thus able to pair with a mobile device to obtain payment object information from a phone that has Bluetooth capabilities but does not have NFC payment capabilities.


To supply power to the components within payment device 200, power system 226 is provided. In some embodiments, power system 226 may include a battery. Coupled to power system 226 is USB micro interface 228 configured to receive a USB micro jack, although other types of connectors may be utilized. In certain embodiments, connection of a jack to USB micro interface 228 can activate a switch within power system 226 to override power supplied by the battery. This allows for battery power to be conserved for situations where external power cannot be provided. Furthermore, power system 226 may also include a battery charger to allow the battery to be charged when external power is supplied via USB micro interface 228. Payment device 200 also includes wake-up electronics 230 configured to wake-up payment object reader 200 from a low-power state to an active state in response to detection of a payment object. In some embodiments, wake-up electronics 230 can also power down payment object reader 200 to a low-power state after a predetermined amount of time or after completion of a communication.


Payment device 200 illustrated in FIG. 2 further contains a Bluetooth low energy (BLE) interface 222 and a BLE antenna 224 to enable Bluetooth communications. In addition, payment object reader 200 includes anti-tamper module 220 configured to prevent unauthorized tampering with the device and possible theft or interception of payment information. In certain embodiments, anti-tamper module may include a wire mesh enclosed within payment object reader 200, as will be described below.


Payment device 200 also includes user interfaces 232 to enhance the user experience. User interfaces 232 can include, but are not limited to, LED indicators, buttons and speakers. In some embodiments, speakers and LED indicators can be used to present audio and visual identifiers of transaction and device status. In addition, buttons may be configured to power payment object reader 200 on or off, operate the device or reset the device.


Payment object reader 200 also includes sensors. As illustrated in FIG. 2, the example sensors are useful in informing payment object reader 200 about its current environment, use, or state such as accelerometer 236 and proximity detector 234



FIG. 3 illustrates components a payment object reader, according to an aspect of the present disclosure.


As shown in FIG. 3, payment object reader 200 includes at least a housing 302 having a slot 304, a card reader 306 embedded on a wall of slot 304, a signal plug 308 extending out from housing 302, and a printed circuit board (PCB) 310. In one example, payment object reader 200 connects to merchant device 116 via signal plug 314.


In one example, slot 304 has lips (edges) 312 and 314 and there may be opening 316 between PCB 306 and lower lip 312. Slot 304 is configured to maintain contact between card reader 306 (which may also be a magnetic read head, NFC chip, etc., as described above) and the magnetic stripe of the financial transaction card (e.g., card 132 shown in FIG. 1) during a swipe. A signal resulting (generated) from the contact is sent to electronic components installed on PCB 310 for processing and transmission to merchant device 116 for decoding, processing, etc., as described above. In one example, slot 304 has a width of no greater than 1 mm. The width of slot 304 is sufficient to enable a successful swiping of the financial transaction card, while producing the signal. It is sized to enable the successful swipe without creating sufficient torque between signal plug 308 or output jack and the read head or at the merchant device 116 to cause damage due to excessive torque.


PCB 310 can have electronic components of payment object reader 200 installed thereon including but not limited to, microcontroller 202, integrated circuit payment object interface 204, NFC microcontroller 210, wake-up electronics 230, etc., as described above with reference to FIG. 2. As shown in FIG. 2, there is a security housing 320 within housing 302 that covers PCB 310. This will be further illustrated and described with reference to FIGS. 4-8. Inclusion of security housing 320 is optional. In one example, there can be no security cage and instead PCB 310 sits within housing 302 and connected to card reader 206.


Furthermore, FIG. 3 illustrates empty space 318 (shown using diagonal lines). As discussed above, design voids can be used to place malicious instruments in payment object reader 200 for purposes of stealing personal and financial information of customers and merchants. Empty space 318 and opening 316 represent examples of such design voids. Furthermore and as will be described below with reference to FIGS. 4-8, there can be design voids between security housing 320 and PCB 310 placed therein.


Having described various examples of POS devices and components thereof as well as systems in which they are used, we now turn to a discussion of addressing air-filled spaces (design voids) inside such POS devices, payment object readers, etc.


Referring back to FIG. 3, design voids such as empty space 318 and opening 316 can be created between card reader 306, PCB 310 and housing 302, once payment object reader 200 is assembled.


It is possible for a scammer to utilize these design voids to insert bugs/malicious instruments into payment object reader 200 (e.g., by drilling through housing 302, disassembling (opening) housing 302, etc.). As is known, a bug may be used to tap signals to steal unencrypted information (e.g., personal and financial information of customers) off of signals generated as a result of detecting a payment object such as a credit card, detection of a customer device via NFC antenna 218, etc.


Typically, design voids having a 5 mm×10 mm×10 mm dimension or bigger, can be used to insert “off the shelf” bugs inside payment object reader 200. However, for utilizing design voids with lower dimension, custom made bugs need to be built and used, which adds complexity and reduces scalability of such scheme to insert bugs in hundreds or thousands of such payment objects readers.



FIG. 4 illustrates a configuration of a security housing around a PCB, according to an aspect of the present disclosure.


As shown in FIG. 4, example security housing 320 has a top portion 405, a bottom portion 410, side portions 415, a back portion (not shown) and a cap 420. In one example, PCB 310 fits within security housing 320 and connected thereto via connector pieces 425. As shown in FIG. 3, PCB 310 can have one or more electronic components 430, such as various components of payment object reader 200 described above with reference to FIG. 2, installed thereon.


Security housing 320 can have tamper mesh traces running through inner surfaces thereof (e.g., in a zigzag or boustrophedonic pattern, for example), which can in turn be connected to a tamper detection circuit on PCB 310, via connectors 425) for detecting any physical tampering therewith (e.g., drilling through security housing 320, by attempting to reroute current within the tamper detection circuit, or by flooding a portion of the tamper detection circuit with conductive ink). Operations of tamper mesh traces and tamper detection circuit are further described in U.S. application Ser. No. 15/250,460 filed on Aug. 29, 2016, the entire content of which is incorporated herein by reference.


Security housing 320 can also be referred to as a tamper cage, a security cage, or simply a shell. Security housing 320 can have non-conductive portions made from plastic, such as thermoplastics manufactured using Laser Direct Structuring (LDS), or from other non-conductive materials. The non-conductive portions of security housing 320 can be fused to each other and/or to the non-conductive board of the PCB 310 to prevent opening the security housing, or can alternately be affixed with glue, cement, or other adhesives. The non-conductive portions of PCB 310 are typically hard but can in some cases have a degree of flexibility. Tamper traces (not shown), which are used in conjunction with tamper detection circuit (not shown but can be anti-tamper module 220 of FIG. 2) can be laid out over the inside surfaces of top portion 405, bottom portion 410 and/or side portions 415 of security housing 320 during an LDS manufacturing process, if LDS is used.



FIG. 5A illustrates a placement of a PCB inside a security housing, according to an aspect of the present disclosure. FIG. 5 illustrates a transparent view of security housing 320 once PCB 310 is inserted therein and connected to PCB 320 via connectors 425. FIG. 5B illustrates a cross section of a security housing with a PCB placed therein, according to an aspect of the present disclosure. The illustrated cross section of FIG. 5B is along a width of security housing 320 of FIG. 5A from one side portion 415 to the opposite side portion 415.


As can be seen from FIG. 5B, once PCB 310 is placed inside security housing 320, there are design voids between the inner sides of security housing 320 and the PCB 310, connectors 425 and components 430 installed on PCB 310. In FIG. 5B, these design voids are illustrated as spaces 500 using diagonal dash lines.


In FIGS. 5A and B, PCB 310 is shown as being placed in a middle of the empty space inside security housing 320. However, the present disclosure is not limited to such placement of PCB 310 in the middle of the empty space inside security housing 320 but, for example, can be placed such that OCB 310 sits directly on top of the inner surface of bottom portion 410 of security housing 320. Furthermore, PCB 310 can be wide enough such that when it is placed inside security housing 320, the width thereof substantially covers the width of security housing 320 from one side portion 415 to another.


While through FIGS. 5A-B some examples of design voids and how they are created are shown, design voids within payment object reader 200 are not limited thereto. For example, design voids can be created between the outer walls of security housing 320 and the housing 302 to create design voids such as empty spaces 318 shown in FIG. 3. Another example of a design void is the opening 316 shown in FIG. 3.


As described herein, one objective of the present disclosure is to reduce and/or eliminate these design voids within payment object reader 200. While payment object reader 200 is used as an example of an assembly with design voids, the present disclosure is not limited thereto. In other words, any other device or component of a POS system that receives sensitive financial and personal information of customers and merchants and is susceptible to insertion of bugs to steal such information can be modified according to examples described hereinafter in order to reduce and/or eliminate any air-filled spaces therein. Furthermore, the present disclosure is equally applicable to any other device that has a security housing with design voids created therein after respective components are installed therein, including but not limited to, access card readers, electronic ignition systems, laptops, handheld devices, mobile phones, computers, medical equipment, security cameras, Automated Teller Machines (ATMs), electrical power grid sensors, oil rig sensors, etc.


Several examples will be described hereinafter according to which design voids can be eliminated and/or reduced to be at least smaller than a 5 mm×10 mm×10 mm, if not substantially eliminated.


In one example, design voids can be partially and/or completely filled with what is referred to as tamper solids. There can be different forms of tamper solids such as an electrical circuit, inert material such as plastic, glue, various types of potting material including semiconductive potting material, etc., all of which will be described below.



FIG. 6 is an example of a tamper solid for filling design voids, according to an aspect of the present disclosure.


As shown in FIG. 6, structure 600 can be a 3-dimensional structure comprising a series (and/or alternatively parallel) connection of resistors 605. In one example, each resistor 605 can have a resistance value of zero or a non-zero value. In one example, a zero value (zero ohm) resistor refers to any resistor or any electronic component having a resistant that is near zero and less than a threshold (e.g., any resistor or any electronic component having a resistance of less than 50 milliohms (mΩ)). FIG. 6 is just one example of a configuration/structure of a 3-dimensional tamper solid. However, any other type of structure or configuration of electrical components can be used as tamper solids (e.g., a two or three dimensional configuration of resistors, capacitors, inductors, conductors, etc.).



FIG. 7A illustrates a transparent view of a security housing with a tamper solid installed therein for filling design voids, according to an aspect of the present disclosure. As shown in FIG. 7A, PCB 310 (having components 430 installed thereon) is placed inside security housing 320. Furthermore, through a transparent view, via top portion 405 of security housing 320, it is shown that tamper solid 600 of FIG. 6 is installed on PCB 310 and protrudes therefrom toward top portion 405 of security housing 320. Tamper solid 600 can be connected to a tamper detection circuit (e.g., anti-tamper module 220 of FIG. 2) on PCB 310. Such circuitry, can be configured to detect a known voltage across tamper solid 600 and therefore, in case one of resistors 605 are broken due to a physical tampering (e.g., breaking into security housing 320), a change in the known voltage (or a short circuit) would be detected resulting in a detection of tampering and triggering a process for disabling payment object reader 200 (e.g., wiping its encryption keys, etc.).


While in FIG. 7A, only one tamper solid 600 is shown as being installed in a design void between two components 430 and top portion 405, one or more additional tamper solids (of exact same size or similar size depending on dimension of each design void) can be installed in other design voids inside security housing 320.



FIG. 7B illustrates a cross section of a security housing with a tamper solid installed therein, according to an aspect of the present disclosure. FIG. 7B illustrates the same structure as FIG. 5B described above with the exception that in FIG. 7B, three example tamper solids are installed on PCB 310 for filling design voids created between two connectors 425, PCB 310, component 430 and top portion of security housing 320. Three tamper solids are the same as tamper solid example 600 having a 3-dimensional structure. However, because FIG. 7B is a cross sectional view of FIG. 7A, tamper solids 600 are shown as two dimensional structures with two side resistors 605.


Comparing FIGS. 5B and 7B, one can readily see that the design void between connectors 425, PCB 310, component 430 and top portion 405 of security housing 320 is partially filled with tamper solids 600 in FIG. 7B such that at least no space large enough (e.g., larger than 5 mm×10 mm×10 mm) is left as a void.


In one example, instead of tamper solid structures 600, unitary resistors 605 can each be considered a tamper solid and individually (and vertically) installed between top portion 405 and PCB 310 and be connected to a tamper detection circuit, in a similar manner as described above.


While in FIGS. 7A and 7B only certain design voids are shown as being filled with tamper solids, other design voids (e.g., design void between PCB 310 and bottom portion 410 of security housing 320 or between sides of PCB 310 and side portions 415 of security housing 320) can similarly have tamper solids installed therein to reduce the size of such design voids.


In another example, instead of a three dimensional structure of tamper solid 600 of FIG. 6, there may be a series of electrical components such as resistors that run through design voids inside security housing 320 (e.g., horizontally or vertically). These electrical components (e.g., resistors) create a net of interconnected electrical components such that if a physical tampering attempt is made to break into security housing 320 to access electrical components on PCB 310 and/or to install bugs, it would have to break one or more of such nested network of electrical components, which would trigger a detection of a tampering event and result in disabling of payment object reader 200 and/or corresponding POS device.


As mentioned above, in addition to design voids described with reference to FIGS. 5A-B and 7A-B, there can be design voids between security housing 320 and housing 302 of payment object reader 200 or within the opening 316 of FIG. 3. Tamper solids such as tamper solid 600 can be installed therein and connected to one or more conducting points on outer surfaces of security housing 320, which would in turn allow the tamper solids to be connected to tamper detection circuit (e.g., anti-tamper module 220 of FIG. 2) on PCB 310 for controlling thereof and detection of a physical tampering with payment object reader 200.


As briefly mentioned above, other examples of tamper solids include inert material that can also be used to fill design voids. Such inter material can include, but is not limited to, plastics, glues and/or any known or to be developed potting material. In one example, such inert material upon dispensing thereof, expands and becomes rigid so as to completely or partially occupy the design voids. Such inert material does not interfere with operation of electrical components of payment object reader on PCB 310.



FIG. 7C illustrates an example of filling design voids with inter material, according to an aspect of the present disclosure. FIG. 7C is the same structure as that shown in FIG. 5B and described above with the exception of design voids 500 being filled with inert material 700. Inert material 700 can partially, substantially and/or completely fill design voids 500. In FIG. 7C inert material 700 are shown to have substantially covered design voids 500 for ease of illustration.


In one example, in addition to design voids 500 inside security housing 320 shown in FIG. 5B, design voids between security housing 320 and housing 302 and/or opening 316 can also be filled with inert material 700.


As described above, inert material 700 can be plastic, glue or potting material. In one example, potting material can be semiconductive potting material such as RTV silicone.


In one example, one or more capacitors can be placed on each end of PCB 310 (or at multiple points across PCB 310) to measure capacitance across semiconductive potting material 700 such as RTV silicone, such that if a physical tampering is detected, capacitance thereof is changed and such change is detected by tamper detection circuit (e.g., anti-tamper module 220 of FIG. 2) on PCB 310. In one example, as a number of such capacitors and placement thereof on PCB 310 is increased, it is possible to better determine (better pinpoint) the location of tampering (e.g., drilling location) within security housing 320 and more generally within payment object reader 200.


In this context, a physical tampering would be a physical alteration of semiconductive potting material deposited within design voids (e.g., chipping away at semiconductive potting material) to make room for inserting a bug.


On example advantage of filling design voids with potting material is that it results in the entire structure of payment object reader 200 to be more rigid and less susceptible to fluctuations in humidity, temperature, etc. Such rigidness also reduces the risk of damaging (physical damage) payment object reader 200 in case of, for example, dropping payment object reader 200, stepping on payment object reader 200, etc.


In one example, during the processing of manufacturing PCB 310, empty spaces or design voids can be filled with tamper meshes etched thereon. For example, on various locations on PCB 310 above which, after installment inside security housing 320, design voids are created, three-dimensional structures such as tamper meshes (e.g., cubic shaped structures) can be etched so as to reduce/eliminate such design voids and/or provide a tamper detecting element that detects tampering with payment object reader 200 upon drilling into security housing 320.


In each of the examples described above, security housing 320 is provided that covers PCB 310 and its components completely and serves as an additional cover (an intermediate cover) between PCB 310 and housing 302.


In another example, housing 320 can be such that instead of completely covering PCB 310 (all around) it can be a “half structure” such that security housing 320 covers the top surface of PCB 310 and design voids are created therein. In this case, security housing 320 no longer has a bottom portion 410 and PCB 310 serves as the bottom of an assembly that includes PCB 310, components 430 and “half structure” 310 covering the same on top. Various design voids and filling thereof using tamper solids and inter material as described above with reference to FIGS. 5A-7C, are equally applicable to such “half structure” 320 covering PCB 310 inside housing 302.


In another example, security housing 320 can be removed and PCB 310 and its components can be placed inside housing 302 with design voids being created between inner walls of housing 302 and PCB 310. Various design voids and filling thereof using tamper solids and inter material as described above with reference to FIGS. 5A-7C, are equally applicable to PCB 310 inside housing 302 without security cage 320.



FIG. 8 illustrates a process of detecting a tampering event, according to an aspect of the present disclosure. FIG. 8 will be described from the perspective of a microcontroller of a tamper detection circuit, which can be anti-tamper module 220 of FIG. 2. Anti-tamper module can be referred to as a controller 220 hereinafter. Alternatively, functionalities of anti-tamper module 220 can be incorporated (programmed) into microcontroller 202 and microcontroller 202 can perform the functions described below with reference to FIG. 8.


At S800, controller 220 performs a security scan of payment object reader 200. In one example, controller 220 performs the security scan at every predetermined interval (e.g., once every few minutes, once every hour, once every 24 hours, etc.).


In one example such security scan can be measurement of a voltage across gap-filling circuitry as described above. In another example, the security scan can be a measurement of resistance across the gap-filling circuitry placed in design voids, as described above. In this example, upon detecting a resistance value that deviates from a threshold (pre-set or known) resistance value, an indication of tampering with the payment object reader 200 can be provided by controller 220. For example and as described above, tamper solid 600 can be a zero ohm structure, where each resistor 605 has a resistance value of zero and/or is a zero value (zero ohm) resistor/component, as defined above. Accordingly, detection of a non-zero resistance value (e.g., a large value or infinity indicating an open circuit (broken resistor)), can be indicative of tampering with payment object reader 200.


In another example, gap-filling circuitry can be a structure formed of one or more capacitors. Accordingly, a detection of tampering is based on a measurement of capacitance across the one or more capacitors and a comparison thereof with a threshold (pre-set or known) capacitance value. Alternatively, the measurement of capacitance can be across the semiconductive potting material as described above, etc.


In another example, gap-filling circuitry can be a structure formed of one or more inductors. Accordingly, a detection of tampering is based on a measurement of inductance of the one or more inductors (e.g., coils, etc.) and a comparison thereof with a threshold (pre-set or known) inductance value. Such inductance value can change if a coil is cut, deformed due to insertion of a bug or malicious circuit, etc.


In another example, gap-filling circuitry can be a structure formed of a combination of the above examples of gap-filling circuitry. For example, gap-filling circuitry can be a combination of one or more resistors, capacitors and/or coils and a detection of tampering can be based on a measurement of corresponding resistance, voltage, capacitance and/or inductance of the resistor(s), capacitor(s) and/or coil(s) of the gap-filling circuitry and comparison thereof to corresponding threshold(s).


Resistance, voltage, inductance and capacitance thresholds mentioned above, can be configurable parameters that can be set and/or adjusted based on experiments and/or empirical studies.


In another example, such security scan can be a continuous monitoring of one or more of voltage(s), resistance, inductance, and/or capacitance value(s), etc.


At S805, controller 220 determines if a tampering event is detected based on security scan performed at S800. For example, upon detecting a short circuit (e.g., due to a breaking of one or more resistors of tamper solid 600 described above), a change in voltage across resistors 605, capacitance across PCB 310, and/or resistance, inductance and capacitance values described above, controller 220 determines that payment object reader 200 has been tampered with. In one example, a change in voltage, inductance and/or capacitance is detected if such change deviates from a given voltage or capacitance value programmed into controller 220. As mentioned above, such short circuit, a break in the circuit, etc., may result from an attempt to physically intrude into payment object reader 200. Such intrusion may be attempted by a merchant or a customer engaging in a financial transaction using a POS device including payment object reader 200, another unauthorized agent attempting to plant a bug or a malware inside the POS device, etc.


As mentioned above, inert material can also be used to fill design voids, where such inert material can be different types of potting material such as plastic, glue, semiconductive potting material, etc. While measuring a change in a measured capacitance value of semiconductive potting material is described as a basis for detecting a tampering event by controller 220, in another example, there can be one or more optical receivers (e.g., one or more pinhole cameras) installed inside security housing 320 and/or 302. An optical receiver can scan the design voids or the potting material used for filling design voids, to detect any alteration and/or removal of parts (portions) and/or the entirety of the potting material. Detection of such alternation and/or removal of parts or entirety of potting material, results in controller 220 detecting a tampering event.


If at S805, controller 220 detects a tampering event, then at S810, controller 220 automatically self-destructs itself (disables payment object reader 200) so that payment object reader 220 (and more generally corresponding POS device such as mobile device 116) will become inoperable. While rendering payment object reader 200 inoperable is one example of disabling at S805, disabling also includes deleting encryption keys stored on payment object reader 200 for purposes of conducting transactions (e.g., financial transactions), rendering POS device incapable of processing transactions (e.g., financial transactions), etc. Thereafter, the process ends.


However, if at S805 and based on a result of the security scan, controller 220 determines that payment object reader 200 is not been tampered with, the process reverts back to S800 and controller 220 repeats S800 to S800 to S810 according a predetermined schedule of scans or on a continuous basis, as described above.


Many of the above-described features and applications are implemented as software processes that are specified as a set of instructions recorded on a computer readable storage medium (also referred to as computer readable medium). When these instructions are executed by one or more processing unit(s) (e.g., one or more processors, cores of processors, or other processing units), they cause the processing unit(s) to perform the actions indicated in the instructions. Examples of computer readable media include, but are not limited to, flash drives, RAM chips, hard drives, EPROMs, etc. The computer readable media does not include carrier waves and electronic signals passing wirelessly or over wired connections.


In this specification, the term “software” is meant to include firmware residing in a non-volatile memory or applications stored in magnetic/non-magnetic storage (e.g., flash and solid state storage devices, etc.), which can be read into memory for processing by a processor. Also, in some implementations, multiple software aspects of the subject disclosure can be implemented as sub-parts of a larger program while remaining distinct software aspects of the subject disclosure. In some implementations, multiple software aspects can also be implemented as separate programs. Finally, any combination of separate programs that together implement a software aspect described here is within the scope of the subject disclosure. In some implementations, the software programs, when installed to operate on one or more electronic systems, define one or more specific machine implementations that execute and perform the operations of the software programs.



FIG. 9 illustrates an example computing system to implement the POS device of FIG. 1, according to an aspect of the present disclosure. For example, any of the computer systems or computerized devices described herein may include at least one computing system 900, or may include at least one component of the computer system 900 identified in FIG. 9. The computing system 900 of FIG. 9 includes one or more processors 910 and memory 910. Main memory 920 stores, in part, instructions and data for execution by processor 910. Main memory 920 can store the executable code when in operation. The system 900 of FIG. 9 further includes a mass storage device 930, portable storage medium drive(s) 940, output devices 950, user input devices 960, a graphics display 970, and peripheral devices 980.


The components shown in FIG. 9 are depicted as being connected via a single bus 590. However, the components may be connected through one or more data transport means. For example, processor 910 and main memory 920 may be connected via a local microprocessor bus, and mass storage device 930, peripheral device(s) 980, portable storage device 940, and display system 970 may be connected via one or more input/output (I/O) buses.


Mass storage device 930, which may be implemented with a magnetic disk drive or an optical disk drive, is a non-volatile storage device for storing data and instructions for use by processor 910. Mass storage device 930 can store the system software for implementing embodiments of the present invention for purposes of loading that software into main memory 910.


Portable storage device 940 operates in conjunction with a portable non-volatile storage medium, such as a compact disk or Digital video disc, to input and output data and code to and from the computer system 900 of FIG. 9. The system software for implementing embodiments of the present invention may be stored on such a portable medium and input to the computer system 900 via the portable storage device 940.


Main memory 920, mass storage device 930, or portable storage 940 can in some cases store sensitive information, such as transaction information, health information, or cryptographic keys, and may in some cases encrypt or decrypt such information with the aid of the processor 910. Main memory 920, mass storage device 930, or portable storage 940 may in some cases store, at least in part, instructions, executable code, or other data for execution or processing by the processor 910.


Output devices 950 may include, for example, communication circuitry for outputting data through wired or wireless means, display circuitry for displaying data via a display screen, audio circuitry for outputting audio via headphones or a speaker, printer circuitry for printing data via a printer, or some combination thereof. The display screen may be any type of display discussed with respect to the display system 970. The printer may be inkjet, laser/toner based, thermal, or some combination thereof. In some cases, the output device circuitry 950 may allow for transmission of data over an audio jack/plug, a microphone jack/plug, a universal serial bus (USB) port/plug, an Apple® Lightning® port/plug, an Ethernet port/plug, a fiber optic port/plug, a proprietary wired port/plug, a BLUETOOTH® wireless signal transfer, a BLUETOOTH® low energy (BLE) wireless signal transfer, a radio-frequency identification (RFID) wireless signal transfer, near-field communications (NFC) wireless signal transfer, 802.11 Wi-Fi wireless signal transfer, cellular data network wireless signal transfer, a radio wave signal transfer, a microwave signal transfer, an infrared signal transfer, a visible light signal transfer, an ultraviolet signal transfer, a wireless signal transfer along the electromagnetic spectrum, or some combination thereof. Output devices 550 may include any ports, plugs, antennae, or any other components necessary for the communication types listed above, such as cellular Subscriber Identity Module (SIM) cards.


Input devices 960 may include circuitry providing a portion of a user interface. Input devices 960 may include an alpha-numeric keypad, such as a keyboard, for inputting alpha-numeric and other information, or a pointing device, such as a mouse, a trackball, stylus, or cursor direction keys. Input devices 960 may include touch-sensitive surfaces as well, either integrated with a display as in a touchscreen, or separate from a display as in a trackpad. Touch-sensitive surfaces may in some cases detect localized variable pressure or force detection. In some cases, the input device circuitry may allow for receipt of data over an audio jack, a microphone jack, a universal serial bus (USB) port/plug, an Apple® Lightning® port/plug, an Ethernet port/plug, a fiber optic port/plug, a proprietary wired port/plug, a BLUETOOTH® wireless signal transfer, a BLUETOOTH® low energy (BLE) wireless signal transfer, a radio-frequency identification (RFID) wireless signal transfer, near-field communications (NFC) wireless signal transfer, 802.11 Wi-Fi wireless signal transfer, cellular data network wireless signal transfer, a radio wave signal transfer, a microwave signal transfer, an infrared signal transfer, a visible light signal transfer, an ultraviolet signal transfer, a wireless signal transfer along the electromagnetic spectrum, or some combination thereof. Input devices 560 may include any ports, plugs, antennae, or any other components necessary for the communication types listed above, such as cellular SIM cards.


Display system 970 may include a liquid crystal display (LCD), a plasma display, an organic light-emitting diode (OLED) display, an electronic ink or “e-paper” display, a projector-based display, a holographic display, or another suitable display device. Display system 970 receives textual and graphical information, and processes the information for output to the display device. The display system 970 may include multiple-touch touchscreen input capabilities, such as capacitive touch detection, resistive touch detection, surface acoustic wave touch detection, or infrared touch detection. Such touchscreen input capabilities may or may not allow for variable pressure or force detection.


Peripherals 980 may include any type of computer support device to add additional functionality to the computer system. For example, peripheral device(s) 980 may include a modem, a router, an antenna, a printer, a bar code scanner, a quick-response (“QR”) code scanner, a document/image scanner, a visible light camera, a thermal/infrared camera, an ultraviolet-sensitive camera, a night vision camera, a light sensor, a battery, a power source, or some combination thereof.


The components contained in the computer system 900 of FIG. 9 are those typically found in computer systems that may be suitable for use with embodiments of the present invention and are intended to represent a broad category of such computer components that are well known in the art. Thus, the computer system 900 of FIG. 9 can be a personal computer, a hand held computing device, a telephone (“smart” or otherwise), a mobile computing device, a workstation, a server (on a server rack or otherwise), a minicomputer, a mainframe computer, a tablet computing device, a wearable device (such as a watch, a ring, a pair of glasses, or another type of jewelry/clothing/accessory), a video game console (portable or otherwise), an e-book reader, a media player device (portable or otherwise), a vehicle-based computer, some combination thereof, or any other computing device. The computer system 900 may in some cases be a virtual computer system executed by another computer system. The computer can also include different bus configurations, networked platforms, multi-processor platforms, etc. Various operating systems can be used including Unix, Linux, Windows, Macintosh OS, Palm OS, Android, iOS, and other suitable operating systems.


In some cases, the computer system 900 may be part of a multi-computer system that uses multiple computer systems 900, each for one or more specific tasks or purposes. For example, the multi-computer system may include multiple computer systems 900 communicatively coupled together via at least one of a personal area network (PAN), a local area network (LAN), a wireless local area network (WLAN), a municipal area network (MAN), a wide area network (WAN), or some combination thereof. The multi-computer system may further include multiple computer systems 500 from different networks communicatively coupled together via the internet (also known as a “distributed” system).


A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.


These functions described above can be implemented in digital electronic circuitry, in computer software, firmware or hardware. The techniques can be implemented using one or more computer program products. Programmable processors and computers can be included in or packaged as mobile devices. The processes and logic flows can be performed by one or more programmable processors and by one or more programmable logic circuitry. General and special purpose computing devices and storage devices can be interconnected through communication networks.


Some implementations include electronic components, such as microprocessors, storage and memory that store computer program instructions in a machine-readable or computer-readable medium (alternatively referred to as computer-readable storage media, machine-readable media, or machine-readable storage media). Some examples of such computer-readable media include RAM, ROM, flash memory (e.g., SD cards, mini-SD cards, micro-SD cards, etc.), magnetic and/or solid state hard drives, non-volatile memory, read-only and recordable Blu-Ray® discs, ultra density optical discs, any other optical or magnetic media. The computer-readable media can store a computer program that is executable by at least one processing unit, such as a microcontroller, and includes sets of instructions for performing various operations. Examples of computer programs or computer code include machine code, such as is produced by a compiler, and files including higher-level code that are executed by a computer, an electronic component, or a microprocessor using an interpreter.


While the above discussion primarily refers to microprocessor or multi-core processors that execute software, some implementations are performed by one or more integrated circuits, such as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). In some implementations, such integrated circuits execute instructions that are stored on the circuit itself.


As used in this specification and any claims of this application, the terms “computer”, “server”, “processor”, and “memory” all refer to electronic or other technological devices. These terms exclude people or groups of people. For the purposes of the specification, the terms display or displaying means displaying on an electronic device. As used in this specification and any claims of this application, the terms “computer readable medium” and “computer readable media” are entirely restricted to tangible, physical objects that store information in a form that is readable by a computer. These terms exclude any wireless signals, wired download signals, and any other ephemeral signals.


Examples of the subject matter described in this specification can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (“LAN”) and a wide area network (“WAN”), an inter-network (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks).


The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. In some embodiments, a server transmits data (e.g., an HTML page) to a client device (e.g., for purposes of displaying data to and receiving user input from a user interacting with the client device). Data generated at the client device (e.g., a result of the user interaction) can be received from the client device at the server.


It is understood that any specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged, or that all illustrated steps be performed. Some of the steps may be performed simultaneously. For example, in certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.


The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. Pronouns in the masculine (e.g., his) include the feminine and neuter gender (e.g., her and its) and vice versa. Headings and subheadings, if any, are used for convenience only and do not limit the subject disclosure.


A phrase such as an “aspect” does not imply that such aspect is essential to the subject technology or that such aspect applies to all configurations of the subject technology. A disclosure relating to an aspect may apply to all configurations, or one or more configurations. A phrase such as an aspect may refer to one or more aspects and vice versa. A phrase such as a “configuration” does not imply that such configuration is essential to the subject technology or that such configuration applies to all configurations of the subject technology. A disclosure relating to a configuration may apply to all configurations, or one or more configurations. A phrase such as a configuration may refer to one or more configurations and vice versa.

Claims
  • 1. A Point of Sale (POS) device used in performing a transaction between a merchant and a customer, the POS device configured to prevent a physical installation of unauthorized bugging devices within design voids of a housing of the POS device, the POS device comprising: the housing;a printed circuit board within the housing;electronic components installed on the printed circuit board and configured to enable processing of the transaction between the merchant and the customer;a tamper cage within the housing and configured as a barrier to prevent physical access to the electronic components on the printed circuit board;a design void between the tamper cage and the printed circuit board, wherein the design void is a volume not filled by an electronic component after installation of the electronic components;a tamper solid installed on the printed circuit board and filling the design void; anda controller configured to: detect penetration of the tamper cage adjacent to the design void or removal of the tamper solid filling the design void; anddisable operation of the POS device upon determining that a tampering event occurred, whereby POS device is no longer operational for performing the transaction, the tampering event being the penetration of the tamper cage or the removal of the tamper solid.
  • 2. The POS device of claim 1, wherein the tamper solid is a circuit having a plurality of electrical components placed in the design void.
  • 3. The POS device of claim 1, wherein the electrical components are resistors.
  • 4. The POS device of claim 1, wherein the tamper solid includes a tamper mesh trace connected to the printed circuit board.
  • 5. The POS device of claim 4, wherein the tampering event includes an installation of a bug on the printed circuit board to skim signals for data related to transaction conducted using the POS device.
  • 6. A payment object reader comprising: a housing;a payment reader configured to receive payment information from a payment object;a printed circuit board within the housing;electronic components installed on the printed circuit board and configured to enable processing of the payment information for completing a transaction between a merchant and a customer;at least one design void between the printed circuit board and the housing;a tamper detection component configured to fill the at least one design void; anda controller configured to: detect a tampering event based on a change of state in the tamper detection component; anddisable operation of the payment object reader upon detecting the tampering event occurred.
  • 7. The payment object reader of claim 6, further comprising: a shell inside the housing and configured to cover the printed circuit board and the electronic components, whereina first design void is between the shell and the printed circuit board.
  • 8. The payment object reader of claim 7, further comprising a second design void between the shell and the housing, andan opening between an edge of a slot in which the payment object is inserted and the payment reader, whereina separate tamper detection component is provided to fill each of the first design void, the second design void and the opening.
  • 9. The payment object reader of claim 6, wherein the tamper detection component is a tamper detection circuit.
  • 10. The payment object reader of claim 9, wherein the tamper detection circuit is a three-dimensional structure that fits within the at least one design void and is configured to communicate with the controller for detecting the tampering event.
  • 11. The payment object reader of claim 9, wherein the tamper detection circuit comprises two or more resistors.
  • 12. The payment object reader of claim 9, wherein the controller is configured to detect the tampering event by detecting one of a short circuit or a change in voltage across the tamper detection circuit.
  • 13. The payment object reader of claim 6, wherein the tamper detection component is a filler configured to expand within the at least one design void after being dispensed therein.
  • 14. The payment object reader of claim 13, wherein the filler is configured to completely cover the at least one design void upon complete expansion.
  • 15. The payment object reader of claim 13, wherein the filler is one of a plastic or a glue.
  • 16. The payment object reader of claim 13, wherein the filler is a semiconductive potting material.
  • 17. The payment object reader of claim 16, wherein the controller is configured to detect the tampering event by detecting a change in capacitance across the semiconductive potting material.
US Referenced Citations (347)
Number Name Date Kind
3128349 Boesch et al. Apr 1964 A
3854036 Gupta et al. Dec 1974 A
4035614 Frattarola et al. Jul 1977 A
4254441 Fisher Mar 1981 A
4591937 Nakarai et al. May 1986 A
4609957 Gentet et al. Sep 1986 A
4727544 Brunner et al. Feb 1988 A
4776003 Harris Oct 1988 A
4788420 Chang et al. Nov 1988 A
4845740 Tokuyama et al. Jul 1989 A
4860336 D'Avello et al. Aug 1989 A
5091811 Chang Feb 1992 A
5173597 Anglin Dec 1992 A
5221838 Gutman et al. Jun 1993 A
5266789 Anglin et al. Nov 1993 A
5270523 Chang et al. Dec 1993 A
5351296 Sullivan Sep 1994 A
5388155 Smith Feb 1995 A
5406627 Thompson et al. Apr 1995 A
5408513 Busch, Jr. et al. Apr 1995 A
5434400 Scherzer Jul 1995 A
5463678 Kepley, III et al. Oct 1995 A
5589855 Blumstein et al. Dec 1996 A
5603078 Henderson et al. Feb 1997 A
5616904 Fernadez Apr 1997 A
5679943 Schultz et al. Oct 1997 A
5714741 Pieterse et al. Feb 1998 A
5729591 Bailey Mar 1998 A
5740232 Pailles et al. Apr 1998 A
5764742 Howard et al. Jun 1998 A
5838773 Eisner et al. Nov 1998 A
5850599 Seiderman Dec 1998 A
5867795 Novis et al. Feb 1999 A
5878337 Joao et al. Mar 1999 A
5907801 Albert et al. May 1999 A
5940510 Curry et al. Aug 1999 A
5945654 Huang Aug 1999 A
5991410 Albert et al. Nov 1999 A
5991749 Morrill, Jr. Nov 1999 A
6006109 Shin Dec 1999 A
6010067 Elbaum Jan 2000 A
6021944 Arakaki Feb 2000 A
6032859 Muehlberger et al. Mar 2000 A
6061666 Do et al. May 2000 A
6095410 Andersen et al. Aug 2000 A
6098881 Deland, Jr. et al. Aug 2000 A
6129277 Grant et al. Oct 2000 A
6144336 Preston et al. Nov 2000 A
6234389 Valliani et al. May 2001 B1
6278779 Bryant et al. Aug 2001 B1
6308227 Kumar et al. Oct 2001 B1
6341353 Herman et al. Jan 2002 B1
6363139 Zurek et al. Mar 2002 B1
6400517 Murao Jun 2002 B1
6431445 DeLand et al. Aug 2002 B1
6476743 Brown et al. Nov 2002 B1
6481623 Grant et al. Nov 2002 B1
6497368 Friend et al. Dec 2002 B1
6536670 Postman et al. Mar 2003 B1
6612488 Suzuki Sep 2003 B2
6813608 Baranowski Nov 2004 B1
6832721 Fujii Dec 2004 B2
6850147 Prokoski et al. Feb 2005 B2
6868391 Hultgren Mar 2005 B1
6886742 Stoutenburg et al. May 2005 B2
6896182 Sakaguchi May 2005 B2
6898598 Himmel et al. May 2005 B2
6944782 von Mueller et al. Sep 2005 B2
6990683 Itabashi Jan 2006 B2
7003316 Elias et al. Feb 2006 B1
7013149 Vetro et al. Mar 2006 B2
7066382 Kaplan Jun 2006 B2
7083090 Zuili Aug 2006 B2
7149296 Brown et al. Dec 2006 B2
7163148 Durbin et al. Jan 2007 B2
7167711 Dennis Jan 2007 B1
7252232 Fernandes et al. Aug 2007 B2
7309012 von Mueller et al. Dec 2007 B2
7324836 Steenstra et al. Jan 2008 B2
7409234 Glezerman Aug 2008 B2
7424732 Matsumoto et al. Sep 2008 B2
7433452 Taylor et al. Oct 2008 B2
7505762 Onyon et al. Mar 2009 B2
7506812 von Mueller et al. Mar 2009 B2
7520430 Stewart et al. Apr 2009 B1
7581678 Narendra et al. Sep 2009 B2
7591425 Zuili et al. Sep 2009 B1
7600673 Stoutenburg et al. Oct 2009 B2
7668308 Wurtz Feb 2010 B1
7673799 Hart et al. Mar 2010 B2
7703676 Hart et al. Apr 2010 B2
7708189 Cipriano May 2010 B1
7757953 Hart et al. Jul 2010 B2
7793834 Hachey et al. Sep 2010 B2
7810729 Morley, Jr. Oct 2010 B2
7869591 Nagel et al. Jan 2011 B1
7945494 Williams May 2011 B2
8011587 Johnson et al. Sep 2011 B2
8015070 Sinha et al. Sep 2011 B2
8086531 Litster et al. Dec 2011 B2
8126734 Dicks et al. Feb 2012 B2
8231055 Wen Jul 2012 B2
8297507 Kayani Oct 2012 B2
8336771 Tsai et al. Dec 2012 B2
8367239 Hermann Feb 2013 B2
8376239 Humphrey Feb 2013 B1
8397988 Zuili Mar 2013 B1
8413901 Wen Apr 2013 B2
8500010 Marcus et al. Aug 2013 B1
8560823 Aytek et al. Oct 2013 B1
8571989 Dorsey et al. Oct 2013 B2
8573486 McKelvey et al. Nov 2013 B2
8573487 McKelvey Nov 2013 B2
8573489 Dorsey et al. Nov 2013 B2
8584946 Morley, Jr. Nov 2013 B2
8584956 Wilson et al. Nov 2013 B2
8602305 Dorsey et al. Dec 2013 B2
8612352 Dorsey et al. Dec 2013 B2
8615445 Dorsey et al. Dec 2013 B2
8640953 Dorsey et al. Feb 2014 B2
8662389 Dorsey et al. Mar 2014 B2
8678277 Dorsey et al. Mar 2014 B2
8701996 Dorsey et al. Apr 2014 B2
8701997 Dorsey et al. Apr 2014 B2
8763900 Marcus et al. Jul 2014 B2
8794517 Templeton et al. Aug 2014 B1
8820650 Wilson et al. Sep 2014 B2
8870070 McKelvey et al. Oct 2014 B2
8870071 McKelvey Oct 2014 B2
8876003 McKelvey Nov 2014 B2
8910868 Wade et al. Dec 2014 B1
8931699 Wade et al. Jan 2015 B1
8967465 Wade et al. Mar 2015 B1
9016572 Babu et al. Apr 2015 B2
9020853 Hoffman et al. Apr 2015 B2
9141950 Wade et al. Sep 2015 B2
9195454 Wade et al. Nov 2015 B2
9218517 Morley, Jr. Dec 2015 B2
9224142 Lamba et al. Dec 2015 B2
9230143 Wade et al. Jan 2016 B2
9237401 Modi et al. Jan 2016 B2
9262757 Lamba et al. Feb 2016 B2
9262777 Lamba et al. Feb 2016 B2
9286635 Lamba et al. Mar 2016 B2
9305314 Babu et al. Apr 2016 B2
9449203 Lamba et al. Sep 2016 B2
9495676 Lamba et al. Nov 2016 B2
9595033 Lamba et al. Mar 2017 B2
9633236 Wade Apr 2017 B1
9679286 Colnot et al. Jun 2017 B2
9799025 Skoog Oct 2017 B2
9858603 Lamba et al. Jan 2018 B2
10057395 Wagstaff et al. Aug 2018 B1
10410021 Razaghi et al. Sep 2019 B1
20010001856 Gould et al. May 2001 A1
20020002507 Hatakeyama Jan 2002 A1
20020017568 Grant et al. Feb 2002 A1
20020030871 Anderson et al. Mar 2002 A1
20020077974 Ortiz Jun 2002 A1
20020091633 Proctor Jul 2002 A1
20020099648 DeVoe et al. Jul 2002 A1
20020108062 Nakajima et al. Aug 2002 A1
20020165462 Westbrook et al. Nov 2002 A1
20020169541 Bouve et al. Nov 2002 A1
20020188535 Chao et al. Dec 2002 A1
20030089772 Chien May 2003 A1
20030132300 Dilday et al. Jul 2003 A1
20030135418 Shekhar et al. Jul 2003 A1
20030135463 Brown et al. Jul 2003 A1
20030144040 Liu et al. Jul 2003 A1
20030183691 Lahteenmaki et al. Oct 2003 A1
20040012875 Wood Jan 2004 A1
20040033726 Kao Feb 2004 A1
20040041911 Odagiri et al. Mar 2004 A1
20040058705 Morgan et al. Mar 2004 A1
20040059682 Hasumi et al. Mar 2004 A1
20040087339 Goldthwaite et al. May 2004 A1
20040093496 Colnot May 2004 A1
20040104268 Bailey Jun 2004 A1
20040127256 Goldthwaite et al. Jul 2004 A1
20040128256 Krouse et al. Jul 2004 A1
20040151026 Naso et al. Aug 2004 A1
20040167820 Melick et al. Aug 2004 A1
20040204074 Desai Oct 2004 A1
20040204082 Abeyta Oct 2004 A1
20040230489 Goldthwaite et al. Nov 2004 A1
20040230526 Praisner Nov 2004 A1
20040235524 Abuhamdeh Nov 2004 A1
20050077870 Ha et al. Apr 2005 A1
20050097015 Wilkes et al. May 2005 A1
20050109841 Ryan et al. May 2005 A1
20050156037 Wurzburg Jul 2005 A1
20050156038 Wurzburg et al. Jul 2005 A1
20050167496 Morley, Jr. et al. Aug 2005 A1
20050194452 Nordentoft et al. Sep 2005 A1
20050209719 Beckert et al. Sep 2005 A1
20050236480 Vrotsos et al. Oct 2005 A1
20050242173 Suzuki Nov 2005 A1
20050247787 Von Mueller et al. Nov 2005 A1
20060000917 Kim et al. Jan 2006 A1
20060032905 Bear et al. Feb 2006 A1
20060094481 Gullickson May 2006 A1
20060122902 Petrov et al. Jun 2006 A1
20060123138 Perdomo et al. Jun 2006 A1
20060142058 Elias et al. Jun 2006 A1
20060152276 Barksdale Jul 2006 A1
20060208066 Finn et al. Sep 2006 A1
20060219776 Finn Oct 2006 A1
20060223580 Antonio et al. Oct 2006 A1
20060234771 Shavrov Oct 2006 A1
20060255128 Johnson Nov 2006 A1
20060273158 Suzuki Dec 2006 A1
20070063048 Havens et al. Mar 2007 A1
20070067833 Colnot Mar 2007 A1
20070100651 Ramer et al. May 2007 A1
20070124211 Smith May 2007 A1
20070155430 Cheon et al. Jul 2007 A1
20070168300 Quesselaire et al. Jul 2007 A1
20070174080 Outwater Jul 2007 A1
20070194104 Fukuda et al. Aug 2007 A1
20070198436 Weiss Aug 2007 A1
20070201492 Kobayashi Aug 2007 A1
20070203836 Dodin Aug 2007 A1
20070221728 Ferro et al. Sep 2007 A1
20070236336 Borcherding Oct 2007 A1
20070244811 Tumminaro Oct 2007 A1
20070250623 Hickey et al. Oct 2007 A1
20070255620 Tumminaro et al. Nov 2007 A1
20070255643 Capuano et al. Nov 2007 A1
20070255653 Tumminaro et al. Nov 2007 A1
20080027815 Johnson et al. Jan 2008 A1
20080040265 Rackley, III et al. Feb 2008 A1
20080040274 Uzo Feb 2008 A1
20080059370 Sada et al. Mar 2008 A1
20080059375 Abifaker Mar 2008 A1
20080091617 Hazel et al. Apr 2008 A1
20080103972 Lanc May 2008 A1
20080130913 Kong et al. Jun 2008 A1
20080147564 Singhal Jun 2008 A1
20080172306 Schorr et al. Jul 2008 A1
20080177662 Smith et al. Jul 2008 A1
20080208762 Arthur et al. Aug 2008 A1
20080238610 Rosenberg Oct 2008 A1
20080249939 Veenstra Oct 2008 A1
20080275779 Lakshminarayanan Nov 2008 A1
20080294766 Wang et al. Nov 2008 A1
20090048978 Ginter et al. Feb 2009 A1
20090068982 Chen et al. Mar 2009 A1
20090070583 von Mueller et al. Mar 2009 A1
20090098908 Silverbrook et al. Apr 2009 A1
20090100168 Harris Apr 2009 A1
20090104920 Moon et al. Apr 2009 A1
20090112768 Hammad et al. Apr 2009 A1
20090117883 Coffing et al. May 2009 A1
20090119190 Realini May 2009 A1
20090125429 Takayama May 2009 A1
20090144161 Fisher Jun 2009 A1
20090159681 Mullen et al. Jun 2009 A1
20090164326 Bishop et al. Jun 2009 A1
20090166422 Biskupski Jul 2009 A1
20090180354 Sander et al. Jul 2009 A1
20090187492 Hammad et al. Jul 2009 A1
20100057620 Li et al. Mar 2010 A1
20100063893 Townsend Mar 2010 A1
20100117806 Hong May 2010 A1
20100127857 Kilmurray et al. May 2010 A1
20100128900 Johnson May 2010 A1
20100184479 Griffin, Jr. Jul 2010 A1
20100222000 Sauer et al. Sep 2010 A1
20100243732 Wallner Sep 2010 A1
20100260341 Sander et al. Oct 2010 A1
20100314446 Morley, Jr. Dec 2010 A1
20100332339 Patel et al. Dec 2010 A1
20110053560 Jain et al. Mar 2011 A1
20110062235 Morley, Jr. Mar 2011 A1
20110084131 McKelvey Apr 2011 A1
20110084139 McKelvey et al. Apr 2011 A1
20110137803 Willins Jun 2011 A1
20110161235 Beenau et al. Jun 2011 A1
20110191196 Orr et al. Aug 2011 A1
20110198395 Chen Aug 2011 A1
20110202463 Powell Aug 2011 A1
20110231272 Englund et al. Sep 2011 A1
20110258120 Weiss Oct 2011 A1
20110295721 MacDonald Dec 2011 A1
20110313880 Paul et al. Dec 2011 A1
20120005039 Dorsey et al. Jan 2012 A1
20120008851 Pennock et al. Jan 2012 A1
20120011071 Pennock et al. Jan 2012 A1
20120012653 Johnson et al. Jan 2012 A1
20120016794 Orr et al. Jan 2012 A1
20120052910 Mu et al. Mar 2012 A1
20120061467 Tang et al. Mar 2012 A1
20120095869 McKelvey Apr 2012 A1
20120095870 McKelvey Apr 2012 A1
20120095871 Dorsey et al. Apr 2012 A1
20120095906 Dorsey et al. Apr 2012 A1
20120095907 Dorsey et al. Apr 2012 A1
20120095916 Dorsey et al. Apr 2012 A1
20120118959 Sather et al. May 2012 A1
20120118960 Sather et al. May 2012 A1
20120126005 Dorsey et al. May 2012 A1
20120126006 Dorsey et al. May 2012 A1
20120126007 Lamba et al. May 2012 A1
20120126010 Babu et al. May 2012 A1
20120126013 Sather et al. May 2012 A1
20120126014 Sather et al. May 2012 A1
20120130903 Dorsey et al. May 2012 A1
20120138683 Sather et al. Jun 2012 A1
20120154561 Chari Jun 2012 A1
20120168505 Sather et al. Jul 2012 A1
20120234918 Lindsay Sep 2012 A1
20120246074 Annamalai et al. Sep 2012 A1
20120255996 Ahmed et al. Oct 2012 A1
20120259651 Mallon et al. Oct 2012 A1
20120270528 Goodman Oct 2012 A1
20120293001 Chan et al. Nov 2012 A1
20130031004 Dorsey et al. Jan 2013 A1
20130087614 Limtao et al. Apr 2013 A1
20130130743 Lin May 2013 A1
20130137367 Fisher May 2013 A1
20130200153 Dorsey et al. Aug 2013 A1
20130207481 Gobburu et al. Aug 2013 A1
20130254117 von Mueller et al. Sep 2013 A1
20130254574 Zacchio et al. Sep 2013 A1
20130299575 McKelvey et al. Nov 2013 A1
20130304244 Ojanpera Nov 2013 A1
20140001257 Dorsey et al. Jan 2014 A1
20140001263 Babu et al. Jan 2014 A1
20140017955 Lo et al. Jan 2014 A1
20140018016 Chang et al. Jan 2014 A1
20140061301 Cho et al. Mar 2014 A1
20140076964 Morley, Jr. Mar 2014 A1
20140097242 McKelvey Apr 2014 A1
20140124576 Zhou et al. May 2014 A1
20140131442 Morrow et al. May 2014 A1
20140144983 Dorsey et al. May 2014 A1
20140203082 Huh Jul 2014 A1
20140265642 Utley et al. Sep 2014 A1
20140297539 Swamy et al. Oct 2014 A1
20150100495 Salama et al. Apr 2015 A1
20150200590 Tanzawa Jul 2015 A1
20160171486 Wagner Jun 2016 A1
20160188915 Babu et al. Jun 2016 A1
20160275478 Li et al. Sep 2016 A1
20160371513 Lamba et al. Dec 2016 A1
20190095655 Krawczewicz Mar 2019 A1
Foreign Referenced Citations (123)
Number Date Country
2324402 Jun 2002 AU
2 811 979 Apr 2012 CA
2 812 251 Apr 2012 CA
2 812 594 Apr 2012 CA
2 812 611 Apr 2012 CA
2 813 236 Apr 2012 CA
2 813 237 Apr 2012 CA
2 932 849 Jun 2015 CA
2459833 Nov 2001 CN
2543289 Apr 2003 CN
1682240 Oct 2005 CN
1860730 Nov 2006 CN
101520928 Sep 2009 CN
102598046 Jul 2012 CN
104680369 Jun 2015 CN
20320080 Apr 2004 DE
0 895 203 Feb 1999 EP
1 874 014 Jan 2008 EP
2 812 744 Feb 2002 FR
2 812 745 Feb 2002 FR
2 834 156 Jun 2003 FR
H02-188884 Jul 1990 JP
H04-79430 Mar 1992 JP
H08-147420 Jun 1996 JP
109231285 Sep 1997 JP
2000-030146 Jan 2000 JP
2000-184087 Jun 2000 JP
2000-276539 Oct 2000 JP
2001-175723 Jun 2001 JP
2001-222595 Aug 2001 JP
2001-313714 Nov 2001 JP
2001-357337 Dec 2001 JP
2001-527672 Dec 2001 JP
2002-074507 Mar 2002 JP
2002-123771 Apr 2002 JP
2002-279320 Sep 2002 JP
2002-352166 Dec 2002 JP
2002-358285 Dec 2002 JP
2003-016359 Jan 2003 JP
2003-108777 Apr 2003 JP
2003-242428 Aug 2003 JP
2003-281453 Oct 2003 JP
2003-308438 Oct 2003 JP
2004-054651 Feb 2004 JP
2004-062733 Feb 2004 JP
2004-078553 Mar 2004 JP
2004-078662 Mar 2004 JP
2004-199405 Jul 2004 JP
2004-326727 Nov 2004 JP
2005-063869 Mar 2005 JP
2005-242550 Sep 2005 JP
2005-267031 Sep 2005 JP
2005-269172 Sep 2005 JP
2006-004264 Jan 2006 JP
2006-127390 May 2006 JP
2006-139641 Jun 2006 JP
2006-179060 Jul 2006 JP
2006-308438 Nov 2006 JP
2006-350450 Dec 2006 JP
2008-187375 Aug 2008 JP
2009-048567 Mar 2009 JP
2009-199649 Sep 2009 JP
2009-205196 Sep 2009 JP
2010-516002 May 2010 JP
2010-527063 Aug 2010 JP
2013-518344 May 2013 JP
2013-539889 Oct 2013 JP
2013-539890 Oct 2013 JP
2013-541105 Nov 2013 JP
2013-541106 Nov 2013 JP
2013-543180 Nov 2013 JP
2014-500537 Jan 2014 JP
2017-033603 Feb 2017 JP
2017-062844 Mar 2017 JP
10-1999-0066397 Aug 1999 KR
10-1999-0068618 Sep 1999 KR
200225019 Mar 2001 KR
10-2003-0005936 Jan 2003 KR
10-2003-0005984 Jan 2003 KR
10-2003-0012910 Feb 2003 KR
200333809 Nov 2003 KR
10-2004-0016548 Feb 2004 KR
100447431 Aug 2004 KR
10-0452161 Oct 2004 KR
10-2005-0077659 Aug 2005 KR
200405877 Jan 2006 KR
100649151 Nov 2006 KR
10-2007-0107990 Nov 2007 KR
10-2008-0039330 May 2008 KR
100842484 Jun 2008 KR
2012004397 Aug 2012 MX
2284578 Sep 2006 RU
1998012674 Mar 1998 WO
2000011624 Mar 2000 WO
2000025277 May 2000 WO
0137199 May 2001 WO
0165827 Sep 2001 WO
2001086599 Nov 2001 WO
2002033669 Apr 2002 WO
2002043020 May 2002 WO
02084548 Oct 2002 WO
2002082388 Oct 2002 WO
2003044710 May 2003 WO
2003079259 Sep 2003 WO
2004023366 Mar 2004 WO
2006131708 Dec 2006 WO
2007084896 Jul 2007 WO
2010097711 Sep 2010 WO
2010111130 Sep 2010 WO
2010135174 Nov 2010 WO
2011047028 Apr 2011 WO
2011047030 Apr 2011 WO
2011093998 Aug 2011 WO
2012051067 Apr 2012 WO
2012051069 Apr 2012 WO
2012051070 Apr 2012 WO
2012051071 Apr 2012 WO
2012051072 Apr 2012 WO
2012051073 Apr 2012 WO
2013009891 Jan 2013 WO
2013074499 May 2013 WO
2015089301 Jun 2015 WO
2016028823 Feb 2016 WO
Non-Patent Literature Citations (236)
Entry
Notice of Allowance dated Jul. 1, 2014 for U.S. Appl. No. 13/043,258, of McKelvey, J., filed Mar. 8, 2011.
Notice of Allowance dated Jul. 15, 2014 for U.S. Appl. No. 13/043,263, of McKelvey, J., filed Mar. 8,2011.
Non-Final Office Action dated Jul. 17, 2014 for U.S. Appl. No. 13/298,491, of Lamba, K., et al., filed Nov. 17, 2011.
Non-Final Office Action dated Jul. 22, 2014 for U.S. Appl. No. 13/298,560, of Lamba, K., et al., filed Nov. 17, 2011.
Corrected Notice of Allowance dated Jul. 30, 2014 for U.S. Appl. No. 14/052,009, of Wilson, M., et al., filed Oct. 11, 2013.
Notice of Allowance dated Aug. 1, 2014 for U.S. Appl. No. 14/203,463, of Wade, J., et al., filed Mar. 10, 2014.
Non-Final Office Action dated Aug. 15, 2014 for U.S. Appl. No. 13/010,976, of Babu, A. R., et al., filed Jan. 21, 2011.
Final Office Action dated Aug. 15, 2014 for U.S. Appl. No. 14/012,655, of McKelvey, J., filed Aug. 28, 2013.
Non-Final Office Action dated Aug. 21, 2014 for U.S. Appl. No. 13/298,487, of Lamba, K., et al., filed Nov. 17, 2011.
English-language translation of First Office Action and Search for Chinese Patent Application No. 201080051400.5, dated Sep. 3, 2014.
Non-Final Office Action dated Sep. 11, 2014 for U.S. Appl. No. 13/298,501, of Babu, A., et al., filed Nov. 17, 2011.
Non-Final Office Action dated Sep. 11, 2014 for U.S. Appl. No. 13/298,506, of Lamba, K., et al., filed Nov. 17, 2011.
Non-Final Office Action dated Sep. 11, 2014 for U.S. Appl. No. 13/298,510, of Lamba, K. et al., filed Nov. 17, 2011.
Non-Final Office Action dated Oct. 7, 2014 for U.S. Appl. No. 13/298,534, of Lamba, K., et al., filed Nov. 17, 2011.
Notice of Allowance dated Oct. 17, 2014 for U.S. Appl. No. 14/220,967, of Wade, J., et al., filed Mar. 20, 2014.
Notice of Allowance dated Nov. 25, 2014 for U.S. Appl. No. 14/231,598, of Claude, J.B., et al., filed Mar. 31, 2014.
Corrected Notice of Allowance dated Dec. 18, 2014 for U.S. Appl. No. 14/220,967, of Wade, J., et al., filed Mar. 20, 2014.
Notice of Allowance dated Dec. 24, 2014 for U.S. Appl. No. 13/010,976, of Babu, A. R., et al., filed Jan. 21, 2011.
Non-Final Office Action dated Jan. 20, 2015 for U.S. Appl. No. 14/012,655, of McKelvey, J., filed Aug. 28, 2013.
Examiner Requisition for Canadian Patent Application No. 2,813,237, dated Jan. 20, 2015.
Examiner Requisition for Canadian Patent Application No. 2,812,611, dated Jan. 22, 2015.
Examiner Requisition for Canadian Patent Application No. 2,812,251, dated Jan. 27, 2015.
Final Office Action dated Jan. 28, 2015 for U.S. Appl. No. 13/298,560, of Lamba, K., et al., filed Nov. 17, 2011.
Final Office Action dated Feb. 4, 2015 for U.S. Appl. No. 13/298,491, of Lamba, K., et al., filed Nov. 17, 2011.
Examiner Requisition for Canadian Patent Application No. 2,813,236, dated Feb. 17, 2015.
English-language translation of Decision of Refusal for Japanese Patent Application No. 2013-533897, dated Feb. 23, 2015.
Examiner Requisition for Canadian Patent Application No. 2,811,979, dated Feb. 23, 2015.
Examiner Requisition for Canadian Patent Application No. 2,812,594, dated Feb. 24, 2015.
Office Action for European Patent Application No. 11833169.3, dated Mar. 16, 2015.
Final Office Action dated Mar. 18, 2015 for U.S. Appl. No. 13/298,487, of Lamba, K., et al., filed Nov. 17, 2011.
Final Office Action dated Apr. 8, 2015 for U.S. Appl. No. 13/298,534, of Lamba, K., et al., filed Nov. 17, 2011.
Advisory Action dated Apr. 9, 2015 for U.S. Appl. No. 13/298,560, of Lamba, K., et al., filed Nov. 17, 2011.
Final Office Action dated May 6, 2015 for U.S. Appl. No. 13/298,501, of Babu, A., et al., filed Nov. 17, 2011.
Final Office Action dated May 6, 2015 for U.S. Appl. No. 13/298,506, of Lamba, K., et al., filed Nov. 17, 2011.
Final Office Action dated May 6, 2015 for U.S. Appl. No. 13/298,510, of Lamba, K. et al., filed Nov. 17, 2011.
Notice of Allowance dated May 19, 2015 for U.S. Appl. No. 14/620,765, of Wade, J., et al., filed Feb. 12, 2015.
Non-Final Office Action dated May 26, 2015 for U.S. Appl. No. 14/551,681, of Wade, J., et al., filed Nov. 24, 2014.
Notice of Allowance dated Jun. 22, 2015 for U.S. Appl. No. 13/298,491, of Lamba, K., et al., filed Nov. 17, 2011.
Non-Final Office Action dated Jul. 6, 2015 for U.S. Appl. No. 13/298,534, of Lamba, K., et al., filed Nov. 17, 2011.
Non-Final Office Action dated Jul. 16, 2015 for U.S. Appl. No. 13/298,560, of Lamba, K., et al., filed Nov. 17, 2011.
English-language translation of Office Action for Japanese Patent Application No. 2013-533895, dated Aug. 26, 2015.
Notice of Allowance dated Aug. 27, 2015, for U.S. Appl. No. 13/298,501, of Babu, A., et al., filed Nov. 17, 2011.
Notice of Allowance dated Aug. 28, 2015 for U.S. Appl. No. 13/298,510, of Lamba, K. et al., filed Nov. 17, 2011.
Notice of Allowance dated Sep. 1, 2015 for U.S. Appl. No. 13/298,487, of Lamba, K., et al., filed Nov. 17, 2011.
Notice of Allowance dated Sep. 2, 2015, for U.S. Appl. No. 14/578,107, of Wade, J. et al., filed Dec. 19, 2014.
English-language translation of Office Action for Japanese Patent Application No. 2013-533898, dated Sep. 9, 2015.
Advisory Action dated Sep. 11, 2015 for U.S. Appl. No. 13/298,506, of Lamba, K., et al., filed Nov. 17, 2011.
Notice of Allowance dated Sep. 16, 2015 for U.S. Appl. No. 14/551,681, of Wade, J., et al., filed Nov. 24, 2014.
English-language translation of Office Action for Japanese Patent Application No. 2013-533899, dated Sep. 30, 2015.
Notice of Allowance dated Oct. 6, 2015 for U.S. Appl. No. 13/298,491, of Lamba, K., et al., filed Nov. 17, 2011.
Notice of Allowance dated May 6, 2019, for U.S. Appl. No. 15/836,691 of Razaghi, M., et al., filed Dec. 8, 2017.
Bauer, G.R., et al., “Comparing Block Cipher Modes of Operation on MICAz Sensor Nodes,” 17th Euromicro International Conference on Parallel, Distributed and Network-based Processing, 2009, Feb. 18-20, 2009, pp. 371-378.
Lucks, S., “Two-Pass Authenticated Encryption Faster than Generic Composition,” H. Gilbert and H. Handschuh (Eds.): FSE 2005, LNCS 3557, © International Association for Cryptologic Research 2005, pp. 284-298.
Oumu, T., “Auction Techniques for Making Money without Failure—50 Tricks for selling at high price and buying at low price in Yahoo! Auction”, ASCII Net J. Japan, ASCII Corporation, dated Dec. 22, 2000, vol. 5, pp. 1-22.
“What is a Coupling Capacitor,” Retrieved from the Internet URL: http://www.learningaboutelectronics.com/Articles/What-is-a-coupling-capacitor, on Mar. 21, 2016, pp. 1-4.
Non-Final Office Action dated Sep. 30, 2011 for U.S. Appl. No. 12/903,753, of McKelvey, J., et al., filed Oct. 13, 2010.
Non-Final Office Action dated Sep. 30, 2011 for U.S. Appl. No. 13/005,822, of McKelvey, J., et al., filed Jan. 13, 2011.
Non-Final Office Action dated Sep. 30, 2011 for U.S. Appl. No. 13/010,976, of Babu, A. R., et al., filed Jan. 21, 2011.
Non-Final Office Action dated Oct. 7, 2011 for U.S. Appl. No. 13/043,258, of McKelvey, J., filed Mar. 8, 2011.
Non-Final Office Action dated Oct. 11, 2011 for U.S. Appl. No. 13/043,203, of McKelvey. J., et al., filed Mar. 8, 2011.
Non-Final office Action dated Oct. 11, 2011 for U.S. Appl. No. 13/043,263, of McKelvey, J., filed Mar. 8, 2011.
Final Office Action dated Jun. 12, 2012 for U.S. Appl. No. 13/010,976, of Babu, A. R., et al., filed Jan. 21, 2011.
Final Office Action dated Jul. 6, 2012 for U.S. Appl. No. 12/903,753, of McKelvey, J., et al., filed Oct. 13, 2010.
Final Office Action dated Jul. 6, 2012 for U.S. Appl. No. 13/043,203, of McKelvey. J., et al., filed Mar. 8, 2011.
Final Office Action dated Jul. 9, 2012 for U.S. Appl. No. 13/005,822, of McKelvey, J., et al., filed Jan. 13, 2011.
Final office Action dated Jul. 9, 2012 for U.S. Appl. No. 13/043,263, of McKelvey, J., filed Mar. 8, 2011.
Final Office Action dated Jul. 13, 2012 for U.S. Appl. No. 13/043,258, of McKelvey, J., filed Mar. 8, 2011.
Non-Final Office Action dated Jul. 19, 2012 for U.S. Appl. No. 12/903,758, of Wilson, M., et al., filed Oct. 13, 2010.
Advisory Action dated Aug. 1, 2012 for U.S. Appl. No. 13/043,203, of McKelvey, J., filed Mar. 8, 2011.
Advisory Action dated Aug. 15, 2012 for U.S. Appl. No. 13/043,258, of McKelvey, J., filed Mar. 8, 2011.
Advisory Action dated Aug. 16, 2012 for U.S. Appl. No. 13/043,263, of McKelvey, J., filed Mar. 38,2011.
Advisory Action dated Aug. 17, 2012 for U.S. Appl. No. 13/005,822, of McKelvey, J.,et al., filed Jan. 13, 2011.
Advisory Action dated Aug. 24, 2012 for U.S. Appl. No. 13/010,976, of Babu, A. R., et al., filed Jan. 21, 2011.
Final Office Action dated Apr. 24, 2013 for U.S. Appl. No. 12/903,758, of Wilson, M., et al., filed Oct. 13, 2010.
Non-Final Office Action dated Apr. 25, 2013 for U.S. Appl. No. 13/298,491, of Lamba, K., et al., filed Nov. 17, 2011.
Non-Final Office Action dated Apr. 29, 2013 for U.S. Appl. No. 13/043,263, of McKelvey, J., filed Mar. 38, 2011.
Non-Final Office Action dated Apr. 29, 2013 for U.S. Appl. No. 13/298,487, of Babu, A., et al., filed Nov. 17, 2011.
Non-Final Office Action dated Apr. 30, 2013 for U.S. Appl. No. 13/043,203, of McKelvey, J., filed Mar. 8, 2011.
Non-Final Office Action dated May 28, 2013 for U.S. Appl. No. 13/298,560, of Lamba, K., et al., filed Nov. 17, 2011.
Non-Final Office Action dated Jun. 18, 2013 for U.S. Appl. No. 13/005,822, of McKelvey, J., et al., filed Jan. 13, 2011.
Non-Final Office Action dated Jul. 8, 2013 for U.S. Appl. No. 12/903,753, of McKelvey, J., et al., filed Oct. 13, 2010.
Notice of Allowance dated Jul. 9, 2013 for U.S. Appl. No. 13/043,203, of McKelvey, J., filed Mar. 8, 2011.
Notice of Allowance dated Aug. 6, 2013 for U.S. Appl. No. 12/903,758, of Wilson, M., et al., filed Oct. 13, 2010.
Final Office Action dated Aug. 15, 2013 for U.S. Appl. No. 13/043,263, of McKelvey, J., filed Mar. 8, 2011.
Final Office Action dated Aug. 22, 2013 for U.S. Appl. No. 13/298,487, of Babu, A., et al., filed Nov. 17, 2011.
Final Office Action dated Sep. 6, 2013 for U.S. Appl. No. 13/298,560, of Lamba, K., et al., filed Nov. 17, 2011.
Final Office Action dated Sep. 17, 2013 for U.S. Appl. No. 13/298,491, of Lamba, K., et al., filed Nov. 17, 2011.
Notice of Allowance dated Oct. 10, 2013, for U.S. Appl. No. 12/903,753, of Mckelvey, J., filed Oct. 13, 2010.
Advisory Action dated Oct. 21, 2013 for U.S. Appl. No. 13/298,560 of Lamba, K., et al., filed Nov. 17, 2011.
Advisory Action dated Oct. 22, 2013 for U.S. Appl. No. 13/298,487, of Babu, A., et al., filed Nov. 17, 2011.
Advisory Action dated Oct. 22, 2013 for U.S. Appl. No. 13/298,491, of Lamba, K., et al., filed Nov. 17, 2011.
Advisory Action dated Nov. 8, 2013 for U.S. Appl. No. 13/043,263, of McKelvey, J., filed Mar. 38, 2011.
Non-Final Office Action dated Nov. 21, 2013 for U.S. Appl. No. 14/052,009, of Wilson, M., et al., filed Oct. 11, 2013.
Non-Final Office Action dated Dec. 10, 2013 for U.S. Appl. No. 13/005,822 of McKelvey, J., et al., Filed Jan. 13, 2011.
Non-Final Office Action dated Dec. 11, 2013 for U.S. Appl. No. 13/043,258, of McKelvey, J., filed Mar. 8, 2011.
Non-Final Office Action dated Feb. 24, 2014 for U.S. Appl. No. 13/043,263, of McKelvey, J., filed Mar. 8, 2011.
Non-Final Office Action dated Apr. 2, 2014 for U.S. Appl. No. 14/012,655, of McKelvey, J., filed Aug. 28, 2013.
Notice of Allowance dated Apr. 4, 2014 for U.S. Appl. No. 14/052,009, of Wilson, M., et al., filed Oct. 11, 2013.
English-language translation of Office Action for Japanese Patent Application No. 2013-533897, dated Jun. 5, 2014.
Non-Final Office Action dated Jun. 6, 2014 for U.S. Appl. No. 14/231,598, of Wade, J., et al., filed Mar. 31, 2014.
Notice of Allowance dated Jun. 24, 2014 for U.S. Appl. No. 13/005,822, of McKelvey, J., et al., filed Jan. 13, 2011.
“Connection of Terminal Equipment to the Telephone Network,” FCC 47 CFR Part 68, Retrieved from the URL: http://www.tscm.com/FCC47CFRpart68.pdf , on Sep. 24, 2019 Oct. 1, 1999 Edition.
“Embedded FINancial transactional IC card READer,” Retrieved from the URL: https://cordis.europa.eu/project/rcn/58338/factsheet/en.
Geethapriya Venkataramani and Srividya Gopalan., “Mobile phone based RFID architecture for secure electronic payments using RFID credit cards,” 2007 IEEE, (ARES'07).
“Guideline for the Use of Advanced Authentication Technology,” FIPS 190, Sep. 28, 1994.
“Identification cards—Recording technique—Part 4—Location of read-only magnetic tracks—Track 1 and 2,” ISO/IEC 7811-4:1995, International Organization for Standardization, Aug. 1995.
Jerome Svigals., “The Long Life and Imminent Death of the Mag-stripe Card,” IEEE Spectrum, vol. 49, Issue 61, Jun. 2012.
“Magensa's Decryption Services and MagTek's MagneSafe™ Bluetooth Readers Selected by eProcessing Network to Implement Secure Customer Card Data with Mobile Devices,” Retrieved from the URL: https://www.magnensa.net/aboutus/articles/eProcessing - rev1.pdf Apr. 14, 2008.
Martha E Haykin et al., “Smart Card Technology: New Methods for Computer Access Control,” NIST Special Publication 500-157, Sep. 1988.
“MSP430x1xx Family User's Guide,” (including 2016 correction sheet at 2), Texas Instruments Inc., 2006.
Spegele, Joseph Brain., “A Framework for Evaluating Application of Smart Cards and Related Technology Within the Department of Defense,” Naval Postgraduate School, Jan. 1995.
Stephen A. Sherman et al., “Secure Network Access Using Multiple Applications of AT&T's Smart Card,” AT&T Technical Journal, Sep./Oct. 1994.
Notice of Allowance dated Oct. 7, 2015 for U.S. Appl. No. 13/298,510, of Lamba, K., et al., filed Nov. 17, 2011.
Notice of Allowance dated Oct. 8, 2015 for U.S. Appl. No. 13/298,487, of Lamba, K., et al., filed Nov. 17, 2011.
Notice of Allowance dated Oct. 13, 2015 for U.S. Appl. No. 14/578,107, of Wade, J., et al., filed Dec. 19, 2014.
Notice of Allowance dated Nov. 13, 2015 for U.S. Appl. No. 13/298,487, of Lamba, K., et al., filed Nov. 17, 2011.
Corrected Notice of Allowance dated Nov. 18, 2015, for U.S. Appl. No. 14/578,107, of Wade, J., et al., filed Dec. 19, 2014.
Notice of Allowance dated Nov. 19, 2015 for U.S. Appl. No. 13/298,491, of Lamba, K., et al., filed Nov. 17, 2011.
Notice of Allowance dated Nov. 20, 2015 for U.S. Appl. No. 13/298,501, of Babu, A., et al., filed Nov. 17, 2011.
Non-Final Office Action dated Dec. 14, 2015 for U.S. Appl. No. 13/298,506, of Lamba, K., et al., filed Nov. 17, 2011.
Notice of Allowance for Canadian Patent Application No. 2,812,251, dated Jan. 5, 2016.
Notice of Allowance dated Jan. 12, 2016, for U.S. Appl. No. 13/298,534, of Lamba, K., et al., filed Nov. 17, 2011.
Corrected Notice of Allowance dated Jan. 29, 2016, for U.S. Appl. No. 13/298,534, of Lamba, K., et al., filed Nov. 17, 2011.
Final Office Action dated Feb. 1, 2016, for U.S. Appl. No. 13/298,560, of Lamba, K., et al., filed Nov. 17, 2011.
Notice of Allowance for Canadian Patent Application No. 2,812,611, dated Feb. 19, 2016.
English-language translation of Decision to Grant for Japanese Patent Application No. 2013-533895, dated Feb. 22, 2016.
Examiner Requisition for Canadian Patent Application No. 2,812,594, dated Feb. 26, 2016.
Examiner Requisition for Canadian Patent Application No. 2,811,979, dated Feb. 26, 2016.
Non-Final Office Action dated Mar. 1, 2016, for U.S. Appl. No. 14/942,515, of Lamba, K., et al., filed Nov. 16, 2015.
Examiner Requisition for Canadian Patent Application No. 2,813,236, dated Mar. 21, 2016.
Non-Final Office Action dated Apr. 7, 2016, for U.S. Appl. No. 13/298,506, of Lamba, K., et al., filed Nov. 17, 2011.
Advisory Action dated Apr. 14, 2016, for U.S. Appl. No. 13/298,560, of Lamba, K., et al., filed Nov. 17, 2011.
Non-Final Office Action dated May 5, 2016, for U.S. Appl. No. 14/306,041, of Wade, J., filed Jun. 16, 2014.
Notice of Allowance dated May 10, 2016, for U.S. Appl. No. 14/942,515, of Lamba, K., et al., filed Nov. 16, 2015.
Office Action for European Patent Application No. 11833172.7, dated May 17, 2016.
Office Action for European Patent Application No. 11833173.5, dated May 18, 2016.
Non-Final Office Action dated May 19, 2016, for U.S. Appl. No. 13/298,560, of Lamba, K., et al., filed Nov. 17, 2011.
Office Action for European Patent Application No. 11833174.3, dated May 19, 2016.
English-language translation of Office Action for Japanese Patent Application No. 2013-533899, dated Jun. 1, 2016.
English-language translation of Decision of Final Rejection for Japanese Patent Application No. 2013-533898, dated Jun. 29, 2016.
Notice of Acceptance for Australian Patent Application No. 2014362287, dated Jun. 30, 2016.
Non-Final Office Action dated Jun. 30, 2016 for U.S. Appl. No. 15/066,496, of Babu, A., et al., filed Mar. 10, 2016.
Non-Final Office Action dated Jul. 1, 2016, for U.S. Appl. No. 15/013,937, of Lamba, K., et al., filed Feb. 2, 2016.
Examiner Requisition for Canadian Patent Application No. 2,932,849, dated Jul. 13, 2016.
Notice of Allowance dated Aug. 26, 2016, for U.S. Appl. No. 13/298,506, of Lamba, K., et al., filed Nov. 17, 2011.
Notice of Allowance dated Sep. 27, 2016, for U.S. Appl. No. 14/306,041, of Wade, J., filed Jun. 16, 2014.
Notice of Allowance dated Oct. 26, 2016, for U.S. Appl. No. 15/013,937, of Lamba, K., et al., filed Feb. 2, 2016.
Final Office Action dated Nov. 3, 2016, for U.S. Appl. No. 13/298,560, of Lamba, K., et al., filed Nov. 17, 2011.
Notice of Allowance dated Dec. 19, 2016, for U.S. Appl. No. 14/306,041, of Wade, J., filed Jun. 16, 2014.
Non-Final Office Action dated Jan. 17, 2017, for U.S. Appl. No. 14/463,455, of Skoog, L., filed Aug. 19, 2014.
Non-Final Office Action dated Feb. 15, 2017, for U.S. Appl. No. 15/066,496, of Babu, A., et al., filed Mar. 10, 2016.
Advisory Action dated Feb. 21, 2017, for U.S. Appl. No. 13/298,560, of Lamba K, et al., filed Nov. 17, 2011.
English-language translation of Decision of Refusal for Japanese Patent Application No. 2013-533899, dated Feb. 22, 2017.
Examiner Requisition for Canadian Patent Application No. 2,811,979, dated Mar. 10, 2017.
Notice of Allowance for Canadian Patent Application No. 2,932,849, dated Mar. 27, 2017.
Examiner Requisition for Canadian Patent Application No. 2,813,236, dated Apr. 20, 2017.
Non-Final Office Action dated May 8, 2017, for U.S. Appl. No. 15/013,964, of Lamba, K., et al., filed Feb. 2, 2016.
Notice of Allowance dated Jun. 22, 2017, for U.S. Appl. No. 14/463,455, of Skoog, L., filed Aug. 19, 2014.
Non-Final Office Action dated Jul. 28, 2017, for U.S. Appl. No. 15/252,033, of Lamba, K., et al., filed Aug. 30, 2016.
Summons to attend Oral Proceedings for European Patent Application No. 11833173.5, mailed Aug. 2, 2017.
English-language translation of First Office Action and Search for Chinese Patent Application No. 201510109013.7, dated Sep. 5, 2017.
Ex Parte Quayle Action mailed Sep. 8, 2017, for U.S. Appl. No. 15/066,496, of Babu, A., et al., filed Mar. 10, 2016.
Notice of Allowance dated Sep. 28, 2017, for U.S. Appl. No. 15/013,964, of Lamba, K., et al., filed Feb. 2, 2016.
Office Action for European Patent Application No. 11833172.7, dated Oct. 24, 2017.
English-language translation of Notification of Reasons for Refusal for Japanese Patent Application No. 2016-234281, dated Dec. 1, 2017.
English-language translation of Notification of Reasons for Refusal for Japanese Patent Application No. 2016-213566, dated Jan. 12, 2018.
Notice of Allowance dated Jan. 18, 2018, for U.S. Appl. No. 15/066,496, of Babu, A., et al., filed Mar. 10, 2016.
Notice of Allowance for Canadian Patent Application No. 2,811,979, dated Jan. 25, 2018.
Final Office Action dated Jan. 29, 2018, for U.S. Appl. No. 15/252,033, of Lamba, K., et al., filed Aug. 30, 2016.
Corrected Notice of Allowance dated Feb. 9, 2018, for U.S. Appl. No. 15/066,496, of Babu, A., et al., filed Mar. 10, 2016.
Examiner Requisition for Canadian Application No. 2,813,236, dated May 3, 2018.
International Search Report and Written Opinion for International Application No. PCT/US2010/052483, dated Jun. 10, 2011.
International Search Report and Written Opinion for International Application No. PCT/US2010/052481, dated Jun. 23, 2011.
International Search Report and Written Opinion for International Application No. PCT/US2011/055382, dated Dec. 28, 2011.
International Search Report and Written Opinion for International Application No. PCT/US2011/055394, dated Dec. 28, 2011.
International Search Report and Written Opinion for International Application No. PCT/US2011/055386, dated Feb. 22, 2012.
International Search Report and Written Opinion for International Application No. PCT/US2011/055402 dated Feb. 24, 2012.
International Search Report and Written Opinion for International application No. PCT/US2011/055387, dated Feb. 29, 2012.
International Search Report and Written Opinion for International Application No. PCT/US2011/055375, dated Mar. 2, 2012.
International Search Report and Written Opinion for International Application No. PCT/US2012/064782, dated Feb. 26, 2013.
English-language translation of Search Report for Japanese Patent Application No. 2013-533897, dated Apr. 14, 2014.
Supplementary European Search Report for European Patent Application No. 11833169.3, dated Apr. 17, 2014.
Supplementary European Search Report for European Patent Application No. 11833171.9, dated Apr. 17, 2014.
Supplementary European Search Report for European Patent Application No. 11833174.3, dated Apr. 17, 2014.
Supplementary European Search Report for European Patent Application No. 11833173.5, dated Apr. 17, 2014.
European Search Report for European Patent Application No. 11833172.7, dated Apr. 22, 2014.
International Search Report and Written Opinion for International Application No. PCT/US2014/069788, dated May 14, 2015.
English-language translation of Search Report in Japanese Patent Application No. 2013-533895, dated Jul. 23, 2015.
English-language translation of Search Report for Japanese Patent Application No. 2013-533899, dated Aug. 14, 2015.
English-language translation of Search Report for Japanese Patent Application No. 2013-533898, dated Aug. 26, 2015.
International Search Report and Written Opinion for International Application No. PCT/US2015/045772, dated Nov. 6, 2015.
“2.5mm Headset Jack,” Retrieved from the Internet URL: http://www.phonescoop.com/glossary/term.php?gid=360, on May 5, 2011, pp. 1-1.
“A Magnetic Stripe Reader—Read Credit Cards & Driver Licences!,” Articlesbase (articlesbase.com), Sep. 7, 2009, Retrieved from the Internet URL: http://www.articlesbase.com/electronics-articlesta-magnetic-stripe-reader-read-credit-cards- . . . , on Feb. 8, 2011, pp. 1-3.
“Announcement: Semtek Introduces Side Swipe II Card Reader for Wireless Devices,” Brighthand, Retrieved from the Internet URL: http://forum.brighthand.com/pdas-handhelds/173285-announcement-semtek-introduces-sid . . . , on Apr. 19, 2011, pp. 1-2.
“Barcode scanner and Magnetic Stripe Reader (MSR) for Pocke . . . ,” Tom's Hardware (tomshardware.com), Retrieved from the Internet URL: http://www.tomshardware.com/forum/24068-36-barcode-scanner-magnetic-stripe-reader-po . . . , on Feb. 8, 2011, pp. 1-2.
“Credit Card Swiper and Reader for iPhone, iPad, Blackberry, Android and more,” Retrieved from the Internet URL: http://hubpages.com/hub/Credit-Card-Swiper-and-Reader-for-iPhone-iPad-Blackberry-An . . . , on Apr. 20, 2011, pp. 1-2.
“Get paid on the spot from your mobile phone,” Retrieved from the Internet URL: http://payments.intuit.com/products/basic-payment-solutions/mobile-credit-card-processin . . . , on Feb. 11, 2011, pp. 1-3.
“Headphone Jack (3.5mm),” Retrieved from the Internet URL: http://www.phonescoop.com/glossary/term.php?gid=440, on May 5, 2011, pp. 1-1.
“Magnetic Card Reader,” lekernel.net˜scrapbook, Retrieved from the Internet URL: http://lekernel.net/scrapbook/old/cardreader.html, on Apr. 25, 2011, pp. 1-4.
“Magnetic Stripe Reader (MSR) MSR7000-100R,” Motorola Solutions, Retrieved from the Internet URL: http://www.motorola.com/business/US-EN/MSR7000-100R_US-EN.do?vgnextoid=164fc3 . . . , on Feb. 8, 2011, pp. 1-1.
“Magnetic stripe reader/writer,” Retrieved from the Internet URL: http://www.gae.ucm.es/-padilla/extrawork/stripe.html, on Dec. 21, 2009, pp. 1-2.
“Mag-stripe readers the hunt for a homebrew mag-stripe reader that'll work with modern,” Jan. 16, 2009, Retrieved from the Internet URL: http://www.hak5.org/forums/index.php?showtopic=11563&st=20, on Apr. 25, 2011, pp. 1-6.
“Mophie Marketplace Magnetic Strip Reader/Case for iPhone 3G & 3GS—Grey,” J&R (JR.com), Retrieved from the Internet URL: http://www.jr.com/mophie/pe/MPE_MPIP3GBLK/, on Feb. 8, 2011, pp. 1-1.
“MSR500EX (Mini123EX) Portable Magnetic Stripe Card Reader,” TYNER, Apr. 27, 2007, Retrieved from the Internet URL: http://www.tyner.com/magnetic/msr500ex.htm, on Apr. 22, 2011, pp. 1-3.
“Pay@PC,” Retrieved from the Internet URL: http://www.merchantanywhere.com/PAY_AT_PCT@PC.htm, on Feb. 11, 2011, pp. 1-2.
“Reference Designations for Electrical and Electronics Parts and Equipment, Engineering Drawing and Related Documentation Practices,” ASME Y14A4-2008, The American Society of Mechanical Engineers, Nov. 21, 2008, pp. 1-31.
“Semtek 3913 Insert Magnetic Card Reader 20 Pin Serial RS232,” Product description, RecycledGoods.com, Retrieved from the Internet URL: http://www.recycledgoods.com/products/Semtek-3913-Insert-Magnetic-Card-Reader-20-Pi . . . , on Apr. 19, 2011, pp. 1-3.
“Semtek to target healthcare with HandEra PDAs and PDA swipe card reader,” Aug. 29, 2001, Retrieved from the Internet URL: http://www.pdacortex.com/semtek.htm, on Apr. 19, 2011, pp. 1-2.
“Touch-Pay Wireless Credit Card Processing,” MerchantSeek, Retrieved from the Internet URL: http://www.merchantseek.com/wireless-credit-card-processing.htm, on Feb. 11, 2011, pp. 1-5.
“Travel industry targeted for Palm PDA card reader,” Retrieved from the Internet URL: http://www.m-travel.com/news/2001/08/travel_industry.html, on Apr. 19, 2011, pp. 1-2.
“USB Magnetic Stripe Credit/Card Track-2 Reader and Writer (75/210BPI),” Deal Extreme (dealextreme.com), Nov. 15, 2008, Retrieved from the Internet URL: http://www.dealextreme.com/p/usb-magnetic-stripe-credit-debit-card-track-2-reader-and-wr . . . , on Feb. 8, 2011, pp. 1-3.
Acidus, “Mag-stripe Interfacing—A Lost Art,” Retrieved from the Internet URL: http://www.scribd.com/doc/18236182/Magstripe-Interfacing#open_ . . . , on Feb. 7, 2011, pp. 1-4.
Bourdeauducq, S., “Reading magnetic cards (almost) for free” (“Lekernel”), Jan. 26, 2009, Retrieved from the internet URL: http://lekernel.net/blog/?p=12, on May 5, 2011, pp. 1-2.
Buttell, A.E., “Merchants eye mobile phones to transact card payments,” Feb. 3, 2010, Retrieved from the Internet URL: http://www.merchantaccountguide.com/merchant-account-news/cell-phone-credit-card-mer . . . , on Feb. 8, 2011, pp. 1-3.
Grandison, K., “vTerminal Credit Card Processing App for AuthorizeNet and PayPal Payflow Pro for Curve 8350 8500 8900 and Bold 9000,” Retrieved from the Internet URL: http://www.4blackberry.net/tag/business-tools/vterminal-credit-card-processing-app-for-authorizenet-and-paypal-payflow-pro-for-curve-8350-8500-890-download-2075.html, on Mar. 30, 2015, pp. 1-4.
Harris A., “Magnetic Stripe Card Spoofer,” Aug. 4, 2008, Retrieved from the Internet URL: http://hackaday.com/2008/08/04/magnetic-stripe-card-spoofer/, on Apr. 25, 2011, pp. 1-11.
Jones, R., “U.S. Credit Cards to get a high-tech makeover,” Oct. 22, 2010, Retrieved from the Internet URL: http://lifeine.today.com/_news/2010/10/22/5334208-us-credit-cards-to-get-a-high-tech-mak . . . , on Feb. 8, 2011, pp. 1-8.
Kuo, Y-S et al., “Hijacking Power and Bandwidth from the Mobile Phone's Audio Interface,” Proceedings of the First ACM Symposium on Computing for Development, (DEV'10), Dec. 17, 2010, pp. 1-10.
Padilla, L. “The simplest magnetic stripe reader,” Jan. 27, 2003, Retrieved from the Internet URL: www.gae.ucm.esi˜padilla/extrawork/soundtrack.html, on Dec. 21, 2009, pp. 1-5.
Padilla, L., “Magnetic stripe reader circuit,” Jan. 28, 1997, Retrieved from the Internet URL: http://www.gae.ucm.es/˜padilla/extraworkImagamp.html, on May 5, 2011, pp. 1-7.
Padilla, L., “Turning your mobile into a magnetic stripe reader,” Retrieved from the Internet URL: http://www.gae.ucm.es/˜padilla/extrawork/mobilesoundtrack.html, on Feb. 7, 2011, pp. 1-4.
Ryan, P., “Plug and Pay: A Gallery of 26 Mobile Card Readers,” Aug. 20, 2013, Retrieved from the Internet URL: hittp://bankinnovation.net/2013/08/plug-and-pay-a-gallery-of-26-mobile-card-readers/, on Feb. 19, 2015, pp. 1-12.
Titlow, J.P., “Roam pay is like Square for Blackberry (Plus Android, iOS and Desktops),” Dec. 1, 2010, Retrieved from the Internet URL: http://www.readwriteweb.com/biz/2010/12/roampay-is-like-square-for-bla.php, on Apr. 20, 2011, pp. 1-12.
Veneziani, V., “Use a cellphone as a magnetic card reader,” Apr. 15, 2005, Retrieved from the Internet URL: http://hackaday.com/2005/04/15/use a-cellphone-as-a-magnetic-card . . . , on Feb. 7, 2011, pp. 1-10.
Website: www.alexwinston.com, Aug. 31, 2009, pp. 1-5.
Examiner Requisition for Canadian Patent Application No. 2,812,594, dated Jun. 19, 2018.
Notice of Allowance dated Jul. 6, 2018, for U.S. Appl. No. 15/252,033, of Lamba, K., et al., filed Aug. 30, 2016.
Non-Final Office Action dated Jan. 7, 2019, for U.S. Appl. No. 15/836,691, of Razaghi, M., et al., filed Dec. 8, 2017.
English-language translation of Notification to Grant for Chinese Patent Application No. 201510109013.7, dated Aug. 3, 2018.
English-language translation of Decision of Refusal for Japanese Patent Application No. 2016-234281, dated Aug. 17, 2018.
English-language translation of Decision of Refusal for Japanese Patent Application No. 2016-213566, dated Sep. 18, 2018.
Non-Final Office Action dated Jan. 6, 2021, for U.S. Appl. No. 16/564,553, of Razaghi, M., et al., filed Sep. 9, 2019.
Decision to Grant for European Patent Application No. 11833169.3, dated Oct. 24, 2019.
Decision to Grant for European Patent Application No. 11833172.7, dated Nov. 14, 2019.
Notice of Allowance dated Apr. 28, 2021, for U.S. Appl. No. 16/564,553, of Razaghi, M., et al., filed Sep. 9, 2019.
Corrected Notice of Allowability dated May 18, 2021, for U.S. Appl. No. 16/564,553, of Razaghi, M., et al., filed Sep. 9, 2019.