The present invention relates to the field of quantum computing, and, in particular, to the use of superconducting nanostructures for handling quantum information.
Nanowires (NWs) and nanotubes approximating 1-dimensional structures are a basis for topological superconducting devices, in which Majorana Zero Modes (MZM) are formed at the boundaries of topological superconducting regions. MZMs are zero-energy quasiparticle excitations which are electrically neutral, which are their own anti-particles, and which exhibit non-Abelian exchange statistics. These properties make MZMs desirable for use in quantum computing, by occupying degenerate zero-energy ground states in which quantum qubits may be encoded.
MZMs possess several advantages in a quantum computing environment, including immunity to decoherence and a high degree of noise-resistance, which would greatly reduce or altogether eliminate the need for large-scale redundancies and burdensome fault-tolerance measures.
Establishing a regime of topological superconductivity in such a 1-dimensional structure, however, requires careful tuning of the chemical potential of the structure. This is typically performed using external gating, which typically depends on a delicate balance of external parameters. It would therefore be highly beneficial and desirable to have microfilament devices which are not restricted by such tuning requirements. This goal is met by embodiments of the present invention.
Embodiments of the present invention provide 1-dimensional nanostructures which facilitate establishing regions of 1-dimensional topological superconductivity without the need for elaborate tuning procedures. Certain embodiments also provide a novel mechanism for transporting MZMs from one location to another location. Further embodiments provide a swap gate for interchanging the respective quantum states of MZMs in two different locations.
In one embodiment this invention provides a quantum computing device comprising:
In one embodiment of the quantum computing device Majorana Zero Modes (MZMs) are present at the boundaries the at least one discrete superconducting region. In one embodiment of the quantum computing device the tapered NW comprises a semiconducting material. In one embodiment of the quantum computing device the semiconducting material is a high spin-orbit coupling material. In one embodiment of the quantum computing device the high spin-orbit coupling material is selected from Indium Arsenide (InAs) or Indium Antimonide (InSb). In one embodiment of the quantum computing device the tapered NW is gate-defined. In one embodiment of the quantum computing device the substrate is conductive. In one embodiment of the quantum computing device the substrate is doped silicon. In one embodiment the doped silicon is highly doped. In another embodiment the doped silicon is either n-type or p-type. In one embodiment the quantum computing device further comprises at least one insulating layer disposed in between the substrate and the tapered NW. In another embodiment, the device comprises additional layers to improve coupling between layers. In one embodiment of the quantum computing device the superconducting layer comprises at least one superconducting metal. In one embodiment of the quantum computing device the superconducting layer at least partially covers the tapered NW. In one embodiment the quantum computing device further comprises at least one gate, configured to control the electric potential within the tapered NW. In one embodiment the at least one gate is a back gate. In another embodiment, gate-defined NWs are coupled to a 2D electron gas.
In one embodiment the presently disclosed subject matter provides a crossed tapered NW device, the device comprising:
In one embodiment of the crossed tapered NW device the first tapered NW and the second tapered NW comprise a semiconducting high spin-orbit coupling material. In one embodiment the first tapered NW and the second tapered NW are gate-defined NWs. In one embodiment the crossed tapered NW further comprises electrodes disposed at the ends of the first tapered NW and the second tapered NW and wherein the at least one voltage source is configured to apply a potential across each of the first tapered NW and the second tapered NW. In one embodiment the crossed tapered NW further comprises at least one gate configured to control the electric potential within the first tapered NW and the second tapered NW. In one embodiment the crossed tapered NW is provided for use in a quantum computer.
In one embodiment the presently disclosed subject matter provides a method of performing a quantum computing swap function, the method comprising:
The subject matter disclosed may best be understood by reference to the following detailed description when read with the accompanying drawings in which:
For simplicity and clarity of illustration, elements shown in the figures are not drawn to scale, and some dimensions are exaggerated to visually emphasize essential features. In particular, NWs and their cross-sections are shown with an exaggerated taper for clarity. In some places, reference numerals are repeated among the figures to indicate corresponding or analogous features.
A goal of the presently disclosed subject matter is to provide a geometry which facilitates the manipulation of Majorana Zero Modes (MZMs). In one embodiment, a tapered nanowire (NW) defines a region wherein topological superconducting regions are present. The tapered structure of the NW facilitates discrete topological superconducting regions. In a case where the NW is not tapered the whole of the NW can be either fully topologically superconducting or non-topologically superconducting. To this end, tapering of NWs can be carried out in many different ways, as disclosed herein. For example, 3-dimensional NWs on surfaces or 2-dimensional gate-defined NWs.
Topological superconductors are a class of superconducting materials characterized by sub-gap zero energy modes, known as MZM (also known as Majorana bound states, or Majoranas).
The term “nanowire” (NW) herein denotes a microscopic structure capable of supporting non-localized topologically 1-dimensional quantum-mechanical properties. The “nano” prefix indicates that the structure has a very small diameter (generally in the order of nanometers), but there are no explicit constraints regarding the overall length of the structure; the structure's length, however, is understood to be many times larger than its diameter. Additional qualifications and descriptions herein further define this term in the context and practice of the present invention.
In one embodiment, the term “tapered NW” herein denotes a NW characterized as geometrically approximating a truncated cone (or “frustum”) having a major (larger area) base and a minor (smaller area) base with respective diameters which are both much smaller than the NW height (or its length, when it is oriented horizontally). As will become clear, the tapering of a NW is not restricted to a 3D frustrum shape, but can also be any shape that is tapered, even in two dimensions. In one embodiment, the tapered NW is flat. In another embodiment the tapered NW is a flat, gate-defined NW. In another embodiment, the tapered NW is gate-defined. Typically, gate-defined wires are produced on substrates and are coupled to 2D electron gases. The orientation of a NW is thus taken to be the orientation of its longitudinal 1-dimensional axis, where the direction of orientation is taken to be the direction from the major base to the minor base. A typical height of a tapered NW (or its length, when it is oriented horizontally) is measured in microns, and typical diameters measure in the range of 50 nm to 100 nm, wherein the minor base diameter is on the order of nanometers to tens of nanometers smaller than the major base diameter. In some embodiments, the terms “nanowire”, “NW”, “nanofilament”, “tapered nanofilament”, “tapered NW” and “nanostructure” are used interchangeably.
In one embodiment, the tapered NW comprises a semiconductor. In one embodiment, the NW consists of a semiconductor. In one embodiment the tapered NW is semiconducting. In one embodiment, the tapered NW comprises a semiconductor with high spin-orbit coupling. In quantum mechanics “spin-orbit coupling” refers to a relativistic interaction between a particle's spin with its motion inside a potential. Non-limiting examples of semiconductors of high spin-orbit coupling include: Indium Arsenide (InAs) and Indium Antimonide (InSb). Other non-limiting examples of NWs include: NWs of metal, semiconductor, or inorganic molecules; and carbon nanotubes. Fabrication and manipulation of tapered NWs are currently available using known techniques. In one embodiment the tapered NW comprises transition-metal dichalcogenides (TMDs). In one embodiment the tapered NW consists of TMDs. In one embodiment the TMD is selected from a group comprising: MoS2, WS2, MoSe2, WSe2, MoTe2 or combinations thereof.
Although examples are shown herein of particular fabricated tapered nanostructures, a principal feature of the presently disclosed subject matter is not bound to the particular structures that are described herein. In one embodiment, the presently disclosed subject matter relates to a tapered NW structure that facilitates the presence of discrete topological superconducting regions with corresponding MZMs. In one embodiment, the tapered NW is a structure that is fabricated on a substrate, as described herein. In another embodiment, the tapered NW structure is a gate-defined tapered nanostructure comprised within a semiconducting material. In one embodiment the terms “semiconductor”, “semiconducting material”, “semiconducting medium” are used interchangeably. In one embodiment, manipulation of Majoranas is facilitated by the tapered NW structure.
In some embodiments the tapered NWs are gate-defined. As used herein “gate-defined” NWs refer to NWs that are produced in a material by means of at least one gate electrode. The use of gate-defined NWs can be extrapolated to any desired shape and device structure, according to the requirements of a particular device optimized to achieve the required topological superconductivity, in two or three spatial dimensions. Typically, gate-defined NWs require coupling to a 2D electron gas (2DEG) on a substrate. In some embodiments a plurality of gate electrodes are used to achieve at least one gate-defined tapered NW. In some embodiments, the gate can be a top, bottom and/or side-gates, used independently or in any combination, to achieve the desired gate-field and/or gate-profile to produce the desired shape of the resulting NW. Gate-defined structures are well known to experts in the art. Thus, all the components required to enable the implementation of gate-defined structures defined herein are considered to be within the scope of the presently disclosed subject matter.
In one embodiment, devices of the present invention operate under cryogenic conditions, at temperatures which support superconductivity in superconducting layer 109. In one embodiment, devices of the present invention operate at any temperature, on condition that discrete superconducting regions form within the tapered NWs of the present invention.
Tapered NW 101 is also in contact with a surface of a 2-dimensional insulating layer 111 along a generating line (not shown) of the external surface of tapered NW 101. A conductive substrate 113, also referred to herein as an ‘electrically-conductive electrode’ or just ‘electrode’, is attached to the opposite surface of insulating layer 111. In one embodiment the insulating layer 111 is a dieletric. In one embodiment the insulating layer 111 is a high-dielectric material Non-limiting examples include silicon oxide, hafnium oxide, zirconium oxide. In one embodiment the insulating layer comprises an oxide. In a further related embodiment, insulating layer 111 is silicon oxide; in an additional related embodiment, electrode 113 is a charge-carrying semiconductor, a non-limiting example of which is doped Silicon; in another related embodiment, substrate 113 is a metal, a non-limiting example of which is Copper. In one embodiment, the substrate 113 is referred to as the substrate. In another embodiment, the substrate refers to the substrate 113 together with at least one insulating layer 111. In one embodiment the silicon is p-type. In another embodiment the silicon is n-type. In one embodiment, the insulating layer 111 is deposited by any of the following techniques: atomic layer deposition (ALD), evaporation, chemical vapor deposition (CVD), inductively coupled plasma (ICP) growth, plasma enhanced CVD, physical vapor deposition, chemical solution deposition, epitaxy, spin-coating or any combinations thereof. In some embodiments there is at least one insulating layer. In other embodiments additional layers are used to enhance adhesion of NWs to the substrate. In other embodiments additional layers are used to enhance coupling of NWs to the substrate.
Substrate 113 is set to ground potential via a connection 121. An adjustable voltage source 115 is connected to tapered NW 101 via a connection 125, and is settable to a tuning voltage VT 117. Varying voltage VT 117 alters the chemical potential of tapered NW 101; an increase of 1 volt in voltage VT 117 increases the chemical potential of tapered NW 101 by approximately 1 MeV. The particular values of the voltage and the chemical potential are non-limiting examples. In a device, these values will be optimized to the materials used, the device structure and requirements of the user. In one embodiment the tapered NW 101 is connected at either end (103 or 105) with a connection 125. In one embodiment, both ends of the tapered NW 101 are connected as a source-drain junction. There are various ways to connect the tapered NW 101 to the connection 125. In one embodiment the tapered NW 101 is connected to the connection 125 via a connecting electrode. In a further embodiment, the connecting electrode is metallic. In another embodiment, the connecting electrode is fabricated by standard evaporation techniques onto at least one end of the tapered NW e.g., as electrode pads. In one embodiment, to produce a device comprising a tapered NW, the electrode pads are bonded (e.g., wire bonded) on a chip. In one embodiment, a device comprising a tapered NW forms at least one element of an integrated circuit. In one embodiment the substrate 113 is biased whereas the other terminal, connection 125 is grounded.
In one embodiment at least one topological superconducting region is formed in a tapered NW. In one embodiment the terms “topological superconducting regions” and “superconducting regions” are used interchangeably. As used herein “superconducting” refers to a set of physical properties that are observed in certain materials where the electrical resistance becomes negligible. In some embodiment the superconducting regions are topologically superconducting.
The length of the superconducting region can be varied and manipulated. Typically, a topological superconducting region typically cannot be shorter than the coherence length of the topological superconducting region. Furthermore, in one embodiment, the topological superconducting regions can be tuned by the tapering angle of the NW. The tapering angle refers to the angle between the NW (or nanofilament) axis 107 and a line extending from the surface of the tapered NW. In one embodiment a large tapering angle provides more discrete topological superconducting regions in comparison with a smaller tapering angle.
In one embodiment the present invention provides a device that comprises a tapered NW that supports discrete topological superconducting regions. Such a device is connected to incorporate a tapered NW, in a three-terminal source-drain-gate device, in some embodiments. In one embodiment the device comprises at least one back gate. In another embodiment the device comprises at least one top-gate. In another embodiment the device comprises at least one top gate and at least one back gate. In one embodiment, the tapered NW is disposed on a semiconducting substrate, separated by an oxide, wherein the tapered NW is connected with electrodes at either end as a source-drain junction. In one embodiment, the substrate is doped. In one embodiment the substrate is n-doped. In another embodiment the substrate is p-doped. In some embodiments, the material comprised in the tapered NW is doped. Applying a potential difference between the two terminals (i.e., a source-drain) connected at each end of the tapered NW, induces electron transport across the tapered NW. In some embodiments the electrodes connected to the ends of the tapered NWs are made of a conductive material. In some embodiments the electrodes further comprise an adhesion layer. In some embodiments, the electrodes further comprise an additional coupling layer. In some embodiments, the electrodes further comprise an additional insulating layer. Applying a gate modulates the electron transport through the tapered NW. In one embodiment the connecting electrodes are fabricated by evaporation onto either end of the tapered NW. In another embodiment, the connecting electrodes are fabricated by standard evaporation techniques onto at least one end of the tapered NW e.g., as electrode pads. In one embodiment, to produce a device comprising a tapered NW, the electrode pads are bonded (e.g., wire bonded) on a chip. In one embodiment, a device comprising a tapered NW forms at least one element of an integrated circuit.
In one embodiment the device further comprises side gates. Side gates are typically used to form tunnel junctions across the NW to measure spectroscopy.
In one embodiment the device further comprises at least one of the following additional materials: additional superconducting materials, non-superconducting materials, doped materials, semiconducting materials, dielectric materials, oxide materials, insulating materials, metals, 2DEGs, electron conductors, hole conductors, polymers or any combinations thereof.
According to embodiments of the present invention, the tapering of the tapered NWs is the physical 3-dimensional NWs which provides the discrete regions described above, and permits topologically superconductive regions to exist in a NW—and hence to support Majorana Zero Modes-without requiring tuning parameters to be exactingly precise. In one embodiment, tapered NWs are gate-defined. Therefore, embodiments of the present invention greatly facilitate quantum computing based on MZM-implemented qubits. In addition, embodiments of the present invention also provide further mechanisms to support quantum computing, as disclosed herein.
By adjusting a tuning voltage VT 207 the locations of the discrete regions of topological superconductivity may be changed, as shown by arrows 205. The term “advance” herein denotes moving a region of topological superconductivity in the forward direction of the orientation of the tapered NW; the term “retract” herein denotes moving a region of topological superconductivity in the reverse direction of the orientation. In particular, increasing tuning voltage VT 207 advances regions 211 and 221; decreasing tuning voltage VT 207 retracts regions 211 and 221. It is appreciated that the Majorana Zero Modes on the boundaries of the topologically superconductive regions also move in the same fashion. According to certain embodiments of the present invention, this property of tapered NWs provides a means of moving MZMs from one location to another, without disrupting or altering them.
The formation of a tapered NW cross can be carried out in many ways. In one embodiment, two tapered NWs, disposed on a substrate, cross each other. In another embodiment, two tapered NWs emanating from a substrate, cross each other above the substrate. In another embodiment two kinked NWs cross each other, forming a tapered NW cross. In this embodiment, the two kinked NWs can intersect each other at any point along the kinked NW, as long as the projected orientation of each tapered NW portion that crosses is substantially orthogonal.
Kinked Tapered NWs or Nanoflags and Methods of their Production Thereof
Kinked tapered NWs (also referred to as “nanoflags” herein) are used, in one embodiment, to provide crossed tapered NWs. In such an embodiment the crossing of kinked tapered NWs can be at any location along the kinked tapered NW as long as the projected orientation of each tapered NW is substantially orthogonal (see
In one embodiment a kinked tapered NW comprises a semiconductor. In another embodiment the kinked tapered NW consists of a semiconductor. In one embodiment a kinked tapered NW comprises a semiconductor with a high spin-orbit coupling. In another embodiment the kinked tapered NW consists of a semiconductor with a high spin-orbit coupling. In one embodiment the material comprising the kinked tapered NW is selected from InAs or InSb. In one embodiment the tapered NW comprises a doped semiconducting material.
It is important to note, as mentioned herein, that crossed tapered NWs can be formed in many different ways. The present disclosure provides several non-limiting examples and tapering NWs but is not limited to the present examples alone. Generally, tapered NWs can be disposed on a surface, but they can also be embodied as gate-defined structures. The invention is not limited to the method in which such tapering, or crossing is achieved; all of which are considered within the scope of the presently disclosed subject matter.
In one embodiment, kinked NWs are produced by molecular beam epitaxy (MBE). In some embodiments “kinked NWs” are also referred to as “kinked tapered NWs”. More specifically, and in another embodiment, kinked NWs are produced in Au-assisted vapor liquid solid (VLS) MBE. First, a semiconducting substrate is provided. In one embodiment, the semiconducting substrate comprises InAs or InSb. In another embodiment, the semiconducting substrate consists of InAs or InSb. In one embodiment the orientation of the semiconducting substrate is selected from (100), (111) or (001). In some embodiments, the substrate is doped. In some embodiments the substrate is n-doped. In other embodiments the substrate is p-doped. In some embodiments, the substrates is cleaned in organic solvents before any deposition processes. In some embodiments, the substrate is cleaned by plasma ashing and/or UV-ozone surface treatment. After cleaning, and in one embodiment, before placing the substrate in the MBE chamber, the substrate undergoes oxide blow-off. A thin film (also referred to herein as a layer) of a catalyst, for example Au, is then evaporated onto the substrate. In one embodiment the Au-layer has a thickness of less than 1 nm. In other embodiments the thickness of the Au-layer ranges between 1-2 nm. in other embodiments the thickness of the Au-layer ranges between 2-10 nm. In some embodiments the Au deposition produces a discontinuous layer of gold on the surface of the substrate. In other embodiments the Au deposition produces Au droplets on the surface of the substrate. In other embodiments the Au deposition produces a continuous layer on the surface of the substrate. In some embodiments the substrate, comprising the Au-film is further annealed.
Next, the Au-comprising substrate is heated to an elevated temperature. The temperature of the elevated temperature will be different for each substrate and material that is used; the temperature should be optimized for each material and substrate. In one example, InAs substrates coated with thin Au films are initially heated to about 600° C. In a further embodiment, the elevated temperature occurs under As overpressure. The material used in the overpressure will depend on the NW and substrate material used. In one embodiment the As/In overpressure is about 100. In one embodiment the As/In overpressure is about. In one embodiment the As/In overpressure is about. The substrate is subsequently cooled by about 100° C. after which an In shutter is opened. In one embodiment the rate of cooling at this stage is about 100° C. per hour. At this stage, and in one embodiment, patterns form on the substrate, for example on the surface of an InAs substrate, which comprises facets oriented in two opposite directions e.g., two opposite (111) facets. In some embodiments, the substrate is patterned such that it comprises multiple facets and/or facets oriented in opposite directions. In one embodiment the NWs emanating from the Au nucleation sites are rounded. NWs then emanate from the Au nucleation sites (or whichever catalyst is used), i.e., sites on the Au-film, in two opposite directions. Thus far, the method provides a method of producing uni-directional NWs.
In one embodiment, lowering the temperature of the MBE process changes the direction of growth of the NW, causing a kink in the growing NW. In one embodiment the change of temperature required to cause a kink in a NW is 100° C. In one embodiment the change of temperature required to cause a kink in a NW is 200° C. In one embodiment the change of temperature required to cause a kink in a NW is 300° C. In one embodiment, to change the direction of growth of the NWs the temperature is lowered by about 100° C., for example from 500 to 400° C. In one embodiment the rate at which the temperature is lowered is 10° C. per minute until a temperature of 300° C. is reached. At this final temperature, and in one embodiment, the NW growth is maintained for 1 to 2 hours. In some embodiments, the temperature is maintained for 2 to 5 hours.
This section discloses methods of producing kinked tapered NWs. In one embodiment this same process also produces crossed kinked tapered NWs. Some of the kinked tapered NWs will intersect forming crossed kinked tapered NWs. In one embodiment, the yield of produced crossed kinked tapered NWs is increased by optimizing the channels of growth of NWs along facets on the substrate. In one embodiment the yield of produced crossed kinked tapered NWs is increased by optimizing the temperature, rate of cooling, starting and finishing temperature, duration at a particular temperature or a combination thereof.
According to certain embodiments of the invention, a uniform external magnetic vector field {right arrow over (B)} 321 is applied by a magnet 325 whose strength and orientation are adjustable. In one embodiment the magnet field is provided by a permanent magnet. In another embodiment the magnetic field is provided by an electromagnet. In one embodiment the magnet is provided with a means to point in different directions In one embodiment the magnet is provided with a means to rotate. Typical values of the magnitude of magnetic field {right arrow over (B)} 321 are in the hundreds to thousands of Gauss but must not be strong enough to quench the superconductivity of the superconducting layer (layer 109 in
It is noted that the sequence of superconducting region retracting resulting from steps in
Methods of braiding MZMs are detailed herein wherein the key component is the use of crossed tapered semiconducting NWs. In order to realize the braiding of said MZMs the presently disclosed subject matter provides a device comprising at least one crossed tapered NW. As schematically illustrated in
Four conductive pads 320 shown, positioned at both ends of tapered NW 301 and tapered NW 305. In one embodiment the conductive pads comprise a metallic material. In one embodiment the conductive pads consist of metallic material. In one embodiment the conductive pads further comprise an adhesion later. In one embodiment the conductive pads are wire bonded in a permanently contacted device. In one embodiment the device 400 forms one element of an integrated circuit. In one embodiment the device 400 forms one element of a printed circuit board (PCB).
The device 400 comprising the crossed tapered NW 300 is set on a substrate, embodiments of which are described herein. For the sake of clarity and simplicity of
In some embodiments, crossed tapered NW 300 in the quantum computing device 400 is a gate-defined crossed tapered NW. An expert in the art is familiar with how to achieve gate-defined nanostructures. In one embodiment the gate-defined nanostructures are coupled to a 2D electron gas (2DEG). In some embodiments, the device 400 comprise a magnet 325 whose strength and orientation are adjustable.
In the presently disclosed subject matter, tapered NWs that also host an atomic-scale superstructure on their surfaces have been disclosed. Intriguingly, these provide two complementary methods for engineering the Kramer's degeneracy within the vicinity of the chemical potential. First, a periodic superlattice potential folds the sub-band spectrum. This gives rise to additional Kramer's degeneracies at the edges of the folded Brillouin zone (
Tapered NW crosses provide a route to perform braiding operations with the minimal required number of gates (see
Tapered, so-called nanoflags, InAs NWs that host an atomic-scale superstructure on their surfaces are presented. The present subject matter discloses their growth and electronic structure. InAs NWs, which nucleate on a (001) surface with a pure wurtzite (WZ) structure, are forced to diverge from the direction by experiencing low temperature and high supersaturation. The new growth direction induces a change from WZ structure with a typically rounded shape to a zinc-blende (ZB) tapered rectangular nanoflag with two broad (011) facets. This rectangular shape enables careful STM measurements of the (011) surface of the nanoflag. Studies using SEM, TEM, and STM were correlated and supported by kinetic Monte Carlo MC simulations, shedding light on the unique surface structures composed of ordered rows of atoms. In the tapered NWs, the quantized spectrum evolves with the varying NW diameter. The tapered global structure and the microscopic superstructure provides two complementary methods for engineering the Kramer's degeneracy to within the vicinity of the chemical potential. Thus, nanoflag InAs NW structures are suitable platforms for the search and manipulation of MZMs.
Kinked InAs NWs were grown by Au-assisted vapor-liquid-solid (VLS) molecular beam epitaxy (MBE) on the (001) plane, which produced rounded reclining NWs that emerged in two opposite (111) directions (see
The rectangular nanoplate that forms after the kink is characterized by two narrow facets (about 40 nm thick) and two broad facets, as shown in
A broad neck with occasional diagonal double twin planes (TP) forms between the WZ stem and the ZB nanoplate (see
These NWs resemble so-called nanoflags. Occasional crosses form by the intersection of two nanoflags (
To explain the shape and structure of the kinked InAs NWs, their growth was simulated using the MC method. Simulations start by assuming an external flux of particles approaching the surface with given frequency. As the VLS growth of the InAs NWs in MBE is conducted at a high As overpressure, it is assumed that indium is the element that fully controls the growth. Thus, in the calculations the external flux consists of only one type of particle, i.e., indium atoms. The In adatoms diffuse along the surface and can either nucleate, creating clusters, or attach to steps that exist on the surface. Each of these processes is governed by a different probability. An increased probability for forming clusters is assumed on a 20 lattice units wide part of the surface to simulate the presence of a gold droplet, which catalyzes the NW growth. It is also assumed that the diffusing particles can easily climb up a step on the surface but that coming back is forbidden. In such a way the process of capturing adatoms is modelled on the part of the surface simulating the gold spot. NW growth starts from the nucleation of a seed consisting of four neighboring In atoms on the flat surface within the gold droplet. Each new layer on top of the growing NW also starts with a seed of nucleation. Such a modeling scheme allows simulation of the process of Au-assisted NW growth.
In this present disclosure, the growth of a NW vertical to the (111) surface is first simulated, forming a WZ structure. The attachment of adatoms on the hexagonal top of the NW is equally probable in all six directions, with the rate of 0.09. In the simulation, this NW was grown along the [0001] axis for 33 000 MC steps. As a result, a 180 lattice units high regular hexagonal NW was obtained. Next the NW is bent in that lowering the temperature changes the balance between the free energy of the gold droplet and the chemical potentials of different surfaces. Thus, the gold droplet can move to the side of the NW. The new NW beneath such a gold spot would grow in a different direction with respect to the original one. To include this process into the calculations, the area that simulates the gold droplet is moved to the side of the NW and the whole structure was rotated to have the vertical axis in the [311] direction. Then, performing the growth process upward, a kinked NW is obtained pointing in a direction laying between the [311] and [100] axes (
The obtained rectangular cross-section of the nanoflag with its flat facets renders the kinked NWs highly suitable for scanning tunneling microscopy (STM) studies. NWs were harvested onto an Au substrate and transfer in a designated ultrahigh vacuum suitcase. The results of the STM measurements showing the topography and demonstrating the impact of tapering on its energy spectrum are presented in
The tapered topography of the NWs is clearly visible in
Detailed NW boundaries were modelled along this segment (
STM topography further discovered a self-ordered atomic pattern at the surface of the kinked NWs. It consists of four-atom chains that form rather regular rows (
To test the hypothesis that the patterns at the InAs (110) surface of the nanoflags are related to As adatoms, minimization procedure was performed within the LAMMPS molecular dynamics simulator Tersoff potential. For this procedure, a crystal composed of 12×12×8 atomic layers with a ZB structure and atomic distances typical of InAs was arranged. The top surface was a (110) plane, over which 144 As adatoms were placed in regular rows. The number of additional As atoms is equal to the number of atoms in one monolayer. The initial arrangement is shown in
In
Remarkably, a 4 unit cell potential induces the Brillouin zone folding needed to have a Kramer's degeneracy right at the vicinity of the chemical potential in InAs NWs. Hence, its presence fully alleviates the need to further tune the chemical potential or will at least substantially reduce the amount of tuning needed. The combination of superlattice folding with mild tapering may be ideal to maximize the benefit of both.
The high purity InAs kinked NWs were grown by Au-assisted vapor liquid solid (VLS) molecular beam epitaxy (MBE) in a Riber 32 system with vacuum in the low 10−11 Torr. A very thin (<1 nm) layer of Au was evaporated in-situ on the (001) InAs at ˜100° C. right after oxide blow-off in a separate chamber attached to the MBE growth chamber. For the general NWs growth on the (001) the substrate was first heated to ˜600° C. under arsenic overpressure (As/In ˜100), where the gold droplets form, then gradually cooled to the growth temperature ˜400° C. Midway between the two temperatures the In shutter (˜5e-7) was opened. During this cool down process, the (001) surface initially becomes covered with craters comprised of two opposite (111) facets, which facilitate the nucleation of typically rounded NWs that grow in two opposite directions. NWs growth in the direction is maintained for an hour after which the substrate temperature is reduced by 100° C. at a rate of 10° C. per minute while growth continues all the way to ˜300° C. The low temperature growth continued for 1-2 hours for different samples in order to extend the “plate” length.
Since the nanoflag NWs orient in various directions (
Consequently, the rotation results in an enlarged topological segment on one arm and a shrinking segment on the other, respectively. Combination of both enables the following braiding sequence, sketched in
Regarding
In one embodiment, the term “a” or “one” or “an” refers to at least one. In one embodiment the phrase “two or more” may be of any denomination, which will suit a particular purpose. In one embodiment, “about” or “approximately” may comprise a deviance from the indicated term of +1%, or in some embodiments, −1%, or in some embodiments, 2.5%, or in some embodiments, ±5%, or in some embodiments, ±7.5%, or in some embodiments, ±10%, or in some embodiments, ±15%, or in some embodiments, ±20%, or in some embodiments, ±25.
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/IL2022/051178 | 11/7/2022 | WO |
Number | Date | Country | |
---|---|---|---|
63276623 | Nov 2021 | US |