a is a schematic diagram of a frequency dependent input stage which implements the frequency component of the second term in a Taylor series expansion as described herein.
b is a schematic diagram of a frequency dependent input stage which implements the frequency component of the third term in a Taylor series expansion as described herein.
c is a schematic diagram of an input stage which implements the first term in a Taylor series expansion as described herein.
a is a schematic diagram of a mixer circuit which implements the weighting factor component of the second term in a Taylor series expansion as described herein.
b is a schematic diagram of a mixer circuit which implements the weighting factor component of the third term in a Taylor series expansion as described herein.
c is a simplified schematic diagram of a summing circuit as might be used by an equalization scheme per the present invention.
It is known from transmission line theory that the impedance of a good conductor increases by the square root of frequency due to the skin effect. The equation describing the frequency response of a good conductor is given by:
H(f)=e−kl(1+j)√{square root over (f)} (1)
where k is a constant dependent on the physical parameters of the conductor, l is the length of the conductor, and f is the frequency of the signal. Therefore, to provide equalization which restores the magnitude fidelity of the input signal, a system with a frequency response equal to |H−1(f)=e−kl(1+j)√{square root over (f)}| is needed.
Here, |H−1(f) | is obtained by using the Taylor series expansion for an exponential:
This equation is an infinite series, and the concept presented herein can be extended to include any number of terms, depending on the level of accuracy needed. The first three terms are generally sufficient for a typical application. Expanding equation 1 using equation 2 results in the following (first three terms only):
Equation 3 shows a first term (“1”) which is constant with frequency, a second term (kl√{square root over (f)}) which is proportional to the square root of f, and a third term
which is proportional to f. Inverse frequency response |H−1(f)| will be dominated by one of the three terms, depending on the frequency. From equation 3 it is seen that, for accurate compensation at different conductor lengths, all terms of the Taylor expansion higher than the first (constant) term should be multiplied by a weighting factor that varies with conductor length. Here, the weighting factors for the second and third terms are proportional to kl and k2l2, and thus vary with the length l of the conductor. By using the Taylor series expansion as the basis for the equalization, and then explicitly separating the terms of equation 3 and multiplying them by different weighting factors that vary with line length, highly accurate equalization can be achieved.
The outputs of frequency modules 14 and 16 are provided to “weighting factor” modules 18 and 20, respectively, which serve to multiply a received frequency component with a weighting factor that varies with conductor length. As noted above, the weighting factors for the second and third terms of the Taylor series expansion are proportional to kl and k2l2; these values are represented in
The outputs of modules 12, 18 and 20 are summed with a summing circuit 22, and then preferably buffered with an amplifier 24 and outputted as a single-ended voltage Vout. In this exemplary embodiment, Vout is referred to a reference voltage Vref, discussed below.
The Taylor series expansion shown in equation 3 can be realized with a frequency response H(s) equal to:
in which the first, second and third terms within the parentheses correspond to the constant-with-frequency, the √{square root over (f)}, and the f terms of equation 3, respectively, with ‘A’ varying with conductor length, and s=j2πf.
As explained in more detail below, H(s) is formed by (1) applying the input signal voltage across the impedances defined by the right side of equation 4 to form currents with the needed frequency characteristics, (2) developing the proper “weighting” of those currents by taking the needed portion of each current based on the value of Vpeak, which varies with conductor length, (3) summing the weighted currents, and (4) converting the summed currents to a voltage, typically by running the summed currents through a resistor having value Rs.
Here, the √{square root over (f)} term (corresponding to frequency module 14) is approximated with a piece-wise linear sum of n zero-pole pairs. One possible way of implementing frequency module 14 is shown in
Frequency module 16 may be similarly implemented; one possible embodiment is shown in
One possible embodiment of frequency module 12 is shown in
In practice, the RC product in the third (linear) term is much smaller than the RC products in the second (square root) term, so the pole that levels out the decrease in impedance affects the response at a much higher frequency. In a typical frequency range of interest, the third term can be treated as just linear (sC). The series resistance for module 16 is the sum of the two resistors connected in series with the capacitor, which is typically quite small relative to the resistors in
A plot illustrating the contributions of the frequency modules 12, 14 and 16 to frequency response H(s) is shown in
The differential output currents of frequency modules 14 and 16 are provided to weighting factor modules 18 and 20, respectively, which multiply the incoming currents by respective weighting factors as discussed above. The weighting factor modules are preferably mixer circuits that steer the differential currents in response to control voltage Vpeak, which varies linearly with line length.
Control voltage Vpeak is typically a user-provided value. For example, the present equalization system could be arranged such that line lengths of 25, 50, 75 and 100 meters have corresponding Vpeak values of 0.25, 0.5, 0.75 and 1.0 volts. When so arranged, the present scheme can provide equalization which is accurate at any line length, just by changing the value of Vpeak.
One possible implementation of weighting factor module 18 is shown in
Difference current I2−I1, a copy of current I1, and a current Isig1 given by Ioutp1−Ioutn1 are fed into a current steering circuit block 50, which determines from the ratio of I2−I1 to I1 how much input current to steer to the output Iout1, and how much to discard (Idiscard1). As shown in
and Idiscard is given by:
A possible implementation of weighting factor module 16 is shown in
Current I2=Vpeak,max/R is generated as in
Difference current I2−I1(sq), a copy of current I1(sq), and a current Isig2 given by Ioutp2−Ioutn2 are fed into a current steering circuit block 60, which determines from the ratio of I2−I1(sq) to I1(sq) how much input current to steer to the output Iout2, and how much to discard (Idiscard2). As shown in
and Idiscard2 is given by:
As shown in
The summed currents (Isum) are provided to a buffer amplifier 24, for conversion to a voltage as mentioned above. Amplifier 24 is preferably a current feedback amplifier, though other amplifier types could also be used. One possible embodiment of such an amplifier is shown in
The present equalization scheme is suitably employed as part of an analog equalizer. However, the present scheme could possibly improve the bit error rate of a digital equalizer as well.
The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.
This application claims the benefit of provisional patent application No. 60/828,371 to Lu, filed Oct. 5, 2006.
Number | Date | Country | |
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60828371 | Oct 2006 | US |