Claims
- 1. A circuit providing shared access for a plurality of access requesting devices individually having an input and at least one output, to an electronic device having a output and at least one input, comprising:
- means responsive to a clock signal, for generating a select signal having a plurality of voltage levels uniquely corresponding to respective ones of said plurality of access requesting devices;
- a first multiplexer circuit having a select input receiving said select signal, a plurality of inputs respectively connected to corresponding outputs of said plurality of access requesting devices, and an output connected to a corresponding one of said at least one inputs of said electronic device; and
- a demultiplexer circuit having a select input receiving said select signal, an input connected to said output of said electronic device, and a plurality of outputs respectively connected to corresponding inputs of said plurality of access requesting devices.
- 2. The circuit as recited in claim 1, wherein said output of said electronic device is a data output, said at least one input of said electronic device includes a data input, said input of individual ones of said plurality of access requesting devices is a data input, said at least one output of individual ones of said plurality of access requesting devices includes a data output, said plurality of inputs of said first multiplexer circuit are respectively connected to corresponding data outputs of said plurality of access requesting devices, said output of said first multiplexer circuit is connected to said data input of said electronic device, said input of said demultiplexer circuit is connected to said data output of said electronic device, and said plurality of outputs of said demultiplexer circuit are respectively connected to corresponding data inputs of said plurality of access requesting devices.
- 3. A method of sharing access to an electronic device having an output and at least one input, between a plurality of access requesting devices individually having an input and at least one output, comprising the steps of:
- generating a select signal having a plurality of voltage levels uniquely corresponding to respective ones of said plurality of access requesting devices, such that a voltage level of said select signal changes to a different one of said plurality of voltage levels in response to a clock signal;
- connecting a multiplexer circuit responsive to said select signal, between said electronic device and said plurality of access requesting devices such that inputs of said multiplexer circuit are connected to corresponding outputs of said plurality of access requesting devices and an output of said multiplexer circuit is connected to a corresponding one of said at least one inputs of said electronic device; and
- connecting a demultiplexer circuit responsive to said select signal, between said electronic device and said plurality of access requesting devices such that an input of said demultiplexer circuit is connected to said output of said electronic device and outputs of said demultiplexer circuit are connected to corresponding inputs of said plurality of access requesting devices.
- 4. The method as recited in claim 3, wherein said select signal generating step comprises the step of generating a select signal having a plurality of monotonically increasing voltage levels uniquely corresponding to respective ones of said plurality of access requesting devices.
- 5. The method as recited in claim 3, wherein said select signal generating step comprises the step of generating a select signal having a repetitive pattern of a plurality of monotonically increasing voltage levels uniquely corresponding to respective ones of said plurality of access requesting devices.
- 6. The method as recited in claim 3, wherein said select signal generating step comprises the step of connecting said clock signal to an input of a frequency divider circuit, and generating a select signal at an output of said frequency divider circuit in response thereof.
- 7. The method as recited in claim 3, wherein said select signal generating step comprises the step of connecting said clock signal to an input of a resettable counter circuit, and generating a select signal at an output of said resettable counter circuit in response thereof.
Parent Case Info
This is a continuation of application Ser. No. 07/981,889, filed Nov. 25, 1992 U.S. Pat. No. 5,471,588.
US Referenced Citations (19)
Continuations (1)
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Number |
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981889 |
Nov 1992 |
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