This invention relates to a wafer structure and method to manufacture thin strip silicon solar cells.
Silicon materials are major parts of cost for silicon solar cells. It is an efficient way to reduce the cost of solar cells by using less silicon materials.
In US Patent “Semiconductor processing method for increasing usable surface area of a semiconductor wafer” (U.S. Pat. No. 7,595,543, Sep. 29, 2009), a number of ways were used to cut thin strips from semiconductor silicon wafers for increasing surface area to receive sun light. The most efficient way to form Si strips was wet anisotropic etching of (110) oriented Si wafers. A protective layer silicon nitride or silicon dioxide was deposited on (110) oriented Si wafers. Lithography processing and etching were used to form gratings windows on the wafers surface. The Si wafers were etched through in KOH solution at elevated temperatures. The width of the formed silicon strips is typically 1 mm and their thickness could be as thin as ten's microns while the length is over 10 centimeters. The silicon strips were supported by a protective frame. The silicon strips connected on protective frames can be further processed for fabrication of solar cells and assembling as solar cell modules. The effective area of solar cells for absorption of solar light was greatly increased and much less expensive silicon materials were used. However, the wafer structures and processing method for cutting thin silicon strips and fabrications remain numbers of technical challenges. Firstly, the silicon wafers can not be uniformly etched through on whole wafer area. The depth variation of etched deep grooves ranges up to hundreds microns for 1-mm thick wafers. It is difficult to process the uneven structures of etched silicon strips for fabrication of solar cells. Secondly, the elongate thin silicon strips are easily adhered together each other. It is very difficult to uniformly diffuse dopant chemical elements into adhered silicon strips. The properties and performance of solar cells were seriously affected by non-uniform diffusions for fabrication of p-n junctions. More seriously, it is very hard to separate the adhered silicon strips for following assembling. The processing cost was increased although the adhesion of silicon strips may be removed by fabrication of interconnecting portions connecting adjoining strips on rear side of silicon wafers. Thirdly, a frame comprising the periphery of the semiconductor wafer was used to connect and mechanically support each strip. The thickness of the frame is the same as the one of the wafer and the width is typically 5 mm The considerable amount of silicon materials was used to form the frame which is useless for fabrication of solar cells. Further, there exists an overlap region for p-type and n-type semiconductors to form a p-n junction as a solar cell. Carriers heavily compensate on the overlap region. Significant loss was induced and fill factor of cells was reduced because of the minor carrier recompensation on the overlap region. Finally, photolithography has to be used for processing to define patterns. The cost for fabrications of solar cells was greatly increased.
It is an objective of present invention to disclose a semiconductor wafer structures for fabrication of solar cells.
Another object of the present invention is that a processing method is disclosed to form planar layers on uneven surface and structure of trenches for wafers as protective and sacrificial film layers for etching of semiconductor materials and selective deposition metal film layers.
It is a further object of present invention that new thin solar cells provide efficient, inexpensive and convenient solution to electric power generation applications.
According to the invention, deep trenches are formed on semiconductor wafers. The wafers are partially etched and the bottom surfaces of grooves are uneven. Plurality of strips is formed on the wafers. The remained thin layer of wafer materials mechanically support and connects adjoining strips.
Another embodiment of present invention is that thin film layers of materials such as polymer, wax or dielectric oxide are sintered on bottom surfaces of trenches. The layers of films are formed by filling of solutions on the trenches followed with evaporation drying.
Another embodiment of present invention is that nanometers structures are fabricated on the surfaces of strips. In this manner, reflection of lights is greatly reduced on the surface of strips.
Present invention also disclosed a method to separate p-type and n-type semiconductors from conductive electrodes with high spatial resolution.
Present invention also disclosed a method to form nickel silicide as conductive electrodes of solar cells.
A better understanding of the invention will obtained by reference to the detailed description below, in conjunction with the following drawings, in which:
(110) oriented single crystalline Si wafers 10 are used. The wafer 10 can be circle shape as shown in
In accordance with the invention, referring to
Reflectivity of bare optical smooth silicon surfaces in air is ˜34% at solar wavelength. The high reflection greatly reduced energy conversion efficiency of solar cells. The surface of strips 11 are textured with nanometers structure as an antireflection layer (ARC). The amplified nanometers structured antireflection layer (ARC) 32 is shown in
A layer of metal nickel was selectively deposited on top of said silicon strips. The said silicon wafers deposited with metal Ni was heated up on 400° C. for 30 minutes. Part of nickel penetrated through said oxide layer into silicon. A layer of nickel silicide was formed on said silicon strips to reduce contact resistances. The metal nickel and nickel silicide 40 was used as one of electrodes for solar cells, as shown in
Multi-layers of films were deposited on the bottom of said trenches for fabrication of solar cells. The first layer of film 50 was deposited on the bottom of said trenches to flat the uneven bottom surfaces of the trenches, as shown in
The material for film 50 is beeswax with low melting temperature Tm˜62° C. The wax on the bottom of said trenches can be heated up to melting temperature to reflow for further leveling and smoothing of the said film.
The second layer of film 60 in
The preferred material for film 60 is styrene-isoprene-styrene block copolymer. The typical solvent of styrene-isoprene-styrene block copolymer is toluene.
Afterwards, the trenches and front surface of said wafers was covered with a polymer 70 as shown in
Usually, a dopant such as boron or phosphor is diffused into silicon to change polarity of semiconductor materials for formation of p-n junction at high temperature over 900° C. A protective dielectric film is often coated on the area of silicon material for selectively doping. However, it is very difficult to diffuse the dopant into semiconductor material with high spatial resolution at such high temperature. The adjacent area of silicon material coated with a protective dielectric film near the diffusion source is often diffused with the dopant on some extent. This effect greatly reduces the open circuit voltage of the formed p-n junction. Doping semiconductor with high spatial resolution is essential for formation of a p-n junction since the physical size of the strips is often limited. The spatial sharpness of p-type and n-type silicon material is implemented by etching away the diffused layer at room temperature as released on present invention, as discussed in following section. Further, metal electrode of p-type semiconductor should be not connected with electrode of n-type semiconductor or n-type semiconductor itself. Otherwise, shunt paths will exist and performance of solar cell will be degraded. Selective deposition of metal electrode films is often implemented by photolithography processing technique. This will greatly increase fabrication cost of the solar cells. A sacrificial layer is used to eliminate the shunt path of electrodes in present invention. The process is much simpler than the ones used in lithography processes. Fabrication cost is greatly reduced.
The said wafer with protected front surfaces is immersed in a solution for etching away the silicon near the rear surface. The solution of etching silicon is mixed HF (5 wt. %):HNO3 (95 wt. %). Exposed silicon is etched away at room temperature. The etching is stopped when the surface 72 of silicon is from the surface 71 of material 70 with distance ds, as shown in
The cross section view of formed single strip solar cell is shown in