Claims
- 1. A system comprising:
a first substrate configured to provide a plurality of unique identifiers corresponding to a plurality of locations on the first substrate; a plurality of connectors coupled to the first substrate at the plurality of locations, each connector comprising a unique identification device configured to receive the corresponding unique identifier; and a plurality of second substrates, each second substrate coupled to a corresponding connector such that the unique identification device couples the corresponding unique identifier to the second substrate.
- 2. The system, as set forth in claim 1, wherein the first substrate is configured to receive five connectors.
- 3. The system, as set forth in claim 1, wherein each connector comprises a memory cartridge connector.
- 4. The system, as set forth in claim 1, wherein the first substrate is configured to receive an array of connectors arranged in a plurality of rows and columns.
- 5. The system, as set forth in claim 4, wherein each connector comprises a memory cartridge connector.
- 6. The system, as set forth in claim 1, wherein each unique identification device comprises a plurality of contacts configurable to be coupled to one of a logical high signal and a logical low signal.
- 7. The system, as set forth in claim 6, wherein each unique identification device comprises three contacts configurable to be coupled to one of a logical high signal and a logical low signal.
- 8. The system, as set forth in claim 1, wherein the unique identifier represents a physical location of the corresponding connector with respect to the first substrate.
- 9. The system, as set forth in claim 1, wherein the unique identifier represents an electrical location of the corresponding connector with respect to the first substrate.
- 10. The system, as set forth in claim 1, wherein each of the plurality of second substrates comprises a plurality of memory modules.
- 11. The system, as set forth in claim 10, wherein each of the plurality of memory modules comprises a plurality of memory devices.
- 12. The system, as set forth in claim 10, wherein each of the plurality of second substrates comprises a memory controller.
- 13. A system comprising:
a first substrate; and a plurality of connectors coupled to the first substrate and configured to receive a plurality of second substrates, each connector comprising a plurality of unique identification devices configured to electrically couple a plurality of electrical signals representative of a unique identifier to a corresponding second substrate, the electrical signals being received from the first substrate and the unique identifier representing a location of the corresponding connector on the first substrate.
- 14. The system, as set forth in claim 13, wherein the first printed circuit board is configured to receive five connectors.
- 15. The system, as set forth in claim 13, wherein each connector comprises a memory cartridge connector.
- 16. The system, as set forth in claim 13, wherein the first substrate is configured to receive an array of connectors arranged in a plurality of rows and columns.
- 17. The system, as set forth in claim 16, wherein each connector comprises a memory cartridge connector.
- 18. The system, as set forth in claim 13, wherein each unique identification device comprises a plurality of contacts configurable to be coupled to one of a logical high signal and a logical low signal.
- 19. The system, as set forth in claim 18, wherein each unique identification device comprises three contacts configurable to be coupled to one of a logical high signal and a logical low signal.
- 20. A system comprising:
a first substrate configured to provide a plurality of unique identifiers corresponding to a plurality of locations on the first substrate; and a plurality of second substrates coupled to the first substrate and configured to receive a corresponding unique identifier corresponding to a plurality of locations on the first substrate.
- 21. The system, as set forth in claim 20, wherein the first substrate is configured to receive five second substrates.
- 22. The system, as set forth in claim 20, wherein the first substrate is configured to receive an array of second printed circuit boards arranged in a plurality of rows and columns.
- 23. The system, as set forth in claim 20, wherein each of the plurality of second substrates comprises a plurality of memory devices.
- 24. The system, as set forth in claim 23, wherein each of the plurality of second substrates comprises a device configurable to control the plurality of memory devices.
- 25. A method of identifying the location of a substrate in a system comprising the acts of:
(a) providing a first substrate; (b) coupling a plurality of connectors to the first substrate, the connectors each comprising a plurality of contacts; (c) electrically coupling each of the plurality of contacts to the first substrate; (d) providing a logical signal to each of the plurality of contacts, the logical signals providing a unique identifier for each of the plurality of connectors; (e) coupling a plurality of second substrates to the plurality of connectors; (f) electrically coupling the plurality of second substrates to the plurality of contacts; and (g) latching the plurality of logical signals of the plurality of contacts to a plurality of control devices existing on the plurality of second substrates.
- 26. The method, as set forth in claim 25, wherein act (b) comprises the act of coupling five connectors to the first substrate.
- 27. The method, as set forth in claim 25, wherein act (b) comprises the act of coupling a plurality of connectors to the first substrate, the connectors each comprising three contacts.
- 28. The method, as set forth in claim 25, wherein act (b) comprises the act of coupling a plurality of connectors to the first substrate, the connectors arranged in a plurality of rows and columns.
- 29. The method, as set forth in claim 25, wherein act (b) comprises the act of coupling a plurality of memory cartridge connectors to the first substrate.
- 30. The method, as set forth in claim 25, wherein act (d) comprises the act of providing one of a logical high signal and a logical low signal to each of the plurality of contacts.
- 31. The method, as set forth in claim 25, wherein act (e) comprises the act of coupling a plurality of memory cartridges to the plurality of connectors.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application claims priority under 35 U.S.C §119(e) to provisional application Ser. No. 60/177,826 filed on Jan. 25, 2000.
Provisional Applications (1)
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Number |
Date |
Country |
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60177826 |
Jan 2000 |
US |