Patent Application
20070260907
1. Field
The present disclosure pertains to the field of computing and computer systems, and, more specifically, to the field of timer management in computing devices or systems.
2. Background
In some prior art computer systems and electronic devices, such as microprocessors, may contain circuits, such as a timer, to maintain a running numerical count for use by other logic or devices within the computer system or electronic device. For example, a timer may be used in a microprocessor to count time between events or to maintain a real-time clock.
On occasion, a timer may need to be updated with a new value by a user or some program running within a computer system. For example, in some prior art techniques, a timer value is updated by first reading the current timer value, storing it in some storage location, loading a new timer value from another storage location, and finally programming the new timer value into the timer. Unfortunately, these operations can require time to perform, and therefore some time may pass between the time that the timer value is read from the timer and the time at which the new timer value is programmed into the timer, thereby creating a difference between “real time” and the time that's reflected by the timer.
This problem may be exacerbated as subsequent timer update operations are performed, thereby creating a greater gap between real time and the timer value whenever the timer is updated. The difference between real time and the timer value may cause errors in some programs or processes running in a computer system or that otherwise depend on an accurate timer value. For example, such a gap between real time and a timer value may cause a computer's real time clock to shift over time, which can affect the accuracy of programs, such as calendaring programs, that rely on the timer.
The present invention is illustrated by way of example and not limitation in the accompanying figures.
Embodiments of the invention relate to computer systems. More particularly, at least one embodiment of the invention relates to a technique to update a timer value while taking into account the advancement of time.
In one embodiment, a timer value is updated using a one or more operations to read the current timer value and update the timer value while taking into account the amount time required to perform the one or more operations. For example, in one embodiment, time corresponding to the amount of time the timer increments (in the case of an “up-timer”) or decrements (in the case of a “down-timer”) may be added/subtracted to/from the update timer value to compensate for the elapsed timer count during the update process.
In some embodiments, the amount of time elapsed during the update process may be reduced by condensing the operations used to update the timer value into a fewer number of operations, than in some prior art timer update techniques. For example, in one embodiment, one operation is used to read the current timer value, update it, and program the updated timer value into the timer. In other embodiments, one operation may be used to read the timer value and update it, and another operation may be used to program the updated timer value into the timer. In yet other embodiments, one operation may be used to read the timer value and another operation may be used to update the time value and program the updated timer value into the timer. Embodiments of the invention, in general, may update a timer using fewer operations than in the prior art as well as compensate the timer value for the time required to update the timer.
Also illustrated in
In one embodiment, the logic of
Particularly, in the case of a decrementing timer, or down-timer, an underflow condition may result from the subtraction of the lower order bits of the new timer value and the elapsed time count previously mentioned resulting in a value less than “0”. In this case, the arithmetic unit may indicate this condition by asserting a signal on output 113, which may cause the upper bits to be decremented to account for the elapsed time. In other embodiments, the subtraction operation resulting in a negative number may have no affect on the upper bits. Likewise, if the timer logic of
In one embodiment, underflow or overflow may be detected by performing a logical AND operation between a carry-out bit from the arithmetic unit and a logical NOR'ed version of the upper bits in count storage area 101. In other embodiments, other techniques may be used to detect an overflow or an underflow condition, including pre-calculating the subtraction or addition operation using microcode. In other embodiments, the underflow or overflow may be calculated using other logic, such as a full adder or subtractor logic.
In one embodiment, a timer value is updated using fewer operations than in the prior art. For example, in one embodiment the timer value stored in the third timer storage area 110 may be read into another storage area (not shown in
Unlike some prior art techniques, at least one embodiment of the invention updates time values without using separate operations or instructions/uops for reading the current timer value, updating the timer value, and then programming the timer with the updated timer value. Particularly, in one embodiment, two or more of these steps, including all three, may be performed by executing one instruction, such as an XCHGTMR instruction.
At operation 220, the upper bits of the updated timer value is stored in a first storage area, such as a register, while an elapsed time value, reflecting the time from when the timer value was read by the instruction until the updated timer value is stored into the timer, is added (in the case of an up-timer) to the lower order bits of the updated timer value or subtracted (in the case of a down-timer) from the lower order bits of the updated timer value and the result is stored in a second storage area, such as a second register. In one embodiment, if the addition or subtraction results in an overflow or underflow condition, respectively, at operation 225, then this is indicated by a signal to reflect the overflow or underflow condition in the upper bits of the updated timer value stored in the first storage area at operation 227. At operation 230, the final result of the updated timer value (post-underflow/overflow adjustment) may be stored in an old timer value storage area, such as a register, so that it is not overwritten by a subsequent timer value update.
Illustrated within the processor of
The main memory may be implemented in various memory sources, such as dynamic random-access memory (DRAM), a hard disk drive (HDD) 320, or a memory source located remotely from the computer system via network interface 330 containing various storage devices and technologies. The cache memory may be located either within the processor or in close proximity to the processor, such as on the processor's local bus 307.
Furthermore, the cache memory may contain relatively fast memory cells, such as a six-transistor (6T) cell, or other memory cell of approximately equal or faster access speed. The computer system of
The system of
Processors referred to herein, or any other component designed according to an embodiment of the present invention, may be designed in various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally or alternatively, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, most designs, at some stage, reach a level where they may be modeled with data representing the physical placement of various devices. In the case where conventional semiconductor fabrication techniques are used, the data representing the device placement model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce an integrated circuit.
In any representation of the design, the data may be stored in any form of a machine-readable medium. An optical or electrical wave modulated or otherwise generated to transmit such information, a memory, or a magnetic or optical storage medium, such as a disc, may be the machine-readable medium. Any of these mediums may “carry” or “indicate” the design, or other information used in an embodiment of the present invention, such as the instructions in an error recovery routine. When an electrical carrier wave indicating or carrying the information is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, the actions of a communication provider or a network provider may be making copies of an article, e.g., a carrier wave, embodying techniques of the present invention.
Thus, techniques for steering memory accesses, such as loads or stores are disclosed. While certain embodiments have been described, and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art upon studying this disclosure. In an area of technology such as this, where growth is fast and further advancements are not easily foreseen, the disclosed embodiments may be readily modifiable in arrangement and detail as facilitated by enabling technological advancements without departing from the principles of the present disclosure or the scope of the accompanying claims.
Various aspects of one or more embodiments of the invention may be described, discussed, or otherwise referred to in an advertisement for a processor or computer system in which one or more embodiments of the invention may be used. Such advertisements may include, but are not limited to news print, magazines, billboards, or other paper or otherwise tangible media. In particular, various aspects of one or more embodiments of the invention may be advertised on the internet via websites, “pop-up” advertisements, or other web-based media, whether or not a server hosting the program to generate the website or pop-up is located in the United States of America or its territories.
