Patent Application
20230131938
The present disclosure relates to electronic integrated circuits and, in particular, to memory circuits in electronic integrated circuits.
Integrated circuits such as programmable logic devices (PLDs) typically include data storage circuitry such as memory circuits. As applications continue to demand more data at higher data rates, memory circuits in programmable logic devices need to increase data input and output bandwidth capabilities to scale with these applications.
In general, the memory circuits in programmable logic devices can be formed from multiple smaller portions of memory circuits that are connected using programmable interconnects within the programmable logic devices. However, using the programmable interconnects in the general routing fabric for high bandwidth routing to and from the memory circuits strains these portions of the general routing fabric, resulting in high routing congestion and degrading the maximum operating frequency or increasing clock latency of the programmable logic device.
This disclosure discusses integrated circuit devices, including configurable (programmable) logic devices such as field programmable gate arrays (FPGAs). As discussed herein, an integrated circuit (IC) can include hard logic and/or soft logic. As used herein, “hard logic” generally refers to circuits in an integrated circuit device that are not programmable by an end user. The circuits in an integrated circuit device (e.g., in a configurable IC) that are programmable by the end user are referred to as “soft logic.”
Throughout the specification, and in the claims, the term “connected” means a direct electrical connection between the circuits that are connected, without any intermediary devices. The term “coupled” means either a direct electrical connection between circuits or an indirect electrical connection through one or more passive or active intermediary devices. The term “circuit” may mean one or more passive and/or active electrical components that are arranged to cooperate with one another to provide a desired function.
One or more specific examples are described below. In an effort to provide a concise description of these examples, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
In some applications, such as deep learning applications for vision, voice, gesture recognition, memory in an integrated circuit may need to handle high data bandwidth in and out of the memory (e.g., receive large amounts of data from external sources, feed large amounts of data to processing cores on the integrated circuit). To properly buffer the large amounts of data, memory can be formed by connecting smaller memory blocks to each other. However, implementing these connections between smaller memory blocks using the routing fabric in the integrated circuit can cause significant routing congestion. To mitigate these problems, circuit designs would have to include undesirable design limitations that provide suboptimal performance in these data-hungry applications.
To more efficiently implement memory in integrated circuits, smaller memory circuits can include configurable input and output circuits.
As shown in Figure (
Memory and control circuitry 102 also includes an address decoder circuit 44 that receives, from configurable memory input circuits 101 and 103, and decodes address signals for reading data from and writing data into the memory cells at the associated addresses in memory bank circuit 46. If desired, address decoder circuit 44 can receive other signals, such as enable signals or other operational control signals.
Memory and control circuitry 102 also includes an error-correction code (ECC) encoder circuit 45 that receives write data from a multiplexer circuit 16 in the configurable memory input circuit 101. Address decoder circuit 44 and ECC encoder circuit 45 are coupled to memory bank circuit 46 and provide address signals, write data, error correction code data, and other signals to memory bank circuit 46 (e.g., to store the write data in memory cells at the corresponding addresses, to store the error correction code data in memory cells at the corresponding addresses, etc.).
Memory and control circuitry 102 also includes read data steering circuit 47 coupled to address decoder circuit 44, ECC encoder circuit 45, and memory bank circuit 46. Read data steering circuit 47 can receive read data output from memory bank circuit 46 and provide the read data to ECC decoder circuit 48 for performing error correction on the read data using error correction codes. The read data can be read from one or more memory cells at an address or addresses indicated by a read address signal provided from address decoder circuit 44. ECC decoder circuit 48 can provide the error corrected read data to multiplexer circuits 21-22 in the configurable memory output circuit 104.
Configurable memory input circuits 101 and 103 can each have input ports and output ports for memory and control circuitry 102 (e.g., writing data into memory bank circuit 46 or providing addresses to read data from memory bank circuit 46). The input ports in configurable memory input circuit 101 include one or more write data input ports X and B and one or more write address and control input ports Y and A. Input ports X and Y can be coupled directly to adjacent logic circuits (e.g., programmable logic circuits) in the same IC as configurable memory block circuit 100. Input ports A and B can be coupled directly to the configurable memory input circuit 101 of a second instance of the configurable memory block circuit 100 in the same IC (or other data storage circuits if desired).
Ports B and X can be configured to accommodate write data of any suitable width. Write data signals UWD received on port B can be provided through multiplexer circuit 12, optionally via SR flip-flop circuit 32 (e.g., a register), and multiplexer circuit 16 to ECC encoder circuit 45. Write data signals WDA received on port X can be provided through multiplexer circuit 16 to ECC encoder circuit 45. Write data signals UWD or WDA can be provided to a third instance of the configurable memory block circuit 100 in the same IC through multiplexer circuit 15 and an output port D.
Ports A and Y can receive any suitable control and address signals such as a read enable signal, a write enable signal, a power control signal (that is provided to power control circuit 43), and an address signal indicative of a read and/or write address or addresses of any suitable width. One or more control and address signals UWC received on port A can be provided through multiplexer circuit 11, optionally via SR flip-flop circuit 31 (e.g., a register), and multiplexer circuit 13 to address decoder circuit 44. One or more control signals WCL received on port Y can be provided to write address generator circuit 41. Write address generator circuit 41 generates write addresses (e.g., write pointers) that are provided through multiplexer circuit 13 to address decoder circuit 44. Signals UWC or WCL can be provided to the third instance of the configurable memory block circuit 100 through multiplexer circuit 14 and an output port C. Ports C and D are coupled to the configurable memory input circuit 101 in the third instance of the configurable memory block circuit 100.
The configurable memory input circuit 103 and configurable memory output circuit 104 include a read data input port F, read control input ports E and Z, and output ports K, W, H, and G. Ports K, W, and Z can be coupled directly to adjacent logic circuits (e.g., programmable logic circuits) in the same IC as configurable memory block circuit 100. Input ports E and F can be coupled directly to the third instance of the configurable memory block circuit 100 in the same IC. Port F can be configured to accommodate read data of any suitable width. Read data signals DRD received on port F can be provided through multiplexer circuit 21, optionally via SR flip-flop circuit 34 (e.g., a register), and multiplexer circuit 20 to the second instance of the configurable memory block circuit 100 through port H. The decoded read data output by the ECC decoder circuit 48 can be provided through multiplexer circuit 21, optionally via SR flip-flop circuit 34, and multiplexer circuit 20 to the second instance of the configurable memory block circuit 100 through port H. The selection of the multiplexer circuit 21 is controlled by a round robin (RR) arbiter circuit 51. The round robin arbiter circuit 51 is used to manage traffic through multiplexer circuit 21 between the read data signals DRD and the read data accessed from memory bank circuit 46 and output by ECC decoder circuit 48. The decoded read data output by the ECC decoder circuit 48 can also, or alternatively, be provided through multiplexer circuit 22 to the adjacent logic circuits in the IC through port W.
Ports E and Z can receive any suitable control and address signals such as a read enable signal, a write enable signal, a power control signal (that is provided to power control circuit 43), and an address signal indicative of a read and/or write address (or addresses) of any suitable width. The control and address signals DRC received on port E can be provided through multiplexer circuit 19 to address decoder circuit 44 for performing read operations to memory bank circuit 46. One or more read control signals RCT received on port Z are provided to read address generator circuit 49. Read address generator circuit 49 generates read addresses (e.g., read pointers) that are provided through multiplexer circuit 19 to address decoder circuit 44 for performing read operations to memory bank circuit 46. Signals DRC received at port E, or the read addresses output by read address generator circuit 49, can be provided to the second instance of the configurable memory block circuit 100 through multiplexer circuits 17-18 (optionally via SR flip-flop circuit 33) and through port G.
The write address generator circuit 41 generates the write addresses (e.g., write pointers) in response to write control signals WCL at port Y to perform write operations to the memory bank circuit 46. Each write operation can, for example, cause the write addresses to increment to the next memory location sequentially in the memory bank circuit 46. Similarly, the read address generator circuit 49 generates the read addresses (e.g., read pointers) in response to read control signals RCT at port Z to perform read operations to the memory bank circuit 46. Each read operation can, for example, cause the read addresses to increment to the next memory location sequentially in the memory bank circuit 46.
Configurable memory block circuit 100 can be operated in a first-in-first-out (FIFO) mode as a FIFO buffer circuit. In the FIFO mode, a write control logic circuit 42 generates write status control signals WST on an output port J in response to the write addresses generated by the write address generator circuit 41 and in response to the read addresses generated by the read address generator circuit 49 (or indicated by signals DRC) and received via multiplexer 19. Also in the FIFO mode, a read control logic circuit 50 generates read status control signals RST on output port K in response to the read addresses generated by the read address generator circuit 49 and in response to the write addresses generated by the write address generator circuit 41 (or indicated by signals UWC) and received via multiplexer 13. The write status control signals WST and the read status control signals RST are used to keep track of the status of a queue in the memory bank circuit 46 during the FIFO mode.
The write and read status control signals can, for example, indicate when the queue in memory bank circuit 46 is full or empty in the FIFO mode. The write status control signals WST can indicate that the queue in memory bank circuit 46 is full when the separation between the read pointer and the write pointer (i.e., the read and the write addresses) reaches a predefined full value. The read status control signals RST can indicate that the queue in memory bank circuit 46 is empty when the separation between the read pointer and the write pointer (i.e., the read and the write addresses) reaches zero. The separation between the read and write pointers can, for example, be measured by a counter circuit and a comparator circuit in each of the write and read control logic circuits 42 and 50.
Implementing the write and read control logic circuits 42 and 50 and the write and read address generator circuits 41 and 49 in hard logic in configurable memory block circuit 100 eliminates the use of soft logic for the counter circuit, the comparator circuit, and the full/empty signal generation. Implementing these circuits in hard logic also enables several configurable memory block circuits 100 to be coupled together in a chain to build a deep FIFO queue having a large width, without reducing the maximum frequency of operation. A chain of the configurable memory block circuits 100 provides a substantial dynamic and static power savings, compared to a memory circuit that uses a soft logic queue, by using more fine-gain dynamic power-up of only the configurable memory block circuits 100 in the chain that are used. Configurable memory block circuit 100 also resolves issues with internal latencies during a de-assertion of empty during a write operation, or during a de-assertion of full during a read operation.
The interface bridge circuit 201 is an interface circuit coupled between fabric region 202 and a device (e.g., an IC) that is external to the circuitry shown in
In the example of
According to some examples disclosed herein, an integrated circuit includes a buffer circuit, one or more memory circuits, and one or more controller circuits. The controller circuits determine whether to transmit information stored in the memory circuits to the buffer circuit based on credits that indicate an amount of storage space available in the buffer circuit. The controller circuits transmit the information to the buffer circuit if the credits indicate that sufficient storage space is available in the buffer circuit to store the information.
According to an example, the controller circuits 311-318, the memory circuits 321-328, and bus 303 can be implemented by 8 instances of the configurable memory block circuit 100 of
The memory circuits 321-328 can be any types of memory circuits. 8 memory circuits and 8 controller circuits are shown in
The response buffer circuit 301 stores and manages credits that indicate how much memory storage space is available in the response buffer circuit 301 for storing write data or write addresses received from the memory circuits 321-328 through bus 303. The response buffer circuit 301 increases the number of the credits available to store write data and write addresses received from memory circuits 321-328 in response to additional storage space that has been allocated to memory circuits 321-328 becoming available in the response buffer circuit 301. The response buffer circuit 301 decreases the number of the credits available in response to storing write data and write addresses received from memory circuits 321-328 in the storage space that has been allocated to memory circuits 321-328. The FIFO mode described above with respect to
If there is a lag in the allocation and availability of the credits, the response buffer circuit 301 does not under-estimate the credits available so that any write data or write addresses received through bus 303 are stored in the response buffer circuit 301. The credits can be provided from the response buffer circuit 301 to the controller circuits 311-318 through the bus 303 or through other conductors. In operation 402, one of the controller circuits 311-318 determines whether to transmit write data or one or more write addresses stored in the respective memory circuit 321-328 to the response buffer circuit 301 based on the available credits received from the response buffer circuit 301 and based on the presence of valid write data or a valid write address being stored in the respective memory circuit.
The controller circuit initially determines if valid write data or a valid write address is stored in the respective memory circuit coupled to that controller circuit. If the controller circuit determines that valid write data or a valid write address is stored in the respective memory circuit, then the controller circuit determines if the available credits indicate that there is enough storage space in the response buffer circuit 301 to store the write data or write address in operation 402. If the controller circuit determines that the available credits indicate that there is enough storage space in the response buffer circuit 301 to store the write data or write address, the controller circuit proceeds to operation 403. Otherwise, the controller circuit can wait for the response buffer circuit 301 to allocate additional storage space for storing write data or write addresses and to indicate the additional storage space by increasing the number of credits available. Operation 402 can be performed by any of the controller circuits 311-318. For example, if controller circuit 311 determines that the memory circuit 321 stores write data or a write address, then controller circuit 311 determines if the available credits indicate that there is enough storage space in the response buffer circuit 301 to store the write data or write address that is currently stored in memory circuit 321 in operation 402.
In operation 403, the controller circuit that performed operation 402 (e.g., one of controller circuits 311-318) generates an interrupt request on the bus 303 to interrupt any signal transmission that is occurring on bus 303. The bus 303 can cause data or address traffic to back-pressure in response to the interrupt request generated by the controller circuit in operation 403. Signal transmission on bus 303 can, for example, be halted, and the data/addresses on bus 303 can be buffered in their current storage locations. Alternatively, the bus 303 can back-pressure the write data or write address in the requesting controller circuit 311-318 or in the respective memory circuit 321-328 in response to the interrupt request generated in operation 403, until the current signal transmission on bus 303 is completed. According to this example, the write data or a write address remains in the controller circuit or in the memory circuit, until signal transmission on bus 303 is completed, and the interrupt request can be serviced. Any of the controller circuits 311-318 can, for example, use the credits to indicate a FIFO queue status in the respective memory circuit 321-328 as full or empty, which can be used to back-pressure the incoming write data or write address.
In operation 404, the controller circuit that performed operations 402-403 transmits the write data or write address stored in the respective memory circuit to the response buffer circuit 301 through the bus 303. In some implementations, each memory circuit 321-328 is assigned to a unique identifier (ID), and only the memory circuits 321-328 having the unique identifiers (IDs) matching IDs associated with the available credits can provide write data or write addresses to the response buffer circuit 301 through bus 303 in operation 404. In operation 405, the response buffer circuit 301 stores the write data or write address received from the controller circuit through the bus 303. In operation 406, the response buffer circuit 301 can optionally transmit the write data or write address through bus 302 to another sub-system in the same IC or externally (e.g., to another memory circuit for performing a write operation).
In addition, programmable logic IC 500 can have input/output elements (IOEs) 502 for driving signals off of programmable logic IC 500 and for receiving signals from other devices. Input/output elements 502 can include parallel input/output circuitry, serial data transceiver circuitry, differential receiver and transmitter circuitry, or other circuitry used to connect one integrated circuit to another integrated circuit. As shown, input/output elements 502 can be located around the periphery of the chip. If desired, the programmable logic IC 500 can have input/output elements 502 arranged in different ways. For example, input/output elements 502 can form one or more columns, rows, or islands of input/output elements that may be located anywhere on the programmable logic IC 500.
The programmable logic IC 500 can also include programmable interconnect circuitry in the form of vertical routing channels 540 (i.e., interconnects formed along a vertical axis of programmable logic IC 500) and horizontal routing channels 550 (i.e., interconnects formed along a horizontal axis of programmable logic IC 500), each routing channel including at least one conductor to route at least one signal.
Note that other routing topologies, besides the topology of the interconnect circuitry depicted in
Furthermore, it should be understood that embodiments disclosed herein with respect to
Programmable logic IC 500 can contain programmable memory elements. Memory elements can be loaded with configuration data using input/output elements (IOEs) 502. Once loaded, the memory elements each provide a corresponding static control signal that controls the operation of an associated configurable functional block (e.g., LABs 510, DSP blocks 520, RAM blocks 530, or input/output elements 502).
In a typical scenario, the outputs of the loaded memory elements are applied to the gates of metal-oxide-semiconductor field-effect transistors (MOSFETs) in a functional block to turn certain transistors on or off and thereby configure the logic in the functional block including the routing paths. Programmable logic circuit elements that can be controlled in this way include multiplexers (e.g., multiplexers used for forming routing paths in interconnect circuits), look-up tables, logic arrays, AND, OR, XOR, NAND, and NOR logic gates, pass gates, etc.
The programmable memory elements can be organized in a configuration memory array having rows and columns. A data register that spans across all columns and an address register that spans across all rows can receive configuration data. The configuration data can be shifted onto the data register. When the appropriate address register is asserted, the data register writes the configuration data to the configuration memory bits of the row that was designated by the address register.
In certain embodiments, programmable logic IC 500 can include configuration memory that is organized in sectors, whereby a sector can include the configuration RAM bits that specify the functions and/or interconnections of the subcomponents and wires in or crossing that sector. Each sector can include separate data and address registers.
The programmable logic IC of
The integrated circuits disclosed in one or more embodiments herein can be part of a data processing system that includes one or more of the following components: a processor; memory; input/output circuitry; and peripheral devices. The data processing system can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application. The integrated circuits can be used to perform a variety of different logic functions.
In general, software and data for performing any of the functions disclosed herein can be stored in non-transitory computer readable storage media. Non-transitory computer readable storage media is tangible computer readable storage media that stores data and software for access at a later time, as opposed to media that only transmits propagating electrical signals (e.g., wires). The software code may sometimes be referred to as software, data, program instructions, instructions, or code. The non-transitory computer readable storage media can, for example, include computer memory chips, non-volatile memory such as non-volatile random-access memory (NVRAM), one or more hard drives (e.g., magnetic drives or solid state drives), one or more removable flash drives or other removable media, compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs (BDs), other optical media, and floppy diskettes, tapes, or any other suitable memory or storage device(s).
Additional examples are now described. Example 1 is an integrated circuit comprising: a buffer circuit; a memory circuit; and a controller circuit to determine whether the memory circuit stores information, the controller circuit to determine whether to transmit the information stored in the memory circuit to the buffer circuit based on credits that indicate an amount of storage space available in the buffer circuit, and the controller circuit to transmit the information to the buffer circuit if the credits indicate that sufficient storage space is available in the buffer circuit to store the information.
In Example 2, the integrated circuit of Example 1 can optionally include, the buffer circuit to change a number of the credits in response to changes in the amount of storage space available in the buffer circuit.
In Example 3, the integrated circuit of any one of Examples 1-2 can optionally include, wherein the memory circuit is one of a set of memory circuits, and wherein the controller circuit is one of a set of controller circuits that determine whether to transmit information stored in the memory circuits to the buffer circuit based on the credits that indicate the amount of storage space available in the buffer circuit and allocated for storing the information stored in the memory circuits.
In Example 4, the integrated circuit of any one of Examples 1-3 can optionally include, the controller circuit to generate an interrupt request on a bus to interrupt signal transmission on the bus prior to transmitting the information to the buffer circuit on the bus.
In Example 5, the integrated circuit of any one of Examples 1-4 can optionally include, the buffer circuit to store the information received from the controller circuit.
In Example 6, the integrated circuit of any one of Examples 1-5 can optionally include, the memory circuit to store the information in response to a write request from a requesting circuit in the integrated circuit.
In Example 7, the integrated circuit of any one of Examples 1-6 can optionally include, the buffer circuit to store and manage the credits that indicate the amount of available storage space in the buffer circuit for storing the information received from the controller circuit.
In Example 8, the integrated circuit of any one of Examples 1-7 can optionally include, wherein the information stored in the memory circuit is one of a write address or write data for a write operation.
Example 9 is a method comprising: determining whether a memory circuit stores information; determining whether to transmit the information stored in the memory circuit to a buffer circuit using a controller circuit based on credits that indicate an amount of available storage in the buffer circuit; transmitting the information from the controller circuit to the buffer circuit through a bus if the credits indicate that enough storage is available in the buffer circuit to store the information; and storing the information in the buffer circuit.
In Example 10, the method of Example 9 further comprises: storing the information in the memory circuit in response to a write request from a requesting circuit.
In Example 11, the method of any one of Examples 9-10 further comprises: changing a number of the credits in response to changes in the amount of storage available in the buffer circuit for storing the information.
In Example 12, the method of any one of Examples 9-11 further comprises: generating an interrupt request on the bus using the controller circuit to interrupt signal transmission on the bus prior to transmitting the information from the controller circuit to the buffer circuit.
In Example 13, the method of any one of Examples 9-12 further comprises: storing the credits in the buffer circuit; and providing the credits to the controller circuit.
In Example 14, the method of any one of Examples 9-13 further comprises: determining whether to transmit information stored in memory circuits to the buffer circuit based on the credits that indicate the amount of available storage in the buffer circuit allocated for storing the information stored in the memory circuits using controller circuits that comprise the controller circuit, wherein the memory circuits comprise the memory circuit.
In Example 15, the method of Example 14 further comprises: transmitting the information stored in the memory circuits from the controller circuits to the buffer circuit through the bus if the credits indicate that enough storage is available in the buffer circuit and allocated to the memory circuits.
Example 16 is an integrated circuit comprising a first configurable memory block circuit, wherein the first configurable memory block circuit comprises: a write address generator circuit to generate a write pointer for a write operation to a first memory circuit; a read address generator circuit to generate a read pointer for a read operation to the first memory circuit; a write control logic circuit to generate a write status control signal that indicates that the first memory circuit is full when a separation between the read pointer and the write pointer reaches a predefined full value; and a read control logic circuit to generate a read status control signal that indicates that the first memory circuit is empty when the separation between the read pointer and the write pointer reaches zero.
In Example 17, the integrated circuit of Example 16 can optionally include, wherein the first configurable memory block circuit further comprises: an address decoder circuit to provide a read address to the first memory circuit for performing the read operation in response to the read pointer, the address decoder circuit to provide a write address to the first memory circuit for performing the write operation in response to the write pointer.
In Example 18, the integrated circuit of any one of Examples 16-17 further comprises: a second configurable memory block circuit comprising a second memory circuit, wherein the first configurable memory block circuit further comprises a multiplexer circuit and a round robin arbiter circuit to manage traffic through the multiplexer circuit between first read data accessed from the first memory circuit during the read operation and second read data accessed from the second memory circuit.
In Example 19, the integrated circuit of Example 18 further comprises: a third configurable memory block circuit coupled to the first configurable memory block circuit, the round robin arbiter circuit to manage traffic through the multiplexer circuit to the third configurable memory block circuit.
In Example 20, the integrated circuit of any one of Examples 16-17 can optionally include, wherein the first configurable memory block circuit further comprises a multiplexer circuit configurable to provide a write control signal from a second configurable memory block circuit or the write pointer to a third configurable memory block circuit.
The foregoing description of the examples has been presented for the purpose of illustration. The foregoing description is not intended to be exhaustive or to be limiting to the examples disclosed herein. In some instances, features of the examples can be employed without a corresponding use of other features as set forth. Many modifications, substitutions, and variations are possible in light of the above teachings.
