Patent Application
20150243234
Traditionally, liquid crystal displays (LCDs) had a fixed refresh rate, wherein the contents of the screen are refreshed at fixed time intervals, e.g., at 60 Hz. While fixed refresh rates perform adequately for certain applications, e.g., T.V. shows, other applications, e.g., gaming suffers. Depending on the complexity of the calculations, the graphics processing unit (GPU) used to render gaming graphics for an LCD display typically renders frames at varying rates. The difference in the rendering rate of the GPU and the fixed refresh rate of the LCD can result in conspicuous visual artifacts that distort a user's experience of the game.
Variable refresh rate monitors alleviate this problem by requiring the LCD screen to sync with the GPU instead of refreshing at a fixed rate. The GPU sends an image to the LCD as soon as it is rendered and the LCD monitor repaints the image. Subsequently, the LCD waits for the next image to be transmitted from the GPU. This reduces visual artifacts like stutter and tearing and results in smoother on-screen motion. However, because of the variable refresh rate, each RGB component of a pixel can start to accumulate charge if positive and negative polarity frame durations are not equal because of an unbalanced polarity pattern (also called a beat pattern).
The intensity of each one of the RGB components of a pixel of a liquid crystal display (“LCD”) is determined by the voltage difference that is applied to the pixel cell. In the neutral state, no voltage is applied. In the active state, the voltage can either have positive or negative polarity. It should be noted that both positive and negative polarities result in the same intensity of color on the LCD screen. As the voltage is applied to a pixel cell, the RGB component of a pixel (hereinafter, each RGB component of a pixel will be referred to as a “pixel”) may slowly accumulate a charge. When this charge is present, the intensity of the pixel will be different than when the charge is not present, even in cases where the same voltage is applied.
Over time, the charge accumulation inside a component dot of a pixel will result in visual artifacts. For example, the intensity of the pixel will be different when a positive voltage is applied than when a negative voltage of the same magnitude is applied. If the polarity changes for each frame displayed, the pixel will alternately have different values for the same applied voltage magnitude, which can be observed as significant flicker.
To avoid this charge accumulation and noticeable flicker, the driving electronics of the LCD panel need to ensure that the average charge in the pixels stays close to zero, which means that the average voltage applied over time should approximately be zero also. It should be noted that because the charge inside a pixel leaks away over time, similar to a leaky capacitor, the average voltage applied does not have to be exactly zero.
In a display with a fixed refresh rate, ensuring that the average voltage applied is zero can be accomplished by alternately applying a positive and negative voltage across the pixels. The polarity of the voltage on each pixel is typically changed for each frame for a regular 2D display, e.g., in the following pattern: (+−+−+−+−). For some stereo 3D displays, for example, the polarity of the voltage on each pixel may change in the following fashion: (++−−++−−++−−++).
In a variable rate display, however, ensuring that the average voltage charge applied stays close to zero is more challenging. Conventional variable rate LCD displays do not have an efficient or any mechanism for ensuring that the average voltage applied over time stays close to zero and, therefore, undesirable parasitic charge can build up for the pixels of the LCD screen which causes visible artifacts.
Accordingly a need exists for a method and apparatus to prevent charge accumulation within the component dots of pixels in a variable refresh rate display. Embodiments of the present invention provide a method for avoiding charge accumulation and resultant visual artifacts by intelligently inserting repeat frames between input frames provided by a graphics processing unit (GPU) to a LCD monitor.
Embodiments of the present invention provide a method for preventing charge accumulation and resultant visual artifacts by dynamically analyzing a sequence of frames to detect any DC imbalance building up within the pixels of the LCD panel and performing a sequence of remediation counter-measures in response to cure for the imbalance. The novel procedure of applying DC imbalance remediation techniques advantageously breaks the unbalanced polarity pattern or beat pattern that may result in the charge accumulation running away.
In one embodiment, a method for driving a display panel having a variable refresh rate is disclosed. The method comprises receiving a current input frame from an image source. It also comprises determining a first number of re-scanned frames to insert between the current input frame and a subsequent input frame, wherein the re-scanned frames repeat the current input frame, and wherein the determining depends on a minimum refresh interval (MRI) of the display panel. Next, it comprises calculating respective intervals at which to insert the first number of re-scanned frames between the current input frame and the subsequent input frame. Further, it comprises scanning the current input frame for display on the display panel. Finally, it comprises inserting the first number of re-scanned frames at the respective intervals between the current input frame and the subsequent input frame from the image source, wherein the inserting is operable to reduce charge accumulation in the display panel.
In a different embodiment, a non-transitory computer-readable storage medium having stored thereon, computer executable instructions that, if executed by a computer system cause the computer system to perform a method for driving a display panel having a variable refresh rate is disclosed. The method comprises receiving a current input frame from an image source. It also comprises determining a first number of re-scanned frames to insert between the current input frame and a subsequent input frame, wherein the re-scanned frames repeat the current input frame, and wherein the determining depends on a minimum refresh interval (MRI) of the display panel. Next, it comprises calculating respective intervals at which to insert the first number of re-scanned frames between the current input frame and the subsequent input frame. Further, it comprises scanning the current input frame for display on the display panel. Finally, it comprises inserting the first number of re-scanned frames at the respective intervals between the current input frame and the subsequent input frame from the image source, wherein the inserting is operable to reduce charge accumulation in the display panel.
In a different embodiment, a system comprising a variable refresh rate display, a memory for storing images from an image source, and a processor coupled to the memory is disclosed. The processor is operable to implement a method for driving a display panel having a variable refresh rate. The method implemented by the processor comprises receiving a current input frame from an image source. It also comprises determining a first number of re-scanned frames to insert between the current input frame and a subsequent input frame, wherein the re-scanned frames repeat the current input frame, and wherein the determining depends on a minimum refresh interval (MRI) of the display panel. Next, it comprises calculating respective intervals at which to insert the first number of re-scanned frames between the current input frame and the subsequent input frame. Further, it comprises scanning the current input frame for display on the display panel. Finally, it comprises inserting the first number of re-scanned frames at the respective intervals between the current input frame and the subsequent input frame from the image source, wherein the inserting is operable to reduce charge accumulation in the display panel.
The following detailed description together with the accompanying drawings will provide a better understanding of the nature and advantages of the present invention.
Embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements.
Reference will now be made in detail to the various embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While described in conjunction with these embodiments, it will be understood that they are not intended to limit the disclosure to these embodiments. On the contrary, the disclosure is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure.
Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those utilizing physical manipulations of physical quantities. Usually, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as transactions, bits, values, elements, symbols, characters, samples, pixels, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present disclosure, discussions utilizing terms such as “inserting,” “receiving,” “calculating,” “determining,” or the like, refer to actions and processes (e.g., flowchart 700 of
Embodiments described herein may be discussed in the general context of computer-executable instructions residing on some form of computer-readable storage medium, such as program modules, executed by one or more computers or other devices. By way of example, and not limitation, computer-readable storage media may comprise non-transitory computer-readable storage media and communication media; non-transitory computer-readable media include all computer-readable media except for a transitory, propagating signal. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types. The functionality of the program modules may be combined or distributed as desired in various embodiments.
Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable ROM (EEPROM), flash memory or other memory technology, compact disk ROM (CD-ROM), digital versatile disks (DVDs) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can accessed to retrieve that information.
Communication media can embody computer-executable instructions, data structures, and program modules, and includes any information delivery media. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), infrared, and other wireless media. Combinations of any of the above can also be included within the scope of computer-readable media.
Processor 114 generally represents any type or form of processing unit capable of processing data or interpreting and executing instructions. For example, processing unit 114 may represent a central processing unit (CPU), a graphics processing unit (GPU), or both. In one embodiment, the DC imbalance detection and DC imbalance remediation procedure of the present invention is programmed into either the CPU (or GPU) 114. In certain embodiments, processor 114 may receive instructions from a software application or module. These instructions may cause processor 114 to perform the functions of one or more of the example embodiments described and/or illustrated herein.
System memory 116 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and/or other computer-readable instructions. Examples of system memory 116 include, without limitation, RAM, ROM, flash memory, or any other suitable memory device. Although not required, in certain embodiments computing system 110 may include both a volatile memory unit (such as, for example, system memory 116) and a non-volatile storage device (such as, for example, primary storage device 132).
Computing system 110 may also include one or more components or elements in addition to processor 114 and system memory 116. For example, in the embodiment of
Memory controller 118 generally represents any type or form of device capable of handling memory or data or controlling communication between one or more components of computing system 110. For example, memory controller 118 may control communication between processor 114, system memory 116, and I/O controller 120 via communication infrastructure 112.
I/O controller 120 generally represents any type or form of module capable of coordinating and/or controlling the input and output functions of a computing device. For example, I/O controller 120 may control or facilitate transfer of data between one or more elements of computing system 110, such as processor 114, system memory 116, communication interface 122, display adapter 126, input interface 130, and storage interface 134.
Communication interface 122 broadly represents any type or form of communication device or adapter capable of facilitating communication between example computing system 110 and one or more additional devices. For example, communication interface 122 may facilitate communication between computing system 110 and a private or public network including additional computing systems. Examples of communication interface 122 include, without limitation, a wired network interface (such as a network interface card), a wireless network interface (such as a wireless network interface card), a modem, and any other suitable interface. In one embodiment, communication interface 122 provides a direct connection to a remote server via a direct link to a network, such as the Internet. Communication interface 122 may also indirectly provide such a connection through any other suitable connection.
Communication interface 122 may also represent a host adapter configured to facilitate communication between computing system 110 and one or more additional network or storage devices via an external bus or communications channel. Examples of host adapters include, without limitation, Small Computer System Interface (SCSI) host adapters, Universal Serial Bus (USB) host adapters, IEEE (Institute of Electrical and Electronics Engineers) 1394 host adapters, Serial Advanced Technology Attachment (SATA) and External SATA (eSATA) host adapters, Advanced Technology Attachment (ATA) and Parallel ATA (PATA) host adapters, Fibre Channel interface adapters, Ethernet adapters, or the like. Communication interface 122 may also allow computing system 110 to engage in distributed or remote computing. For example, communication interface 122 may receive instructions from a remote device or send instructions to a remote device for execution.
As illustrated in
As illustrated in
As illustrated in
In one example, databases 140 may be stored in primary storage device 132. Databases 140 may represent portions of a single database or computing device or it may represent multiple databases or computing devices. For example, databases 140 may represent (be stored on) a portion of computing system 110 and/or portions of example network architecture 200 in
Continuing with reference to
Many other devices or subsystems may be connected to computing system 110. Conversely, all of the components and devices illustrated in
The computer-readable medium containing the computer program may be loaded into computing system 110. All or a portion of the computer program stored on the computer-readable medium may then be stored in system memory 116 and/or various portions of storage devices 132 and 133. When executed by processor 114, a computer program loaded into computing system 110 may cause processor 114 to perform and/or be a means for performing the functions of the example embodiments described and/or illustrated herein. Additionally or alternatively, the example embodiments described and/or illustrated herein may be implemented in firmware and/or hardware.
For example, a computer program for tracking and remedying DC imbalance may be stored on the computer-readable medium and then stored in system memory 116 and/or various portions of storage devices 132 and 133. When executed by the processor 114, the computer program may cause the processor 114 to perform and/or be a means for performing the functions required for carrying out DC imbalance avoidance, detection and remediation discussed above.
Techniques for Avoiding and Remedying Dc Bias Buildup on a Flat Panel Variable Refresh Rate Display
Embodiments of the present invention provide a method and apparatus to prevent charge accumulation within the component dots of pixels in a variable refresh rate display. Embodiments of the present invention provide a method for avoiding charge accumulation and resultant visual artifacts by intelligently inserting repeat frames between input frames provided by a graphics processing unit (GPU) to a LCD monitor.
Embodiments of the present invention provide a method for preventing charge accumulation and resultant visual artifacts by dynamically analyzing a sequence of frames to detect any DC imbalance building up within the pixels of the LCD panel and performing a sequence of remediation procedures in response to cure for the imbalance. The novel procedure of applying DC imbalance remediation techniques advantageously breaks the unbalanced polarity pattern or beat pattern that may result in the charge running away.
In a conventional variable refresh rate display, successive frames will have roughly the same duration and alternating the polarity between successive frames will typically work to prevent charge accumulation. However, there are some scenarios where this does not hold true. For example, image sources such as graphics processing units (GPUs) can have a tendency to get into an unbalanced polarity pattern or beat pattern where the arrival interval of incoming frames alternates between longer and shorter. For example, the beat pattern may be represented as the following: +/long, −/short, +/long, −/short, etc. This can result in a DC imbalance over time.
Another example where charge build-up can result is where an LCD panel has a minimum refresh rate (or maximum frame duration) below which the panel will start to show delay-related flicker. In the event that the GPU cannot keep up with the refresh rate, to combat this decay flicker, the driving electronics of the LCD panel or the GPU itself will repeat the prior frame to ensure that the refresh rate will not fall below this minimum threshold.
Embodiments of the present invention provide a method and apparatus to combat this DC imbalance, either by avoiding it completely or by remedying it when it occurs. In one embodiment, the present invention first tries to avoid DC imbalance altogether by intelligently re-scanning frames at equi-distant intervals in between input frames from the GPU. Stated differently, incoming frames from the GPU are repeated and inserted at equi-distant intervals in between the incoming frames. It should be noted that timing controllers (TCONS) within the LCD panel alternate polarity with every scan-out of a frame, whether a new frame or a repeated frame. The polarity of the frames typically cannot be directly controlled. Thus, the DC avoidance procedure, in one embodiment, controls when to repeat (or re-scan) some available frame. Accordingly, as will be explained in detail below, the avoidance mechanism works by strategically inserting re-scanned frames between input frames from the GPU.
In another embodiment, the present invention performs DC imbalance monitoring and detection. If a DC imbalance exceeds a predetermined threshold, a sequence of remediation procedures, which will be explained in detail below, is applied to restore the DC balance. For example, the sequence, in one embodiment, first tries to reduce the number of inserted re-scanned frames to try and invert the polarity pattern. It may also try to drop a frame entirely. In one embodiment, the sequence of remediation procedures may also try to add another re-scanned frame in order to invert the polarity pattern.
As mentioned above, in one embodiment, the DC imbalance detection and DC imbalance remediation procedures of the present invention can be programmed into the GPU, which is in constant communication with the LCD. In a different embodiment, the detection and remediation procedures can be programmed directly into the firmware of the LCD display. It should be noted that in a typical embodiment the DC imbalance detection and remediation are performed collectively for all pixels of the LCD screen. However, in one embodiment, the detection and correction can be performed on a per-pixel basis, however, this embodiment would typically require additional computation power and is less efficient than performing detection and remediation for all pixels collectively.
DC Model
Input Vi 331 represents the driving voltage supplied to a pixel in the panel. Resistor 330 and capacitor 333 together model how fast the pixel will charge and build up voltage, wherein the values of resistor Rcharge 330 and capacitor 333 dictate the value of the RC time constant of the charge/discharge circuit. The charge/discharge time constant, A, can be calculated as follows:
A=C*Rcharge (Eq. 1)
Meanwhile, Rleak 332 and capacitor 333 together model how fast the pixel will leak voltage, wherein the values of Rleak 332 and capacitor 333 dictate the value of the RC time constant of the leakage circuit. The leak time constant, B, can be calculated as follows:
B=C*Rleak (Eq. 2)
The input voltage, Vi 331, is assumed to alternate every frame between −K and +K volts. In one embodiment, in order to track the DC bias, the built-up charge voltage, Vc 335, may be expressed as a fraction of the input amplitude, in which case, the value K itself is not relevant. Accordingly, K can simply be set to the value of 1.
Over a short time period “dt”, which is much smaller than the time constants, A and B, the value of Vc 335 can be approximated using the following linear equation:
Vc(t+dt)=Vc(t)*(1−dt/B)+(Vi−Vc(t))*dt/A (Eq. 3)
In one embodiment, to evaluate how Vc 335 changes over longer time intervals, the long interval can be partitioned into multiple smaller consecutive intervals, and the above formula, Equation 3, can be repeatedly applied to each of those.
The goal of DC balancing is to prevent |Vc| from exceeding some threshold. If, however, |Vc| does exceed the threshold value, the goal of DC balancing is to detect it and to average Vc around zero.
In a typical embodiment, Equation 3 is used to model the pixels of the LCD panel collectively. A separate calculation is typically not performed for each pixel.
I. A. DC Imbalance Avoidance
In order to avoid delay flicker (at the scan rate), a minimum refresh rate must be maintained as discussed in relation with
In one embodiment, the present invention attempts to avoid DC imbalance altogether by intelligently re-scanning frames at equi-distant intervals in between input frames from the GPU. For example, the DC imbalance of
In one embodiment, the avoidance procedure can compute the location to add the re-scanned frame by predicting the duration of the current frame on the basis of the duration of the prior frame. In other words, the DC imbalance procedure treats the duration of the input frames as highly correlated and, accordingly, uses the length of a prior frame as a prediction for the duration of the current frame. Because the frame prior to Frame 1430 in
By way of example, if only a single frame is repeated as in
A typical example of this embodiment would be a video source that plays a movie at a constant 24 frames per second (fps), below the minimum refresh rate of 30 fps of a panel. By inserting the repeated frames evenly, the refresh rate can be up converted to 48 fps or 72 fps, while keeping the DC balance constant.
It should be noted that the efficacy of the avoidance procedure may be influenced by the correlation of the image content; for example, the procedure may be more effective when image content is highly correlated in terms of temporal variation in pixels.
When discussing the DC imbalance avoidance technique, it is also important to distinguish input frames (provided by the GPU as input to the LCD monitor) from output frames (painted or “scanned out” by the logic circuitry inside the monitor onto the actual LCD panel). As such, input frame parameters, e.g., start time, duration etc. can be distinguished from output frame parameters.
In one embodiment, it is possible for the avoidance procedure to scan out the same input frame to the LCD panel multiple times, e.g., for MRI compliance. It would also be possible, in one embodiment, for the procedure to drop an input frame or never scan it out. The first time that any given input frame is scanned out is called the “first scan-out” of that input frame. Accordingly, if no frames are dropped, then each input frame has one associated first scan-out at least. The first scan-out may begin immediately upon start of the input frame's arrival or with any delay thereafter. In other words the first scan-out may begin before the input frame has fully arrived or it may start after some delay subsequent to arrival. The first scan-out, however, cannot complete until the input frame has fully arrived.
If the scan-outs of the frames are all of near identical duration as in the example of
When a re-scan is inserted, it is possible that the GPU may begin to send a new frame to the monitor while the re-scan is in progress. This is referred to as a temporal collision. Typically, a variable refresh rate display of the present invention that is synced to the image source, e.g., a GPU, will need to scan-out (or “paint”) the new input frame right away. However, in the event of a temporal collision, because a scan-out has already started, it must be completed before the incoming frame is presented on the LCD screen. As a result, the first scan-out of the new input frame, in one embodiment, is delayed until the current re-scan of the prior input frame is completed. The amount of delay incurred as a result of this is referred to as the “push-out” of the input frame.
In one embodiment, the DC imbalance avoidance procedure attempts to insert an even number of re-scans in between input frames. As will be illustrated using the examples from
I. B. Implementation of the DC Imbalance Avoidance Procedure
At step 702, a new input frame is received from the GPU, for example, and the LCD circuitry starts processing it. At step 704, the DC imbalance avoidance procedure determines the number of re-scans that need to be inserted for this new input frame.
The minimum number of re-scans that can be inserted for the new frame depends on the MRI. The maximum number of re-scans that can be inserted is determined by the number of times the frame can be re-scanned after the first scan-out before the next frame is predicted to arrive. In one embodiment, these computations are performed based on the duration of the prior frame and the current frame's push-out. In one embodiment, the procedure chooses the lowest possible value. However, if the value chosen is odd and there is room in the frame to increase it to an even value without pushing out the next frame, then the procedure will increase the value by one. In other words, the procedure, in one embodiment, can be programmed to choose the lowest even value.
In one embodiment, the procedure can be programmed to take the amount of push-out for the current input frame into account in determining the number of re-scans to be inserted into the frame. As was discussed earlier, a push-out can result from insertion of re-scans in a prior frame that produces a temporal collision.
At step 706, the procedure calculates the interval at which re-scans will be inserted using the number of re-scans determined at step 704. If the procedure determines that an N number of re-scans should be inserted at step 704, then the calculated interval will be used at most N times. If, however, the current input frame's duration is longer than expected (or longer than the prior frame), then any further re-scans following the initial N re-scans will be done at an interval size of MRI.
At step 710, the procedure checks the DC balance threshold. In one embodiment, the DC balance is tracked using the RC model described above. In one embodiment, if |Vc| is below a threshold level, then the first scan-out can proceed without interruption at step 712. Further, the procedure waits for the first scan-out to complete at step 712. At step 714, the procedure waits until the first time the input frame is due to be re-scanned or the arrival of the next input frame, whichever occurs sooner. It should be noted that because the computations of the number of re-scans and re-scan intervals are done, in one embodiment, based on an estimated frame size, it is possible for the next input frame to arrive before a scheduled re-scan is performed.
If the time when the first re-scan due to be performed is reached without any new input frame arriving, then a re-scan is initiated at that point and the procedure waits for it to complete. Similarly, if at that point no new input frame has started to arrive, the procedure repeats step 714. In other words, in one embodiment, the procedure waits (for the duration calculated at step 706) until the next re-scan is due to be performed and performs it if no new input frame comes in. Alternatively, if the scheduled number of re-scans has already been performed, then instead of waiting for the duration calculated at step 706, the interval size is modified to MRI. The rationale for modifying the interval size to MRI is that in order to minimize the probability of a temporal collision, the number of re-scans is minimized and, therefore, the re-scan interval is maximized. If the MRI expires prior to the arrival of the subsequent frame, it likely indicates that the avoidance procedure is not working and, thus, there is a possibility of DC imbalance building up. As will be explained later in connection with step 720, in such cases, a counter-measure can be employed.
Finally, when the new frame arrives, the procedure is repeated at step 702 with the new frame.
In one embodiment, if |Vc| reaches a magnitude that exceeds a predetermined threshold, a one-time special action (also called a counter measure) can be taken to attempt to get the DC balance to drift back in the opposite direction (towards zero) at step 720. In one embodiment, however, a counter measure will only be implemented if a predetermined amount of time has elapsed since a prior counter measure. Because the DC balance takes some duration of time to drift back towards zero after a counter measure is implemented, a new counter measure is not typically implemented until the prior counter measure has been tried for a predetermined amount of time. The rationale for waiting is to allow the taken counter measure to take effect and |Vc| to change value so as to lower it below the threshold. Because |Vc| may still be above the threshold on the next input frame, even though it is improving, without this delay, the process may trigger another counter measure that would counteract the result of the prior counter measure and could cause |Vc| to stray in an undesirable direction.
Counter-measures, in one embodiment, are determined based on the values calculated at steps 704 and 706 and also on the history of prior frames. The process for determining and implementing the appropriate counter-measures will be discussed in subsequent sections below. The result of implementing a counter-measure, in one embodiment, is a modified value for the number of re-scans and a new corresponding re-scan interval.
Further, in one embodiment, one of the counter-measures that can be implemented is dropping the current input frame. In accordance with this embodiment, a decision is made at step 722 concerning whether or not to drop the current input frame. If the conditions for dropping the current input frame were met, then the frame is dropped and the avoidance procedure starts anew with a fresh frame at step 702 after the new input frame arrives. However, if after dropping the current frame, the new input arrive does not arrive right away, then the procedure waits at step 740 and provides new re-scans to the panel at the MRI. In one embodiment, the re-scan can simply be a re-scan of the dropped frame. Alternatively, in a different embodiment the re-scan can use the prior frame. From a practical standpoint, a situation where a frame is dropped, but a new frame does not arrive right away will be rare. In one embodiment, for example, the condition for dropping a frame can include the expectation (based on frame duration) that the next frame will arrive before any re-scan is needed for MRI compliance.
At step 724, if the frame is not dropped, then the first scan-out can proceed without interruption. Further, the procedure, in one embodiment, waits for the first scan-out to complete at step 724. At step 726, the procedure waits until the first time the input frame is due to be re-scanned or the arrival of the next input frame, whichever occurs sooner. It should be noted that the values for the number of re-scans to insert and re-scan interval duration used are the updated values calculated at step 720. It should also be noted that because the computations of the number of re-scans and re-scan intervals are done, in one embodiment, based on an estimated frame size, it is possible for the next input frame to arrive before a scheduled re-scan is performed.
If the time when the first re-scan due to be performed is reached without any new input frame arriving, then a re-scan is initiated at that point and the procedure waits for it to complete. Similarly, if after the re-scan completes, no new input frame has started to arrive, the procedure repeats step 726. In other words, in one embodiment, the procedure waits (for the duration calculated at step 720) till the next re-scan is due to be performed and performs it if no new input frame comes in. If, however, the scheduled number of re-scans has already been performed, then instead of waiting for the duration calculated at step 720, the interval size is modified to MRI. As explained earlier, the rationale for modifying the interval size to MRI is that in order to minimize the probability of a temporal collision, the number of re-scans is minimized and, therefore, the re-scan interval is maximized.
As a result of the counter-measure determined at step 720, when the new input frame finally arrives, the avoidance procedure needs to perform one final action related to the counter-measure at step 728 before beginning the processing of a new input frame at step 702.
At step 728, the procedure checks to see if the actual number of re-scans performed at step 726 were even or odd. In one embodiment, the avoidance procedure forces the number of re-scans to be even if the originally calculated number of re-scans at step 720 were even. Similarly, it forces the number of re-scans to be odd if the originally calculated number of re-scans at step 720 was odd. In other words, even if the actual number of re-scans is potentially different from the number predetermined at step 720, the difference (or sum) must be an even number to avoid a polarity inversion from what was intended by the countermeasure decision.
Accordingly, in one embodiment, at step 728, the procedure checks to see if the difference (or sum) of the total number of re-scans inserted at step 726 and the number of re-scans originally calculated at step 720 is an odd number. If it is an odd number, then another re-scan is started immediately. After waiting for the re-scan to complete, the next input frame can be processed at step 702. If the difference (or sum) ends up being an even number, then no re-scans are needed and the processing of the next input frame at step 702 can commence immediately. For example, if step 720 calculates the number of re-scans to be 3, however, at step 728, the procedure determines that only 1 re-scan was performed, no further re-scans need to be added because both numbers are odd. In other words, the difference (or sum) of the calculated number of re-scans (3) and the number of re-scans actually performed (1) is even.
The minimum number of re-scans as mentioned above depends on the MRI. Accordingly, since the MRI is 30 ms the minimum number of re-scans is 1. The first scan-out should be re-scanned, at the latest, by the 30 ms mark. The maximum number of re-scans, as mentioned earlier, is determined by the number of times the frame can be re-scanned after the first scan-out before the next frame is predicted to arrive. The maximum number of re-scans, without potentially delaying the next incoming frame, can be calculated using the amount of push-out of the current frame (start delay due to collision, zero in this case). Accordingly, the maximum number of re-scans is (50−(0+8))/8=5, where the amount of push-out (zero) and the amount of time it takes to perform the first scan-out (8 ms) is subtracted from the frame duration (50 ms) before computing the number of scan-outs that would fit into the 50 ms duration.
In one embodiment, the procedure will give a preference to the lowest even number calculated and, therefore, the procedure chooses to insert the maximum number of re-scans, which is 2, given the predicted duration of the current input frame. In one embodiment, the re-scans, as calculated at step 706, are computed as taking place at the following time interval: 50/(2+1)=16.7 ms. Accordingly, for input frame 0832, the first re-scan 833 will occur at 16.7 ms and the second re-scan 834 will occur at 33.3 ms. Because re-scans take 8 ms as noted above, the second re-scan 834 finishes at 41.3 ms, which indicates that there is no collision with the next input frame 835 if it arrives at the estimate time of 50 ms.
As shown in
However, occasionally DC will build up and |Vc| may exceed the predetermined threshold, for example, if the frame ends up being a different size than the estimated duration. If DC balance does build up, a counter-measure can typically be employed, in one embodiment, for example, at step 720 in
In one embodiment, the DC balance is tracked at regular intervals in order to determine if the DC bias has drifted above a critical threshold and whether a counter-measure should be employed, e.g., at step 710. In one embodiment, the DC balance is updated at a predetermined granularity to track the effectiveness of the decisions made during the application of the procedure illustrated in
II. A. Counter-Measures
As explained in connection with step 710, the avoidance procedure in
When the DC imbalance exceeds the threshold value, it typically indicates that the measures taken at steps 704, 706, 712, and 714 in
In one embodiment, the counter-measure creates a reversal by attempting to produce one less or one extra output frame (as compared with the standard decision taken at steps 704 and 706) within the duration of the current frame and before the first scan-out of the next input frame. It should also be noted that as a result of step 728, the even or odd nature of the number of re-scans determined as part of the counter-measure at step 720 is enforced regardless of input arrival time of the next frame. In other words, even if the current frame's duration is longer or shorter than expected, the action taken at step 728 will enforce that the total number of re-scans is even if the number of re-scans determined as part of the counter-measure at step 720 is even. Similarly, the action taken at step 728 will enforce that the total number of re-scans is odd if the number of re-scans determined as part of the counter-measure at step 720 is odd.
II. B. Implementation of Counter-Measures
At step 904, the number of re-scans is reduced by one from the base decision taken at step 704. For example, at step 720 of
In one embodiment, the process can be programmed to apply this measure infrequently, e.g., at most once per second. The procedure could be programmed with a parameter that keeps track of how often this counter-measure is applied. It will also be noted by one of ordinary skill that reducing the number of re-scans reduces the probability of collisions and, thus, reduces the push-out of the next frame.
In one embodiment, after a decision to take this measure is reached by the procedure, a new re-scan interval duration is also calculated at step 720 before the process continues on to the remaining steps, e.g., 722, 724, 726 and 728.
At step 906, the alternate counter-measure of dropping the input frame entirely can be applied in accordance with the decision made at step 722 of
For example, certain parameters can be programmed within the process to only allow this counter-measure if the original number of re-scans is calculated to be 0 at step 704, the frame duration is expected to be less than a predetermined threshold (corresponding to a high frame rate e.g., exceeding 100 Hz), and the amount of push-out of the input frame exceeds some predetermined fraction of the frame duration. The conditions ensure that the frame can likely be dropped without noticeable visual artifacts on-screen. However, as explained in connection with step 740, in the unlikely event that a frame is dropped, but the frame duration ends up being much longer than expected, then re-scans of either the dropped frame or the frame prior to the current frame can be inserted until the fresh frame arrives at step 702.
Finally at step 908, the process can increase the number of re-scans by one from the base decision taken at step 704. While it possible that the additional re-scan may not fit within the current frame without forcing some amount of push-out for the next frame, this is an acceptable compromise for using this one-time measure for creating a polarity reversal.
In one embodiment, after a decision to take this measure is reached by the procedure, a new re-scan interval duration is also calculated at step 720 before the process continues on to the remaining steps, e.g., 722, 724, 726 and 728.
It should be noted that the sequence of attempting counter-measures illustrated in
As shown in
If, for example, the DC threshold was exceeded at frame 99 because of this imbalance, then a counter-measure would need to be employed. In the example illustrated in
III. Counter-Measure Decision Based on a History Buffer
As discussed earlier, in one embodiment, the procedure of
At step 1104 an input frame is received. It should be noted that the series of steps that this process comprises is performed for each input frame that is received at step 702 in
At the start of each new input frame, the polarity of the input frame is recorded in a polarity history buffer at step 1106. The polarity history buffer comprises a polarity record of a plurality of prior input frames. For example, the polarity history buffer can comprise an array of bits representing the polarity of each first scan-out for the last 8 input frames.
Further, at step 1106, an updated DC balance value is recorded in a DC balance history buffer at the start of each first scan-out.
At step 1108, the polarity array is examined to determine a polarity pattern that may be resulting in a DC imbalance.
For example, the polarity pattern could be examined to determine if consecutive frames (neighboring bits in the polarity array) are often the same. If a high number of bits have the same value as the bit immediately preceding them, it is an indication that polarity reversal is likely not being achieved. This may be the case because the frame pattern may comprise alternating long-short duration frame pairs, e.g., a 40 ms frame followed by a 60 ms frame. In this case, because the duration of each frame in the repeating pair of frames is different from the prior frame, the procedure in
By way of further example, the process can also be programmed to detect other patterns of polarity over a range of first scan-outs, e.g., an irregular polarity pattern such as −++−−++−.
At step 1110, the entries of the DC balance history buffer are used to determine if the DC imbalance is deteriorating. For example, the average of the 2 oldest DC values in the array and the average of the 2 latest DC values in the array could be calculated and compared. From these average values, the process could determine if the DC balance is improving or getting worse. For instance, if both average values were positive or both average values were negative and the absolute value of the average of the 2 latest DC values is greater than the absolute value of the average of the 2 older DC values, it is indicative of the DC imbalance getting worse.
Finally, at step 1112, the process decides a counter-measure if the DC balance is currently exceeding the threshold, e.g., at step 720 in
By way of further example, if it is determined that most first scan-outs do have alternating polarity but the DC imbalance is still getting worse and exceeding the threshold, the process can be programmed to enforce a one-time odd number of re-scans rather than the usual countermeasure.
As discussed above, variations on this process are also possible by detecting other patterns of polarity over a range of first scan-outs and taking specific actions.
If the DC balance history buffer is checked and shows that the DC bias is currently worse at frame N than 8 frames prior, and it is also exceeds the threshold, then a countermeasure that is likely to be successful would be to break this expected inversion by inserting an odd number of re-scans for this frame. If an odd number of re-scans is inserted between frame N and frame N+1, it assures that frame N+1 will have a negative polarity instead of the expected positive one. Further, this decision should take precedence at step 720 over any decision that is just based on the previous frame's duration since it is more likely to be correct, given the larger history that it is based on.
It should be noted that the history buffer is analyzed to see if a recognizable pattern exist. Based on this, a prediction is made of what will happen for the current input frame versus the next input frame, assuming this detected pattern continues. If no pattern can be detected, then no history-based prediction can be made and this method will not be able to produce a counter measure. In such a case, the procedure will likely revert to other techniques of controlling the DC imbalance.
If a pattern is detected, then according to this history analysis result, the next input frame's first scan-out polarity is predicted to either become inverted or not (as compared to that of current input frame), assuming the pattern continues.
In that case, if the DC balance is over the threshold and increasing (in magnitude) then the history based counter measure will enforce the inverse of this prediction, i.e. select an even or odd number of rescans such that the prediction will not come true in order to break the pattern.
While the foregoing disclosure sets forth various embodiments using specific block diagrams, flowcharts, and examples, each block diagram component, flowchart step, operation, and/or component described and/or illustrated herein may be implemented, individually and/or collectively, using a wide range of hardware, software, or firmware (or any combination thereof) configurations. In addition, any disclosure of components contained within other components should be considered as examples because many other architectures can be implemented to achieve the same functionality.
The process parameters and sequence of steps described and/or illustrated herein are given by way of example only. For example, while the steps illustrated and/or described herein may be shown or discussed in a particular order, these steps do not necessarily need to be performed in the order illustrated or discussed. The various example methods described and/or illustrated herein may also omit one or more of the steps described or illustrated herein or include additional steps in addition to those disclosed.
While various embodiments have been described and/or illustrated herein in the context of fully functional computing systems, one or more of these example embodiments may be distributed as a program product in a variety of forms, regardless of the particular type of computer-readable media used to actually carry out the distribution. The embodiments disclosed herein may also be implemented using software modules that perform certain tasks. These software modules may include script, batch, or other executable files that may be stored on a computer-readable storage medium or in a computing system. These software modules may configure a computing system to perform one or more of the example embodiments disclosed herein. One or more of the software modules disclosed herein may be implemented in a cloud computing environment. Cloud computing environments may provide various services and applications via the Internet. These cloud-based services (e.g., software as a service, platform as a service, infrastructure as a service, etc.) may be accessible through a Web browser or other remote interface. Various functions described herein may be provided through a remote desktop environment or any other cloud-based computing environment.
The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as may be suited to the particular use contemplated.
Embodiments according to the invention are thus described. While the present disclosure has been described in particular embodiments, it should be appreciated that the invention should not be construed as limited by such embodiments, but rather construed according to the below claims.
The present application is related to U.S. patent application Ser. No. 14/147,365, filed Jan. 3, 2014, entitled “DC BALANCING TECHNIQUES FOR A VARIABLE REFRESH RATE DISPLAY,” naming Gerrit Slavenburg, Robert Schutten and Tom Verbeure as inventors, and having attorney docket number NVID-P-SC-13-1402-US1. That application is incorporated herein by reference in its entirety and for all purposes.
