This application is related to Foreign Indian Patent Application Serial No. 799/DEL/2010, entitled “TECHNIQUES FOR CONTROLLING FRAME REFRESH”, filed on Mar. 31, 2010 and claims priority there from.
The subject matter disclosed herein relates generally to programming a self refresh display device.
Many mobile computing devices include self refresh display logic. Self refresh displays have access to a local memory that stores an active display frame. When frames from the host computer are not changing, the host computer transfers the last frame buffer to the self refresh display and the host computer's display sub-system is turned-off or put into a low power state. Meanwhile, the display continues to display the saved frame from its local memory. This can help reduce power consumption and increase the battery life of the computing device.
Embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the drawings and in which like reference numerals refer to similar elements.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase “in one embodiment” or “an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in one or more embodiments.
Various embodiments track the lines and pixels in a frame buffer in the host system that are being modified and transmit these modified scan lines or modified pixels to the self refresh display instead of entire contents of the frame buffer. The graphics adapter informs the self refresh display of the modified scan lines or pixel information and then sends the pixel data over the communications channel to the display. Custom codes can be used to identify and transmit modified scan lines and pixels to the self refresh display logic. Transmitting merely modified scan lines or modified pixel data may transfer a smaller amount of data to the display. Consequently, memory accesses in the host system can be reduced and the display pipeline can be turned off faster to save power and battery life.
OS 202 can identify dirty rectangles to UMD 204 by using handles to surface descriptors. A handle is a pointer to a data element that describes properties and uses of the rectangles requested to be drawn. Contents of the flip buffer are available for display in response to OS 202 asking kernel mode driver (KMD) 206 to flip a flip buffer. A surface handle with draw calls from OS 202 indicates whether flipping is to take place. Flipping a buffer means the contents of the flipped buffer are to be shown on screen. In some embodiments, OS 202 asks for a flip on a flip buffer when there are some changes to the contents of the flip buffer. Accordingly, when OS 202 has asked KMD 206 to flip a flip buffer and dirty rectangles are in the flip buffer, the dirty rectangles are considered portions of a displayable screen that have changed. In various embodiments, KMD 206 could perform a pixel-by-pixel comparison between pixels of a current frame and a previous frame to determine which pixels have changed.
UMD 204 tracks all dirty rectangles for each buffer and passes the tracking to KMD 206. For example, UMD 204 can create a list of dirty rectangles for each buffer that is written to. KMD 206 identifies the dirty rectangles that are to be displayed and converts these dirty rectangles to scan line information. A rectangle has x and y coordinates in the screen coordinate space, which identify beginning and end corners of the rectangle. Using the coordinates of the dirty rectangles, KMD 206 identifies the changed pixels within each changed scan line. KMD 206 identifies the changed lines and changed pixels as modified partial scan lines and pixel information to the self refresh display. KMD 206 transmits these modified scan lines and pixels to the display sub-system within the graphics adapter hardware using registers. Accordingly, KMD 206 has the capability of transmitting entire contents of a flip buffer to buffer 254 or merely modified pixels. In some cases, such as when the modified scan lines are spread across the entire screen, KMD will decide to transmit the entire contents of flip buffer instead of modified lines and pixels.
Display engine 210 of graphics adapter 208 can use custom codes to inform the self refresh display (SRD) logic 252 that only modified scan lines and pixels will be transmitted. The codes depend on the protocols supported by interface 220 between graphics adapter 208 and self refresh display logic 252. If interface 220 is inter-integrated circuit (I2C) compliant, then the custom code is compliant with I2C. Interface 220 may include a Main Link and an AUX channel, both described in Video Electronics Standards Association (VESA) DisplayPort Standard, Version 1, Revision 1a (2008) and Version 1.2 (2009). An AUX channel can be used to communicate the codes and to transfer modified scan lines and pixels to buffer 254.
Display engine 210 fetches the modified scan lines or modified pixels from the memory in which the frame is stored. Display engine 210 transmits pixel data to self refresh display 252 for storage in buffer 254 using display timing information of only these modified scan lines and pixels. The display timings (e.g., pixel clock, Hsync, and Vsync) used for transmission of a full frame buffer from display engine 210 to buffer 254 are also used to transmit the modified scan lines/pixel information to the buffer 254. The following provides an example of signals transmitted to buffer 254.
For a first line of pixels:
VSYNC<zero padded pixels><modified pixels><zero padded pixels>HSYNC [on main link]
A line of pixels other than the first line:
HSYNC<zero padded pixels><modified pixels><zero padded pixels>HSYNC [on main link]
Additionally, display engine 210 handles appropriate watermark levels in pipe first-in-first-out (FIFO) registers located in display engine 210 to prevent pipe under-runs. The memory controller of self refresh display 252 updates the memory locations in buffer 254 that have changed based on the incoming data from display engine 210.
After these lines or pixels are transmitted to the display, display engine 210 of graphics adapter 208 can be turned off and the graphics video memory that includes the flip buffer can be put into self refresh so that additional power is saved.
Graphics adapter 208 informs self refresh display 252 about the start of scan line and pixel number and end of scan line and pixel number that are transmitted from graphics adapter 208. Self refresh display 252 receives data of the scan lines or pixel numbers marked by start and end, both inclusive. Transmitted contiguous pixels represent a portion of a line segment. Graphics adapter 208 transmits only modified pixels to SRD 252 as part of the frame data using the display specific encoding. For example, low voltage differential signaling (described in ANSI/TIA/ELA-644-A (2001)), DisplayPort standard 1.1a (2008) or version 1.2 (2009) and revisions and variations thereof can be used to transmit scan lines. Graphics adapter 208 can send a group of consecutive modified pixels to buffer 254 that represent part of a scan line instead of the entire scan line. Buffer 254 is a buffer accessible to display 250. Buffer 254 may be located inside the display or may be accessible to display 250. In some cases, buffer 254 is located within a host system or is accessible by host system.
The memory controller of self refresh display 252 can address a scan line or specific pixel locations shown in
As an example, consider a frame of size of 1600×1200×32 bits-per pixel being sent to the display with a refresh rate of 60 Hz. In current systems, the entire 7.32 megabytes of frame data is sent. According to various embodiments, if only 10 scan lines changed from the last frame, only 62.5 kilobytes of data may be transmitted. This allows the graphics video memory in the host system to enter lower power mode and turning off of display pipeline in the host system faster to save power and increase battery life.
Reducing the amount of data transmitted for display has at least three advantages, although these advantages are not necessary features of any embodiment.
Block 408 includes the KMD determining whether the rectangles of a surface are to be drawn to a screen. In some cases, the surface associated with rectangles is to be drawn to a screen when the rectangles are to be stored in a flip buffer or a flip chain buffer and the flip buffer is requested to be flipped. If the surface is to be displayed to a screen, then block 410 follows block 408. If the surface is not to be displayed to a screen, then block 406 follows block 408.
Block 410 includes the KMD converting the rectangles to be drawn to a screen to scan lines and pixel locations. Block 412 includes the KMD informing the display sub-system to update display of an image by programming registers with modified scan lines/pixels that are to be drawn to a screen. In an embodiment, these registers may be memory mapped when memory mapped input/output is used to read/write into device registers. The display sub-system may receive only the modified line/pixels.
For example, host system 702 may transmit commands to capture an image and power down components to target device 750 using extension packets transmitted using interface 745. Interface 745 may include a Main Link and an AUX channel, both described in Video Electronics Standards Association (VESA) DisplayPort Standard, Version 1, Revision 1a (2008) and Version 1, 2 (2009). In various embodiments, host system 702 (e.g., graphics subsystem 715) may form and transmit communications to target device 750 to write portions of a buffer with modified scan lines and modified pixels.
Target device 750 may be a display device with capabilities to display visual content and broadcast audio content. For example, target device 750 may include control logic such as a timing controller (TCON) that controls writing of pixels as well as a register that directs operation of target device 750.
The graphics and/or video processing techniques described herein may be implemented in various hardware architectures. For example, graphics and/or video functionality may be integrated within a chipset. Alternatively, a discrete graphics and/or video processor may be used. As still another embodiment, the graphics and/or video functions may be implemented by a general purpose processor, including a multi-core processor. In a further embodiment, the functions may be implemented in a consumer electronics device.
Embodiments of the present invention may be implemented as any or a combination of: one or more microchips or integrated circuits interconnected using a motherboard, hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA). The term “logic” may include, by way of example, software or hardware and/or combinations of software and hardware.
Embodiments of the present invention may be provided, for example, as a computer program product which may include one or more machine-readable media having stored thereon machine-executable instructions that, when executed by one or more machines such as a computer, network of computers, or other electronic devices, may result in the one or more machines carrying out operations in accordance with embodiments of the present invention. A machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (Compact Disc-Read Only Memories), magneto-optical disks, ROMs (Read Only Memories), RAMs (Random Access Memories), EPROMs (Erasable Programmable Read Only Memories), EEPROMs (Electrically Erasable Programmable Read Only Memories), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing machine-executable instructions.
The drawings and the forgoing description gave examples of the present invention. Although depicted as a number of disparate functional items, those skilled in the art will appreciate that one or more of such elements may well be combined into single functional elements. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, orders of processes described herein may be changed and are not limited to the manner described herein. Moreover, the actions of any flow diagram need not be implemented in the order shown; nor do all of the acts necessarily need to be performed. Also, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of the present invention, however, is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims.
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