Patent Application
20190341844
This document pertains generally, but not by way of limitation, to voltage regulators, and more particularly, to switched-capacitor voltage regulator power saving techniques.
Buck regulators are regularly used in applications that rely on a limited energy source such as a battery or capacitor, however, other application also make use of buck regulators. Ultra-low power (ULP) systems often include buck regulators because buck regulators are more efficient than, for example, linear regulators. Some ULP systems can be in a standby mode significantly more than in an active mode, hence having an efficient power converter that can support a few micro amperes of load in standby mode can increase the battery lifetime greatly.
In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
Existing ULP regulators can vary quite significantly. Switch capacitor regulators appear to be the most common architecture where a battery powered device is designed to incur significant amounts of standby operation compared to active operation. Control of switched-capacitor regulators can also vary. More common control flavors can include hysteretic control or output voltage control. A hysteretic control for a switch capacitor regulator typically is enabled when an output voltage hits a lower limit and then is disabled when the output voltage hits an upper limit. Such a control ensures the output voltage is related with the upper and lower limits. In certain designs, a regulator having hysteretic control can include a battery monitor to allow a gain adjustment as the battery voltage changes. If gain selection is limited, efficiency can vary significantly over the range of possible battery voltages. Also, hysteretic controlled regulators typically do not monitor load current resulting in significant power loss at light loads.
ULP regulators employing output voltage control can adapt the gain of the regulator based on the output voltage. Such control allows for a gain selection that indirectly considers battery voltage and load current. Such controllers typically provide more gains to select from which can help with efficiency over a wide range of output voltages or battery voltages.
The present inventors have recognized an improved control method that allows for improved efficiency of a switch capacitor buck regulator. In general, the inventors have recognized that power provided by a battery when using a switch capacitor buck regulator can be minimized using three factors:
Hysteretic control schemes can satisfy the third factor but cannot meet the first and second factors. Output voltage based control can meet the first factor. In some versions, with enough gain selection, a switch capacitor regulator using output voltage control may be able to meet the second factor. However, switch-capacitor, output-voltage controlled regulators do not meet the third factor as such control schemes continuously switch the regulator.
On can model a battery supplied buck regulator mathematically for example by,
V
OUT
=A·V
BAT, (Eq. 1)
I
BAT
=A·I
LOAD, (Eq. 2)
where A is the gain of the regulator and is <1, VOUT is the output voltage of the regulator, VBAT is the battery voltage supplied to the regulator, IBAT is the current supplied by the battery, and ILOAD is the current consumed by the load connected to the regulator output.
If the impedance (Z0) of the regulator is included, Eq. 1 becomes.
V
OUT
=A·V
BAT
−I
LOAD
·Z
0 (Eq. 3)
The power drawn from the battery (PBAT) can be expressed as,
P
BAT
=V
BAT
·I
BAT=(VOUT+ILOAD·Z0)·ILOAD (Eq. 4)
P
BAT
=V
OUT
·I
LOAD+(A·VBAT−VOUT)·ILOAD (Eq. 5)
P
BAT
=A·V
BAT
·I
LOAD (Eq. 6)
The load current (ILOAD) can be expressed as,
I
LOAD
=I
FIXED
+k·V
OUT
a, (Eq. 7)
where a=1 for dynamic current and a higher order for leakages. Consequently, there is a portion of the power used from the battery that depends on the output voltage of the regulator. In a more precise model, the total power drawn from the battery can also include losses in the regulator (PLOSS), for example, due to parasitic capacitance switching, or continuous operation of non-overlapping clock generation schemes. Editing the equations above, the battery power (PBAT) can be expressed as,
P
BAT
=A·V
BAT·(IFIXED+k·VOUTa)+PLOSS (Eq. 8)
The inventors have recognized that the switching losses associated with the k·VOUTa term in Eq. 8 can form a basis for making an incremental power saving improvement in regulator. The new control scheme uses modified output voltage based control to take advantage of the substantially constant output impedance characteristic resulting from uniformly, or linearly, interspersed gain settings and the ability to adapt to a minimum gain. The modification allows the control circuit to establish a lower upper voltage limit than the gain selection upper voltage limit after the minimum gain of the regulator is selected. The modification allows the regulator to provide an output voltage that, on average, is lower than scaled voltage associated with the regulator continuously operating with the selected gain. Operating the regulator with a lower voltage and resulting lower current reduces the power draw from the battery. In certain examples, control of the range of the output voltage closer to the lower limit can be achieved without having to increase the gain resolution of an existing output voltage based controller. Additional power savings, for example, via lower switching losses, can be achieved by using hysteretic control to regulate the output voltage closer to the lower voltage limit.
Furthermore, hysteretic control can also allow supporting higher loads by increasing the clock frequency without incurring more losses at lighter loads. Employing the new “lower” upper voltage threshold or low-power threshold (H′) close to the lower threshold (L) can also ensure that the regulator's on-to-off time ratio is lower, hence reducing losses even further. For example, once the clock is switched “on” after the regulator discharges to the lower threshold (L), the charging time of the equivalent RC network of the system (e.g., Z0Cload) increases exponentially as the output voltage rises (so keeping H′ low compared to the scaled voltage helps) whereas the voltage discharge, once the regulator reaches the new lower upper threshold (H′) and is switched “off”, is a function of load current and load capacitance (Cload) and hence is linear with time. Therefore, by lowering the upper voltage threshold (H) to the low-power threshold (H′), the “on” time of the regulator can be reduced significantly.
In certain examples, the controller 105 can use the dynamic voltage divider 107 to disable the clock 104 or otherwise interrupt the switching of the capacitor configuration of the switched-capacitor network 103 to permit the output voltage (Vout) to fall below the scaled output voltage, but to remain above a lower limit of the desired output voltage range. In certain examples, the comparator 109 can enable and disable the clocking of the capacitor network 103 based on a comparison of an output of the dynamic voltage divider 107 and a reference voltage (Vref). Interrupting the switching of the capacitors of the switched-capacitor network 103 while not allowing the output voltage (Vout) to fall below a lower threshold of the desired or predetermined output voltage range can reduce switching losses of the regulator 100 while also delivering close to the minimum power needed to allow the load to function properly.
In certain examples, the controller 105 can disable the clock circuit 104 to interrupt switching of the capacitor configuration of the switched-capacitor network 103. In such examples, the controller 105 can interrupt the clock when the output voltage meets or exceeds a low-power threshold (H′). The low-power threshold (H′) can be significantly lower than either the scaled output voltage or the upper voltage limit (H) of the desired or predetermined output voltage range. If the load current remains steady, as is usually the case when a device is in a low-power mode or a sleep mode, the power consumed by the load 102 will generally be consumed at a lower voltage and a lower current draw than if the switched-capacitor network 103 remained in a constant switching mode. In certain examples, the low-power threshold (H′) can be established by modifying the feedback circuit such as by dynamically re-configuring the dynamic voltage divider 107. In certain examples, the dynamic voltage divider 107 can be modified for the low-power threshold (H′) such that, at the comparator 109, the feedback voltage appears to be at the upper limit (H) of the desired or predefined output voltage range when the actual output voltage (Vout) is at the low-voltage threshold (H′).
After the clock circuit 104 is interrupted when the output voltage (Vout) is at the low-power threshold (H′), the controller 105 can enable the clock circuit 104 when the output voltage (Vout) level meets or falls below a lower limit (L) of the desired or predetermined output voltage range. In certain examples, if the current draw changes, such as increases, the existing gain of the regulator 100 may not allow the output voltage (Vout) to climb to the low-power threshold (H′) or may take an extended amount of time to achieve the low-power threshold (H′). The controller 105 can include a timer or counter to timeout an expected interval, after the clock circuit 104 is enabled, that the output voltage (Vout) should return to the low-power threshold (H′). The timer or counter can be reset when the output voltage (Vout) reaches the low-power threshold (H′). If the timer or counter reaches a timeout value, it can be an indication of a gain mismatch issue and can initiate a gain change of the regulator 100. In such a circumstance, the controller 105 can change one or more of the gain or the configuration of the dynamic voltage divider 107 to make sure the regulator 100 provides an adequate amount of power at a voltage within the desired or predetermined output voltage range. In certain examples, a gain mismatch issue can be detected when the voltage passes a minimum low-voltage limit with a value lower than the lower limit (L) of the desired or predetermined output voltage range.
If the current draw of the load changes, for example, increases at 404, such an increase can delay or prevent the switched-capacitor regulator from raising the output voltage at the same rate as when the current draw of the load was lower. The control logic of the regulator can monitor the increased delay between enabling the switching of the regulator and when the output voltage reaches the second, high voltage limit. If the delay is longer than a predetermined threshold, the control logic of the regulator can attempt to establish a gain to support the increased current draw of the load and the process can repeat such as at 405.
More specifically, in accordance with some embodiments, the converter includes n+m switched capacitors. As explained more fully below, an n set containing n switched capacitors act in an ‘n-role’ and an m set containing m switched capacitors act in an ‘m-role’. The number of switched capacitors in the n set and the number of switched capacitors in the m set is varied to vary gain across the converter. Referring to
As used herein the n-role refers to the configuration of n switched capacitors in parallel with each other and in series with CRes during the discharge phase. Each switched capacitor in the n set is configured through one or more switches to be coupled in parallel with each other switched capacitor acting in the n set and in series with CRes during the charge phase. As used herein, the m-role refers to the configuration of m switched capacitors that are coupled in parallel with each other and with CRes during the discharge phase. Each switched capacitor in the m set is configured through one or more switches to be coupled in parallel with each other switched capacitor in the m set and in parallel with CRes during the discharge phase. In accordance with some embodiments, the switched capacitors in the m set are coupled, during the discharge phase, with their polarities reversed relative to their coupling during the charge phase.
A Load side includes the voltage,
impedance (Z0), the reservoir capacitor (CL) and a Load current (IL) source. Impedance (Z0) coupled in parallel with the reservoir capacitance CL represents impedance due to the switched capacitors.
The number of switched capacitors in the n set and the number of switched capacitors in the m set is selectively varied with desired gain across the converter. However, in accordance with some embodiments, the same total number of switched capacitors, m+n, is used for each of multiple different gains. Moreover, in accordance with some embodiments, at least some of the polarities of the m switch capacitors selected to be in the m-role are reversed when coupled in parallel during the discharge phase.
Gain (A) is represented as follows,
It is noted that gain varies substantially linearly with the number of switched capacitors in the n set.
Output impedance of the converter is represented as follows,
The value (f) represents the switching frequency of capacitor switching; the value (C) is the value of the individual switched capacitors. It is noted that the output impedance is independent of the gain setting. Thus, it is possible to vary the gain with the confidence that the voltage drop of the converter does not vary substantially with gain, which facilitates ease of regulation of the output voltage Vout.
It will be appreciated that an advantage of a configuration of an n set of switched capacitors and an m set of switched capacitors into n-roles and m-roles as described above is that substantially all the integrated circuit (IC) area used to implement capacitors contributes to improve the output impedance, since the number of n capacitors and m capacitors is added up to arrive at the output impedance Z0. In accordance with some embodiments, once a given chip area is committed to act as a switched capacitor block, it can be advantageous to divide it up in many capacitor devices so as to produce many different gains. In general, the larger the number of different gains, the higher the efficiency achievable over the input voltage supply range. A limit to the number of gains arises, however, due to the fact that adding more switched capacitors necessitates more switches to control them.
Battery current used in charging the switch capacitors is represented as follows,
The value IL represents the current through the Load that is driven by the converter. It is noted that Ibat is less than IL by the gain factor (A). The battery current only depends on the load current, which means that no charge sharing occurs among the capacitors.
Output voltage (Vout) produced by the converter to drive the Load is represented as follows,
Efficiency (ε) of the converter is represented as follows,
The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.
In the event of inconsistent usages between this document and any documents so incorporated by reference, the usage in this document controls.
In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of“at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term are still deemed to fall within the scope of subject matter discussed. Moreover, such as may appear in a claim, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.
The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of a claim. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. The following aspects are hereby incorporated into the Detailed Description as examples or embodiments, with each aspect standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations.
