Patent Application
20190065281
Network operators and service providers typically rely on various accelerator technologies to accelerate workloads in complex, large-scale computing environments, such as high-performance computing (HPC) and cloud computing environments. These accelerators can be configured to perform special purpose computations (e.g., searching, pattern matching, signal- and image-processing, encryption, etc.) in an efficient, parallel manner. One such accelerator technology is a field-programmable gate array (FPGA) consisting of an array of logic gates that can be hardware-programmed to fulfill specific tasks. In particular, the clock cycles of FPGAs are relatively low compared to processor clock rates, which means the FPGAs are generally more power effective relative to processor cores.
Accordingly, in some computing architectures, while hardware threads of an application are being executed by a processor, certain application functionality (e.g., compute kernels) may be offloaded to an FPGA. Typically, the hardware threads of the application are paused while waiting for the compute kernels to execute in the FPGA. However, because the hardware threads are merely paused, the software stack is required to make the decision to pause/resume, which can be an ineffective solution under certain conditions. Additionally, pausing/resuming the application threads presently works in the order of milliseconds (e.g., driven by software interactions) and consider only a binary solution (i.e., pause/resume), which can be an inflexible solution in certain computing environments.
The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).
In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.
Referring now to
Referring now to
It should be appreciated that each of the other pods 120, 130, 140 (as well as any additional pods of the data center 100) may be similarly structured as, and have components similar to, the pod 110 shown in and described in regard to
Referring now to
In the illustrative embodiments, each sled of the data center 100 is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, the rack 240 is configured to receive the chassis-less sleds. For example, each pair 310 of elongated support arms 312 defines a sled slot 320 of the rack 240, which is configured to receive a corresponding chassis-less sled. To do so, each illustrative elongated support arm 312 includes a circuit board guide 330 configured to receive the chassis-less circuit board substrate of the sled. Each circuit board guide 330 is secured to, or otherwise mounted to, a top side 332 of the corresponding elongated support arm 312. For example, in the illustrative embodiment, each circuit board guide 330 is mounted at a distal end of the corresponding elongated support arm 312 relative to the corresponding elongated support post 302, 304. For clarity of the Figures, not every circuit board guide 330 may be referenced in each Figure.
Each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 configured to receive the chassis-less circuit board substrate of a sled 400 when the sled 400 is received in the corresponding sled slot 320 of the rack 240. To do so, as shown in
It should be appreciated that each circuit board guide 330 is dual sided. That is, each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 on each side of the circuit board guide 330. In this way, each circuit board guide 330 can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to the rack 240 to turn the rack 240 into a two-rack solution that can hold twice as many sled slots 320 as shown in
In some embodiments, various interconnects may be routed upwardly or downwardly through the elongated support posts 302, 304. To facilitate such routing, each elongated support post 302, 304 includes an inner wall that defines an inner chamber in which the interconnect may be located. The interconnects routed through the elongated support posts 302, 304 may be embodied as any type of interconnects including, but not limited to, data or communication interconnects to provide communication connections to each sled slot 320, power interconnects to provide power to each sled slot 320, and/or other types of interconnects.
The rack 240, in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with a corresponding sled slot 320 and is configured to mate with an optical data connector of a corresponding sled 400 when the sled 400 is received in the corresponding sled slot 320. In some embodiments, optical connections between components (e.g., sleds, racks, and switches) in the data center 100 are made with a blind mate optical connection. For example, a door on each cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable enters the connector mechanism. Subsequently, the optical fiber inside the cable enters a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism.
The illustrative rack 240 also includes a fan array 370 coupled to the cross-support arms of the rack 240. The fan array 370 includes one or more rows of cooling fans 372, which are aligned in a horizontal line between the elongated support posts 302, 304. In the illustrative embodiment, the fan array 370 includes a row of cooling fans 372 for each sled slot 320 of the rack 240. As discussed above, each sled 400 does not include any on-board cooling system in the illustrative embodiment and, as such, the fan array 370 provides cooling for each sled 400 received in the rack 240. Each rack 240, in the illustrative embodiment, also includes a power supply associated with each sled slot 320. Each power supply is secured to one of the elongated support arms 312 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320. For example, the rack 240 may include a power supply coupled or secured to each elongated support arm 312 extending from the elongated support post 302. Each power supply includes a power connector configured to mate with a power connector of the sled 400 when the sled 400 is received in the corresponding sled slot 320. In the illustrative embodiment, the sled 400 does not include any on-board power supply and, as such, the power supplies provided in the rack 240 supply power to corresponding sleds 400 when mounted to the rack 240.
Referring now to
As discussed above, the illustrative sled 400 includes a chassis-less circuit board substrate 602, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that the circuit board substrate 602 is “chassis-less” in that the sled 400 does not include a housing or enclosure. Rather, the chassis-less circuit board substrate 602 is open to the local environment. The chassis-less circuit board substrate 602 may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, the chassis-less circuit board substrate 602 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-less circuit board substrate 602 in other embodiments.
As discussed in more detail below, the chassis-less circuit board substrate 602 includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602. As discussed, the chassis-less circuit board substrate 602 does not include a housing or enclosure, which may improve the airflow over the electrical components of the sled 400 by reducing those structures that may inhibit air flow. For example, because the chassis-less circuit board substrate 602 is not positioned in an individual housing or enclosure, there is no backplane (e.g., a backplate of the chassis) to the chassis-less circuit board substrate 602, which could inhibit air flow across the electrical components. Additionally, the chassis-less circuit board substrate 602 has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-less circuit board substrate 602. For example, the illustrative chassis-less circuit board substrate 602 has a width 604 that is greater than a depth 606 of the chassis-less circuit board substrate 602. In one particular embodiment, for example, the chassis-less circuit board substrate 602 has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, an airflow path 608 that extends from a front edge 610 of the chassis-less circuit board substrate 602 toward a rear edge 612 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of the sled 400. Furthermore, although not illustrated in
As discussed above, the illustrative sled 400 includes one or more physical resources 620 mounted to a top side 650 of the chassis-less circuit board substrate 602. Although two physical resources 620 are shown in
The sled 400 also includes one or more additional physical resources 630 mounted to the top side 650 of the chassis-less circuit board substrate 602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of the sled 400, the physical resources 630 may include additional or other electrical components, circuits, and/or devices in other embodiments.
The physical resources 620 are communicatively coupled to the physical resources 630 via an input/output (I/O) subsystem 622. The I/O subsystem 622 may be embodied as circuitry and/or components to facilitate input/output operations with the physical resources 620, the physical resources 630, and/or other components of the sled 400. For example, the I/O subsystem 622 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative embodiment, the I/O subsystem 622 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDRS data bus.
In some embodiments, the sled 400 may also include a resource-to-resource interconnect 624. The resource-to-resource interconnect 624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect 624 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the resource-to-resource interconnect 624 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.
The sled 400 also includes a power connector 640 configured to mate with a corresponding power connector of the rack 240 when the sled 400 is mounted in the corresponding rack 240. The sled 400 receives power from a power supply of the rack 240 via the power connector 640 to supply power to the various electrical components of the sled 400. That is, the sled 400 does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of the sled 400. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-less circuit board substrate 602, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602 as discussed above. In some embodiments, power is provided to the processors 820 through vias directly under the processors 820 (e.g., through the bottom side 750 of the chassis-less circuit board substrate 602), providing an increased thermal budget, additional current and/or voltage, and better voltage control over typical boards.
In some embodiments, the sled 400 may also include mounting features 642 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled 600 in a rack 240 by the robot. The mounting features 642 may be embodied as any type of physical structures that allow the robot to grasp the sled 400 without damaging the chassis-less circuit board substrate 602 or the electrical components mounted thereto. For example, in some embodiments, the mounting features 642 may be embodied as non-conductive pads attached to the chassis-less circuit board substrate 602. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-less circuit board substrate 602. The particular number, shape, size, and/or make-up of the mounting feature 642 may depend on the design of the robot configured to manage the sled 400.
Referring now to
The memory devices 720 may be embodied as any type of memory device capable of storing data for the physical resources 620 during operation of the sled 400, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include next-generation nonvolatile devices, such as Intel 3D XPoint™ memory or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
Referring now to
In the illustrative compute sled 800, the physical resources 620 are embodied as processors 820. Although only two processors 820 are shown in
In some embodiments, the compute sled 800 may also include a processor-to-processor interconnect 842. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the processor-to-processor interconnect 842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 842 communications. In the illustrative embodiment, the processor-to-processor interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the processor-to-processor interconnect 842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
The compute sled 800 also includes a communication circuit 830. The illustrative communication circuit 830 includes a network interface controller (NIC) 832, which may also be referred to as a host fabric interface (HFI). The NIC 832 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, other devices that may be used by the compute sled 800 to connect with another compute device (e.g., with other sleds 400). In some embodiments, the NIC 832 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 832 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 832. In such embodiments, the local processor of the NIC 832 may be capable of performing one or more of the functions of the processors 820. Additionally or alternatively, in such embodiments, the local memory of the NIC 832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels.
The communication circuit 830 is communicatively coupled to an optical data connector 834. The optical data connector 834 is configured to mate with a corresponding optical data connector of the rack 240 when the compute sled 800 is mounted in the rack 240. Illustratively, the optical data connector 834 includes a plurality of optical fibers which lead from a mating surface of the optical data connector 834 to an optical transceiver 836. The optical transceiver 836 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of the optical data connector 834 in the illustrative embodiment, the optical transceiver 836 may form a portion of the communication circuit 830 in other embodiments.
In some embodiments, the compute sled 800 may also include an expansion connector 840. In such embodiments, the expansion connector 840 is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to the compute sled 800. The additional physical resources may be used, for example, by the processors 820 during operation of the compute sled 800. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-less circuit board substrate 602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.
Referring now to
As discussed above, the individual processors 820 and communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. In the illustrative embodiment, the processors 820 and communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those physical resources are linearly in-line with others along the direction of the airflow path 608. It should be appreciated that, although the optical data connector 834 is in-line with the communication circuit 830, the optical data connector 834 produces no or nominal heat during operation.
The memory devices 720 of the compute sled 800 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the processors 820 located on the top side 650 via the I/O subsystem 622. Because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the processors 820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Of course, each processor 820 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments. Alternatively, in other embodiments, each processor 820 may be communicatively coupled to each memory device 720. In some embodiments, the memory devices 720 may be mounted to one or more memory mezzanines on the bottom side of the chassis-less circuit board substrate 602 and may interconnect with a corresponding processor 820 through a ball-grid array.
Each of the processors 820 includes a heatsink 850 secured thereto. Due to the mounting of the memory devices 720 to the bottom side 750 of the chassis-less circuit board substrate 602 (as well as the vertical spacing of the sleds 400 in the corresponding rack 240), the top side 650 of the chassis-less circuit board substrate 602 includes additional “free” area or space that facilitates the use of heatsinks 850 having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602, none of the processor heatsinks 850 include cooling fans attached thereto. That is, each of the heatsinks 850 is embodied as a fan-less heatsinks.
Referring now to
In the illustrative accelerator sled 1000, the physical resources 620 are embodied as accelerator circuits 1020. Although only two accelerator circuits 1020 are shown in
In some embodiments, the accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042. Similar to the resource-to-resource interconnect 624 of the sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the accelerator-to-accelerator interconnect 1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, the accelerator circuits 1020 may be daisy-chained with a primary accelerator circuit 1020 connected to the NIC 832 and memory 720 through the I/O subsystem 622 and a secondary accelerator circuit 1020 connected to the NIC 832 and memory 720 through a primary accelerator circuit 1020.
Referring now to
Referring now to
In the illustrative storage sled 1200, the physical resources 620 are embodied as storage controllers 1220. Although only two storage controllers 1220 are shown in
In some embodiments, the storage sled 1200 may also include a controller-to-controller interconnect 1242. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
Referring now to
The storage cage 1252 illustratively includes sixteen mounting slots 1256 and is capable of mounting and storing sixteen solid state drives 1254. Of course, the storage cage 1252 may be configured to store additional or fewer solid state drives 1254 in other embodiments. Additionally, in the illustrative embodiment, the solid state drivers are mounted vertically in the storage cage 1252, but may be mounted in the storage cage 1252 in a different orientation in other embodiments. Each solid state drive 1254 may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives 1254 may include volatile and non-volatile memory devices discussed above.
As shown in
As discussed above, the individual storage controllers 1220 and the communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. For example, the storage controllers 1220 and the communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those electrical components are linearly in-line with other along the direction of the airflow path 608.
The memory devices 720 of the storage sled 1200 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the storage controllers 1220 located on the top side 650 via the I/O subsystem 622. Again, because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the storage controllers 1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Each of the storage controllers 1220 includes a heatsink 1270 secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602 of the storage sled 1200, none of the heatsinks 1270 include cooling fans attached thereto. That is, each of the heatsinks 1270 is embodied as a fan-less heatsink.
Referring now to
In the illustrative memory sled 1400, the physical resources 620 are embodied as memory controllers 1420. Although only two memory controllers 1420 are shown in
In some embodiments, the memory sled 1400 may also include a controller-to-controller interconnect 1442. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some embodiments, a memory controller 1420 may access, through the controller-to-controller interconnect 1442, memory that is within the memory set 1432 associated with another memory controller 1420. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled 1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, the memory controllers 1420 may implement a memory interleave (e.g., one memory address is mapped to the memory set 1430, the next memory address is mapped to the memory set 1432, and the third address is mapped to the memory set 1430, etc.). The interleaving may be managed within the memory controllers 1420, or from CPU sockets (e.g., of the compute sled 800) across network links to the memory sets 1430, 1432, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.
Further, in some embodiments, the memory sled 1400 may be connected to one or more other sleds 400 (e.g., in the same rack 240 or an adjacent rack 240) through a waveguide, using the waveguide connector 1480. In the illustrative embodiment, the waveguides are 64 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Rt (i.e., transmit) lanes. Each lane, in the illustrative embodiment, is either 16 Ghz or 32 Ghz. In other embodiments, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets 1430, 1432) to another sled (e.g., a sled 400 in the same rack 240 or an adjacent rack 240 as the memory sled 1400) without adding to the load on the optical data connector 834.
Referring now to
Additionally, in some embodiments, the orchestrator server 1520 may identify trends in the resource utilization of the workload (e.g., the application 1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 1532) and pre-emptively identifying available resources in the data center 100 and allocating them to the managed node 1570 (e.g., within a predefined time period of the associated phase beginning). In some embodiments, the orchestrator server 1520 may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center 100. For example, the orchestrator server 1520 may utilize a model that accounts for the performance of resources on the sleds 400 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, the orchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and the sled 400 on which the resource is located).
In some embodiments, the orchestrator server 1520 may generate a map of heat generation in the data center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the sleds 400 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center 100. Additionally or alternatively, in some embodiments, the orchestrator server 1520 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center 100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. The orchestrator server 1520 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center 100.
To reduce the computational load on the orchestrator server 1520 and the data transfer load on the network, in some embodiments, the orchestrator server 1520 may send self-test information to the sleds 400 to enable each sled 400 to locally (e.g., on the sled 400) determine whether telemetry data generated by the sled 400 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Each sled 400 may then report back a simplified result (e.g., yes or no) to the orchestrator server 1520, which the orchestrator server 1520 may utilize in determining the allocation of resources to managed nodes.
Referring now to
Further, a phase detection logic unit 1610 of each compute sled 1602 collects telemetry data (e.g., top-down microarchitecture analysis method (TMAM) metrics) indicative of a resource usage and/or performance condition of the respective sleds as application workloads are being performed on the respective sleds. The phase detection logic unit 1610, which will be described in further detail below, is configured to analyze the collected data to identify when a given application, executing a set of hardware threads on a central processing unit (CPU) of a compute sled 1602 or an accelerator sled 1618, changes to a different phase, such as one of a compute bound phase, an FPGA bound phase, a memory bound phase, etc.
Additionally, the phase detection logic unit 1610 is configured to determine whether a given application needs to be migrated to another CPU of the compute sled 1602 or the accelerator sled 1618 on which the application is presently being executed, or migrated to another CPU of a different compute sled 1602 or accelerator sled 1618. To do so, the phase detection logic unit 1610 is further configured to determine whether the likelihood of staying in the new, present phase is high enough to migrate the hardware threads and/or an associated compute kernel to another sled, or sleds. Such a determination may depend on an anticipated duration of time of the present phase or other prediction algorithm. If the phase detection logic unit 1610 determines that the hardware threads and/or the compute kernel are to be migrated, the phase detection logic unit 1610 orchestrates the migration process and either offlines the previously used CPU or returns the previously used CPU to the operating system of the applicable sled. It should be appreciated that, as illustratively shown, the phase detection logic unit 1610, or at least a portion thereof, may reside on each of the compute sleds 1602, the network switch 1612, and/or the resource hardware manager 1608, depending on the embodiment. It should be further appreciated that, while illustratively shown in a disaggregated architecture, the functions described herein may be performed on a local multi-processor computing device or configurable platform (e.g., the Intel® Discrete Configurable Platform) in other embodiments.
Each of the compute sleds 1602 may be embodied as any type of compute device capable of performing the functions described herein. As shown in
The compute engine 1702 may be embodied as any type of device or collection of devices capable of performing the various compute functions as described herein. In some embodiments, the compute engine 1702 may be embodied as a single device such as an integrated circuit, an embedded system, an FPGA, a system-on-a-chip (SOC), an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein. Additionally, in some embodiments, the compute engine 1702 may include, or may be embodied as, a processor 1704 (i.e., a central processing unit (CPU)) and memory 1706.
The processor 1704 may be embodied as any type of processor capable of performing the functions described herein. For example, the processor 1704 may be embodied as one or more single-core processors, multi-core processors, digital signal processors, microcontrollers, or other processor(s) or processing/controlling circuit(s). In some embodiments, the processor 1704 may be embodied as, include, or otherwise be coupled to a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein.
As illustratively shown, the processor 1704 may include the phase detection logic unit 1610 described with reference to
The memory 1706 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein. It should be appreciated that the memory 1706 may include main memory (i.e., a primary memory) and/or cache memory (i.e., memory that can be accessed more quickly than the main memory). Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM).
One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include future generation nonvolatile devices, such as a three dimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.
In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™ memory) may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In some embodiments, all or a portion of the memory 1706 may be integrated into the processor 1704. In operation, the memory 1706 may store various software and data used during operation such as job request data, kernel map data, telemetry data, applications, programs, libraries, and drivers.
The compute engine 1702 is communicatively coupled to other components of the network switch 1612 via the I/O subsystem 1708, which may be embodied as circuitry and/or components to facilitate input/output operations with the processor 1704, the memory 1706, and other components of the network switch 1612. For example, the I/O subsystem 1708 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem 1708 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with one or more of the processor 1704, the memory 1706, and other components of the network switch 1612, on a single integrated circuit chip.
The one or more data storage devices 1710 may be embodied as any type of storage device(s) configured for short-term or long-term storage of data, such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. Each data storage device 1710 may include a system partition that stores data and firmware code for the data storage device 1710. Each data storage device 1710 may also include an operating system partition that stores data files and executables for an operating system.
The communication circuitry 1712 may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications between the network switch 1612 and other compute devices (e.g., the compute sleds 1602, the storage sled 1614, the accelerator sleds 1618, the resource hardware manager 1608, etc.). Accordingly, the communication circuitry 1712 may be configured to use any one or more communication technology (e.g., wired or wireless communications) and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, etc.) to effect such communication.
The illustrative communication circuitry 1712 includes a network interface controller (NIC) 1714, which may also be referred to as a host fabric interface (HFI). The NIC 1714 may be embodied as one or more add-in-boards, daughtercards, network interface cards, controller chips, chipsets, or other devices that may be used by the network switch 1612 to connect with another compute device (e.g., one of the compute sleds 1602 of
The one or more peripheral devices 1716 may include any type of device that is usable to input information into the network switch 16121606 and/or receive information from the network switch 1612. The peripheral devices 1716 may be embodied as any auxiliary device usable to input information into the network switch 1612, such as a keyboard, a mouse, a microphone, a barcode reader, an image scanner, etc., or output information from the network switch 1612, such as a display, a speaker, graphics circuitry, a printer, a projector, etc. It should be appreciated that, in some embodiments, one or more of the peripheral devices 1716 may function as both an input device and an output device (e.g., a touchscreen display, a digitizer on top of a display screen, etc.). It should be further appreciated that the types of peripheral devices 1716 connected to the network switch 1612 may depend on, for example, the type and/or intended use of the network switch 1612. Additionally or alternatively, in some embodiments, the peripheral devices 1716 may include one or more ports, such as a USB port, for example, for connecting external peripheral devices to the network switch 1612.
Referring now to
In the illustrative embodiment, the environment 1800 additionally includes telemetry data 1802, phase change data 1804, and migration policy data 1806, each of which may be embodied as any data established by the network switch 1612. The telemetry data 1802 may include any data usable to resource usage and/or performance of a computing element (e.g., a CPU) of a compute sled 1602 or an accelerator sled 1618. In some embodiments, the telemetry data 1802 may also include information about network traffic passing through the network switch 1612, including network congestion information and frequencies of data access requests and responses to/from the compute sleds 1602, the accelerator sleds 1618, the storage sled 1614, etc. The phase change data 1804 may include any data usable to identify phase changes (e.g., thresholds, expected durations, historical information, etc.) of various applications. The migration policy data 1806 may include any data (e.g., rules or policies) usable to instruct the network switch 1612 how/where to migrate hardware threads and/or compute kernels (e.g., under certain conditions).
The network connection manager 1810, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from the network switch 1612, respectively. To do so, the network connection manager 1810 is configured to receive and process data packets from one system or computing device (e.g., one of the compute sleds 1602, the resource hardware manager 1608, the storage sled 1614, one of the accelerator sleds 1618, etc.) and to prepare and send data packets to another computing device or system (e.g., one of the compute sleds 1602, the resource hardware manager 1608, the storage sled 1614, one of the accelerator sleds 1618, etc.). Accordingly, in some embodiments, at least a portion of the functionality of the network connection manager 1810 may be performed by the communication circuitry 1712, or more particularly by the NIC 1714.
As described previously, the phase detection logic unit 1610 is configured to analyze collected telemetry data to determine a phase change and orchestrate a migration of an application (i.e., the hardware threads of an application) and, under certain conditions, a compute kernel (i.e., a routine compiled for high throughput accelerators) associated with the migrated application. To do so, the illustrative phase detection logic unit 1610 includes a telemetry data collector 1812, a phase change detector 1814, and a migration manager 1816. The telemetry data collector 1812, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to collect telemetry data (e.g., the telemetry data 1802) reported by the compute sleds 1602 and the accelerator sleds 1618 the workloads are executed thereon and compute kernels have been offloaded therefrom.
As described previously, at least a portion of the phase detection logic unit 1610 may be performed by the network switch 1612 and/or the resource hardware manager 1608. In such embodiments in which the telemetry data collection is performed by the resource hardware manager 1608, for example, the telemetry data may be destined for the resource hardware manager 1608 and collected upon receipt. In such embodiments in which the telemetry data is collected by the network switch 1612, for example, as network packets containing the telemetry data pass through the network switch 1612 (e.g., through the network connection manager 1810), the telemetry data identifies those network packets and stores the telemetry data locally in the network switch 1612. It should be appreciated that, in either embodiment, an association with an identifier of the corresponding sled, or more particularly a corresponding compute element (i.e., a CPU, an FPGA, etc.) of that sled, is stored with the telemetry data.
The phase change detector 1814, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to detect a phase change of an application subsequent to having executed a compute kernel. As described previously the phases include, but are not limited to, a CPU bound phase, an FPGA bound phase, and a memory bound phase. For example, the phase change detector 1814 is configured to detect when the application changes its behavior from a CPU bound phase to a different phase after the compute kernel execution has started. To do so, the phase change detector 1814 is configured to analyze the collected telemetry data (e.g., the telemetry data 1802) to determine whether a certain condition, or conditions, exists which indicates a phase change. For example, the phase change detector 1814 may be configured to compare an IPC value to a threshold peak IPC value. In another example, the phase change detector 1814 may be configured to identify an amount of time a particular phase has taken historically to determine whether efficiencies can be realized by migrating the application's hardware threads to another compute element.
The migration manager 1816, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to migrate hardware threads associated with an application to another compute element. To do so, the migration manager 1816 is configured to receive an indication of a detected phase change (e.g., from the phase change detector 1814) that indicates the application is to be migrated. The migration manager 1816 is additionally configured identify the other compute element the application is to be migrated to by transmitting a compute element identification request to the resource hardware manager 1608 which is usable by the resource hardware manager 1608 to identify the other compute element (e.g., based on requirements of the workload associated with the hardware threads). Further, the migration manager 1816 is configured to pause the running hardware threads, migrate their status to the identified other compute element, and resume the hardware threads. Additionally, the migration manager 1816 is configured to notify the appropriate operating system and/or the resource manager server 1808 of the completed hardware thread migration.
It should be appreciated that each of the telemetry data collector 1812, the phase change detector 1814, and the migration manager 1816 may be separately embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof. For example, the telemetry data collector 1812 may be embodied as a hardware component, while the phase change detector 1814 and/or the migration manager 1816 may be embodied as virtualized hardware components or as some other combination of hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof. Further it should be appreciated that, in other embodiments, the compute sleds 1602 and/or the resource hardware manager 1608 may include at least a portion of the phase detection logic unit 1610 and may therefor establish an environment similar to the environment 1800 described herein.
Referring back to
The network switch 1612 may be embodied as any type of networking device capable of performing the functions described herein, including switching network packets between the compute sleds 1602, the resource hardware manager 1608, the storage sled 1614, and the accelerator sleds 1618, as well as any other computing devices communicatively coupled to the network switch 1612. Depending on the deployment environment, the network switch 1612 may be embodied as a top-of-rack switch, a middle-of-rack switch, or other Ethernet switch. It should be appreciated that the network switch 1612 may include components similar to those described in the illustrative compute sled 1602 of
The storage sled 1614 may be embodied as any type of storage device capable of performing the functions described herein, such as managing a pool of storage devices 1616 (e.g., physical storage resources 205-1). To do so, the storage sled 1614 may a memory pool controller (not shown) embodied as virtual and/or physical hardware, firmware, software, or a combination thereof, which is configured to manage data into and out of the storage devices 1616. It should be appreciated that while only a single storage sled 1614 is shown, other embodiments may include more than one storage sled 1614.
The storage devices 1616 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM).
One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the storage devices 1616 may be embodied as a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include future generation nonvolatile devices, such as a three dimensional (3D) crosspoint memory device (e.g., Intel 3D XPoint™ memory), or other byte addressable write-in-place nonvolatile memory devices. In such embodiments, the 3D crosspoint memory (e.g., Intel 3D XPoint™ memory) may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
In another embodiment, the storage devices 1616 may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.
As described previously, the compute sleds 1602 may be pooled, as illustratively shown in the high-performance processing sleds 1134 of
As described previously, the accelerator sleds 1618 may be pooled, as illustratively shown in the pooled accelerator sleds 1130 of
It should be appreciated that, in some embodiments, one or more of the compute sleds 1602 and/or accelerator sleds 1618 may be grouped into a managed node, such as by the resource hardware manager 1608, to collectively perform a workload, such as an application. A managed node may be embodied as an assembly of resources, such as compute resources, memory resources, storage resources, or other resources from the same or different sleds or racks.
Further, a managed node may be established, defined, or “spun up” by the resource hardware manager 1608 at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node. The resource hardware manager 1608 may, in some embodiments, perform one or more orchestration operations in support of a cloud operating environment, such as OpenStack, and managed nodes established by the resource hardware manager 1608 may execute one or more applications or processes (i.e., workloads), such as in the VMs or containers, on behalf of a user of a client device (not shown) communicatively coupled to the resource hardware manager 1608 (e.g., via a network).
Referring now to
Referring now to
In block 2112, the compute sled 1602 analyzes the collected telemetry to identify a phase change. To do so, in block 2114, the compute sled 1602 compares at least a portion of the telemetry data to one or more corresponding thresholds. For example, the compute sled 1602 may compare an IPC value against a peak IPC threshold for a particular compute element (e.g., a CPU). In block 2116, the compute sled 1602 determines whether a phase change has been detected as a result of the analysis performed in block 2112. As described previously the phases include, but are not limited to, a CPU bound phase, an FPGA bound phase, and a memory bound phase. If not, the method 2100 returns to block 2104 to continue to monitor the hardware threads; otherwise, if a phase change has been detected (e.g., from a CPU bound phase to another phase) the method 2100 advances to block 2118. In block 2118, the compute sled 1602 identifies a new compute element to migrate the hardware threads to.
It should be appreciated that, in some embodiments, the compute sled 1602 may not be capable of identifying the new compute element (e.g., due to the compute sled 1602 not having the necessary resource information available to do so). Accordingly, in such embodiments, the compute sled 1602 may transmit a request (e.g., a compute element identification request) to the resource hardware manager 1608 requesting the resource hardware manager 1608 to identify the new compute element and return the identified compute element. It should be appreciated that, in such embodiments, the resource hardware manager 1608 may be configured to identify the new compute element based on available resources of the compute sled 1602 on which the hardware threads are presently executing, the available resources of the other compute sleds 1602, and resource requirements of the workload associated with the hardware threads.
In block 2120, the compute sled 1602 migrates the hardware threads to the identified new compute element. To do so, in block 2122, the compute sled 1602 pauses the hardware threads running on the present compute element. Additionally, in block 2124, the compute sled 1602 migrates the hardware thread states to the other new compute element. Further, in block 2126, the compute sled 1602 resumes the migrated hardware threads. Finally, in block 2128, the compute sled 1602 takes the previously used compute element offline. In block 2130, the compute sled 1602 notifies the respective operating system associated with the application of the migration. In some embodiments, the compute sled 1602 may return the offlined compute element to the respective operating system.
In block 2132, the compute sled 1602 determines whether to also migrate the compute kernel associated with the migrated application from the FPGA 1622 on which the compute kernel is presently executing to a different FPGA 1622 (e.g., of a different one of the accelerator sleds 1618). If not, the method 2100 branches to block 2144 of
In block 2136, the compute sled 1602 migrates the compute kernel to the determined new FPGA. In block 2138, the compute sled 1602 notifies the application associated with the compute kernel of the compute kernel's migration to the new FPGA. In block 2140, the compute sled 1602 monitors a completion status of the compute kernel. In block 2142, the compute sled 1602 monitors a phase of the corresponding application. In block 2144, the compute sled 1602 determines whether to migrate the application from the new compute element which the hardware thread was migrated to in block 2120. To do so, for example, the compute sled 1602 may determine to migrate the application in response to having determined the compute kernel operation has completed, or is about to complete. Additionally or alternatively, the compute sled 1602 may determine to migrate the application in response to having detected the phase has changed back to a CPU bound phase.
If the compute sled 1602 determines not to migrate the application, the method 2100 returns to block 2140 to continue monitoring the completion statues of the compute kernel, as well as to continue monitoring the phase of the corresponding application in block 2142. Otherwise, if the compute sled 1602 determines to migrate the application, the method 2100 advances to block 2146 in which the compute sled 1602 identifies another new compute element to migrate the hardware threads to. As noted previously, the compute sled 1602 may rely on the resource hardware manager 1608 to identify the other new compute element and notify the compute sled 1602 of the identified other new compute element. In block 2148, the compute sled 1602 migrates the hardware threads to the identified other new compute element. To do so, in block 2150, the compute sled 1602 pauses the hardware threads running on the present compute element. Additionally, in block 2152, the compute sled 1602 migrates the hardware thread states to the other new compute element. Further, in block 2154, the compute sled 1602 resumes the migrated hardware threads. Finally, in block 2156, the compute sled 1602 offlines the previously used compute element. In block 2158, the compute sled 1602 notifies the respective operating system and the associated application of the successful migration. Accordingly, the application can make any reconfiguration changes to the application's software/network parameters as may be required as a result of the migration.
As noted previously, at least a portion of the phase detection logic unit 1610 may be in one or more of the compute sleds 1602, the resource hardware manager 1608, and the network switch 1612, in other embodiments. Accordingly, it should be appreciated that, in such embodiments, at least a portion of the method 2100 may be performed by the network switch 1612 and/or the resource hardware manager 1608 in addition or alternatively to the compute sleds 1602 as described herein. It should be further appreciated that while the method 2100 has been illustratively described as being performed by a disaggregated architecture, the functions described herein may be performed, in other embodiments, by a platform including a local multi-processor computing device and at least one FPGA, or a configurable platform (e.g., the Intel® Discrete Configurable Platform) having a multiple processors and at least one FPGA.
As described with respect to the method 2000 of
Referring now to
As illustratively shown in post-migration
Referring now to
Referring now to
Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
Example 1 includes a compute sled for auto-migration in accelerated architectures, the compute sled comprising a compute engine to receive, from an application executed on a first compute element of a compute sled of a plurality of compute sleds, an indication that a compute kernel associated with the application has been offloaded to a field-programmable gate array (FPGA) of an accelerator sled of a plurality of accelerator sleds, wherein each of the plurality of accelerator sleds and the plurality of compute sleds are communicatively coupled to the compute sled; monitor a plurality of hardware threads associated with the application; detect whether a phase change has been detected as a function of the monitored hardware threads; and migrate, in response to detected detection of the phase change, the hardware threads to a second compute element.
Example 2 includes the subject matter of Example 1, and wherein to monitor the plurality of hardware threads comprises to collect telemetry data corresponding to one or more hardware resources used by the hardware threads during execution.
Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to collect the telemetry data includes to collect an instructions per cycle (IPC) value of the first compute element.
Example 4 includes the subject matter of any of Examples 1-3, and wherein to detect whether the phase change has been detected comprises to compare the IPC value of the first compute element to a peak IPC threshold value.
Example 5 includes the subject matter of any of Examples 1-4, and wherein to detect whether the phase change has been detected comprises to identify a previous phase as a central processing unit (CPU) bound phase and identify a present phase as an FPGA bound phase.
Example 6 includes the subject matter of any of Examples 1-5, and wherein to detect whether the phase change has been detected comprises to identify a previous phase as a central processing unit (CPU) bound phase and identify a present phase as a memory bound phase.
Example 7 includes the subject matter of any of Examples 1-6, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein to migrate the hardware threads to the second compute element in response to having detected the phase change comprises to migrate the hardware threads to another high-performance CPU of the compute sled.
Example 8 includes the subject matter of any of Examples 1-7, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein to migrate the hardware threads to the second compute element in response to having detected the phase change comprises to migrate the hardware threads to a high-performance CPU of another compute sled of the plurality of compute sleds.
Example 9 includes the subject matter of any of Examples 1-8, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein to migrate the hardware threads to the second compute element in response to having detected the phase change comprises to migrate the hardware threads to a low-performance CPU of another compute sled of the plurality of compute sleds.
Example 10 includes the subject matter of any of Examples 1-9, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein to migrate the hardware threads to the second compute element in response to having detected the phase change comprises to migrate the hardware threads to a low-performance CPU of the accelerator sled.
Example 11 includes the subject matter of any of Examples 1-10, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein to migrate the hardware threads to the second compute element in response to having detected the phase change comprises to migrate the hardware threads to a low-performance CPU of another accelerator sled of the plurality of accelerator sleds.
Example 12 includes the subject matter of any of Examples 1-11, and wherein to migrate the hardware threads to the second compute element comprises to pause the hardware threads at the first compute element, migrate states of the hardware threads from the first compute element to the second compute element, resume the migrated hardware threads at the second compute element, and offline the first compute element.
Example 13 includes the subject matter of any of Examples 1-12, and wherein the compute engine is further to migrate the compute kernel to another FPGA of another accelerator sled of the plurality of accelerator sleds.
Example 14 includes the subject matter of any of Examples 1-13, and wherein the compute engine is further to receive an indication that indicates the compute kernel has completed; and migrate, in response to having received the indication, the application to a third compute element.
Example 15 includes the subject matter of any of Examples 1-14, and wherein to migrate the application to the third compute element comprises to migrate the application to a high-performance CPU of one of the plurality of compute sleds.
Example 16 includes the subject matter of any of Examples 1-15, and wherein to migrate the hardware threads to the third compute element comprises to pause the hardware threads at the second compute element, migrate states of the hardware threads from the second compute element to the third compute element, resume the migrated hardware threads at the third compute element, and offline the second compute element.
Example 17 includes a method for auto-migration in accelerated architectures, the method comprising receiving, by a compute sled, from an application executed on a first compute element of a compute sled of a plurality of compute sleds, an indication that a compute kernel associated with the application has been offloaded to a field-programmable gate array (FPGA) of an accelerator sled of a plurality of accelerator sleds, wherein each of the plurality of accelerator sleds and the plurality of compute sleds are communicatively coupled to the compute sled; monitoring, by the compute sled, a plurality of hardware threads associated with the application; detecting, by the compute sled, whether a phase change has been detected as a function of the monitored hardware threads; and migrating, by the compute sled and in response to detected detection of the phase change, the hardware threads to a second compute element.
Example 18 includes the subject matter of Example 17, and wherein monitoring the plurality of hardware threads comprises collecting telemetry data corresponding to one or more hardware resources used by the hardware threads during execution.
Example 19 includes the subject matter of any of Examples 17 and 18, and wherein collecting the telemetry data includes collecting an instructions per cycle (IPC) value of the first compute element.
Example 20 includes the subject matter of any of Examples 17-19, and wherein detecting whether the phase change has been detected comprises comparing the IPC value of the first compute element to a peak IPC threshold value.
Example 21 includes the subject matter of any of Examples 17-20, and wherein detecting whether the phase change has been detected comprises identifying a previous phase as a central processing unit (CPU) bound phase and identify a present phase as an FPGA bound phase.
Example 22 includes the subject matter of any of Examples 17-21, and wherein detecting whether the phase change has been detected comprises identifying a previous phase as a central processing unit (CPU) bound phase and identify a present phase as a memory bound phase.
Example 23 includes the subject matter of any of Examples 17-22, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein migrating the hardware threads to the second compute element in response to having detected the phase change comprises migrating the hardware threads to another high-performance CPU of the compute sled.
Example 24 includes the subject matter of any of Examples 17-23, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein migrating the hardware threads to the second compute element in response to having detected the phase change comprises migrating the hardware threads to a high-performance CPU of another compute sled of the plurality of compute sleds.
Example 25 includes the subject matter of any of Examples 17-24, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein migrating the hardware threads to the second compute element in response to having detected the phase change comprises migrating the hardware threads to a low-performance CPU of another compute sled of the plurality of compute sleds.
Example 26 includes the subject matter of any of Examples 17-25, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein migrating the hardware threads to the second compute element in response to having detected the phase change comprises migrating the hardware threads to a low-performance CPU of the accelerator sled.
Example 27 includes the subject matter of any of Examples 17-26, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein migrating the hardware threads to the second compute element in response to having detected the phase change comprises migrating the hardware threads to a low-performance CPU of another accelerator sled of the plurality of accelerator sleds.
Example 28 includes the subject matter of any of Examples 17-27, and wherein migrating the hardware threads to the second compute element comprises pausing the hardware threads at the first compute element; migrating states of the hardware threads from the first compute element to the second compute element; resuming the migrated hardware threads at the second compute element; and offlining the first compute element.
Example 29 includes the subject matter of any of Examples 17-28, and further including migrating, by the compute sled, the compute kernel to another FPGA of another accelerator sled of the plurality of accelerator sleds.
Example 30 includes the subject matter of any of Examples 17-29, and further including receiving, by the compute sled, an indication that indicates the compute kernel has completed; and migrating, by the compute sled and in response to having received the indication, the application to a third compute element.
Example 31 includes the subject matter of any of Examples 17-30, and wherein migrating the application to the third compute element comprises migrating the application to a high-performance CPU of one of the plurality of compute sleds.
Example 32 includes the subject matter of any of Examples 17-31, and wherein migrating the hardware threads to the third compute element comprises pausing the hardware threads at the second compute element; migrating states of the hardware threads from the second compute element to the third compute element; resuming the migrated hardware threads at the third compute element; and offlining the second compute element.
Example 33 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute sled to perform the method of any of Examples 17-32.
Example 34 includes a compute sled for improving throughput in a network, the compute sled comprising one or more processors; one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the compute sled to perform the method of any of Examples 17-32.
Example 35 includes a compute sled for auto-migration in accelerated architectures, the compute sled comprising phase detection logic circuitry to receive, from an application executed on a first compute element of a compute sled of a plurality of compute sleds, an indication that a compute kernel associated with the application has been offloaded to a field-programmable gate array (FPGA) of an accelerator sled of a plurality of accelerator sleds, wherein each of the plurality of accelerator sleds and the plurality of compute sleds are communicatively coupled to the compute sled; monitor a plurality of hardware threads associated with the application; detect whether a phase change has been detected as a function of the monitored hardware threads; and migrate, in response to detected detection of the phase change, the hardware threads to a second compute element.
Example 36 includes the subject matter of Example 35, and wherein to monitor the plurality of hardware threads comprises to collect telemetry data corresponding to one or more hardware resources used by the hardware threads during execution.
Example 37 includes the subject matter of any of Examples 35 and 36, and wherein to collect the telemetry data includes to collect an instructions per cycle (IPC) value of the first compute element.
Example 38 includes the subject matter of any of Examples 35-37, and wherein to detect whether the phase change has been detected comprises to compare the IPC value of the first compute element to a peak IPC threshold value.
Example 39 includes the subject matter of any of Examples 35-38, and wherein to detect whether the phase change has been detected comprises to identify a previous phase as a central processing unit (CPU) bound phase and identify a present phase as an FPGA bound phase.
Example 40 includes the subject matter of any of Examples 35-39, and wherein to detect whether the phase change has been detected comprises to identify a previous phase as a central processing unit (CPU) bound phase and identify a present phase as a memory bound phase.
Example 41 includes the subject matter of any of Examples 35-40, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein to migrate the hardware threads to the second compute element in response to having detected the phase change comprises to migrate the hardware threads to another high-performance CPU of the compute sled.
Example 42 includes the subject matter of any of Examples 35-41, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein to migrate the hardware threads to the second compute element in response to having detected the phase change comprises to migrate the hardware threads to a high-performance CPU of another compute sled of the plurality of compute sleds.
Example 43 includes the subject matter of any of Examples 35-42, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein to migrate the hardware threads to the second compute element in response to having detected the phase change comprises to migrate the hardware threads to a low-performance CPU of another compute sled of the plurality of compute sleds.
Example 44 includes the subject matter of any of Examples 35-43, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein to migrate the hardware threads to the second compute element in response to having detected the phase change comprises to migrate the hardware threads to a low-performance CPU of the accelerator sled.
Example 45 includes the subject matter of any of Examples 35-44, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein to migrate the hardware threads to the second compute element in response to having detected the phase change comprises to migrate the hardware threads to a low-performance CPU of another accelerator sled of the plurality of accelerator sleds.
Example 46 includes the subject matter of any of Examples 35-45, and wherein to migrate the hardware threads to the second compute element comprises to pause the hardware threads at the first compute element, migrate states of the hardware threads from the first compute element to the second compute element, resume the migrated hardware threads at the second compute element, and offline the first compute element.
Example 47 includes the subject matter of any of Examples 35-46, and wherein the phase detection logic circuitry is further to migrate the compute kernel to another FPGA of another accelerator sled of the plurality of accelerator sleds.
Example 48 includes the subject matter of any of Examples 35-47, and wherein the compute engine is further to receive an indication that indicates the compute kernel has completed; and migrate, in response to having received the indication, the application to a third compute element.
Example 49 includes the subject matter of any of Examples 35-48, and wherein to migrate the application to the third compute element comprises to migrate the application to a high-performance CPU of one of the plurality of compute sleds.
Example 50 includes the subject matter of any of Examples 35-49, and wherein to migrate the hardware threads to the third compute element comprises to pause the hardware threads at the second compute element, migrate states of the hardware threads from the second compute element to the third compute element, resume the migrated hardware threads at the third compute element, and offline the second compute element.
Example 35 includes a compute sled for auto-migration in accelerated architectures, the compute sled comprising circuitry for receiving, from an application executed on a first compute element of a compute sled of a plurality of compute sleds, an indication that a compute kernel associated with the application has been offloaded to a field-programmable gate array (FPGA) of an accelerator sled of a plurality of accelerator sleds, wherein each of the plurality of accelerator sleds and the plurality of compute sleds are communicatively coupled to the compute sled; means for monitoring a plurality of hardware threads associated with the application; means for detecting whether a phase change has been detected as a function of the monitored hardware threads; and circuitry for migrating, in response to detected detection of the phase change, the hardware threads to a second compute element.
Example 36 includes the subject matter of Example 35, and wherein the means for monitoring the plurality of hardware threads comprises means for collecting telemetry data corresponding to one or more hardware resources used by the hardware threads during execution.
Example 37 includes the subject matter of any of Examples 35 and 36, and wherein the means for collecting the telemetry data includes means for collecting an instructions per cycle (IPC) value of the first compute element.
Example 38 includes the subject matter of any of Examples 35-37, and wherein the means for detecting whether the phase change has been detected comprises means for comparing the IPC value of the first compute element to a peak IPC threshold value.
Example 39 includes the subject matter of any of Examples 35-38, and wherein the means for detecting whether the phase change has been detected comprises means for identifying a previous phase as a central processing unit (CPU) bound phase and identify a present phase as an FPGA bound phase.
Example 40 includes the subject matter of any of Examples 35-39, and wherein the means for detecting whether the phase change has been detected comprises means for identifying a previous phase as a central processing unit (CPU) bound phase and identify a present phase as a memory bound phase.
Example 41 includes the subject matter of any of Examples 35-40, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein migrating the hardware threads to the second compute element in response to having detected the phase change comprises migrating the hardware threads to another high-performance CPU of the compute sled.
Example 42 includes the subject matter of any of Examples 35-41, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein migrating the hardware threads to the second compute element in response to having detected the phase change comprises migrating the hardware threads to a high-performance CPU of another compute sled of the plurality of compute sleds.
Example 43 includes the subject matter of any of Examples 35-42, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein migrating the hardware threads to the second compute element in response to having detected the phase change comprises migrating the hardware threads to a low-performance CPU of another compute sled of the plurality of compute sleds.
Example 44 includes the subject matter of any of Examples 35-43, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein migrating the hardware threads to the second compute element in response to having detected the phase change comprises migrating the hardware threads to a low-performance CPU of the accelerator sled.
Example 45 includes the subject matter of any of Examples 35-44, and wherein the first compute element on which the application is presently executing comprises a high-performance central processing unit (CPU), and wherein migrating the hardware threads to the second compute element in response to having detected the phase change comprises migrating the hardware threads to a low-performance CPU of another accelerator sled of the plurality of accelerator sleds.
Example 46 includes the subject matter of any of Examples 35-45, and wherein the circuitry for migrating the hardware threads to the second compute element comprises circuitry for pausing the hardware threads at the first compute element; circuitry for migrating states of the hardware threads from the first compute element to the second compute element; circuitry for resuming the migrated hardware threads at the second compute element; and circuitry for offlining the first compute element.
Example 47 includes the subject matter of any of Examples 35-46, and further including circuitry for migrating, by the compute sled, the compute kernel to another FPGA of another accelerator sled of the plurality of accelerator sleds.
Example 48 includes the subject matter of any of Examples 35-47, and further including circuitry for receiving, by the compute sled, an indication that indicates the compute kernel has completed; and circuitry for migrating, by the compute sled and in response to having received the indication, the application to a third compute element.
Example 49 includes the subject matter of any of Examples 35-48, and wherein the circuitry for migrating the application to the third compute element comprises circuitry for migrating the application to a high-performance CPU of one of the plurality of compute sleds.
Example 50 includes the subject matter of any of Examples 35-49, and wherein the circuitry for migrating the hardware threads to the third compute element comprises circuitry for pausing the hardware threads at the second compute element; circuitry for migrating states of the hardware threads from the second compute element to the third compute element; circuitry for resuming the migrated hardware threads at the third compute element; and circuitry for offlining the second compute element.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201741030632 | Aug 2017 | IN | national |
The present application claims the benefit of Indian Provisional Patent Application No. 201741030632, filed Aug. 30, 2017 and U.S. Provisional Patent Application No. 62/584,401, filed Nov. 10, 2017.
| Number | Date | Country | |
|---|---|---|---|
| 62584401 | Nov 2017 | US |
