TECHNOLOGIES FOR MANAGING DISAGGREGATED RESOURCES IN A DATA CENTER

BACKGROUND

Large data centers that execute workloads (e.g., services, applications, processes, sets of operations, etc.) on behalf of one or more clients (e.g., customers, tenants, etc.) typically contain racks of compute devices to execute the various workloads. Data centers are evolving towards a disaggregated architecture where storage media can be shared, so as to address issues of underutilization of capacity and/or throughput of storage devices in datacenters due to imbalanced requirements across applications and over time. Each compute device may have multiple components located in various positions on the compute device that perform different functions (e.g., memory to access data, compute components to execute operations, etc.) and each data center may include thousands to tens-of-thousands of such compute devices. As such, scaling the management control plane generally requires the inclusion of additional switching mechanisms, such as a spine switch in data centers which employ top-of-rack switches.

Oftentimes, client workloads are executed in virtualized or containerized clouds (e.g., using Openstack). Accordingly, the composition of client networks, teardown of spawning racks, flow management, and routing across resources is required. Generally, such control plane management requires packet telemetry gathering and analysis at scale, in addition to management of the hardware switches with actions that influence the client virtual networks. For example, spawning a storage volume of disaggregated distributed disks, or disaggregated pooled field programmable gate arrays (FPGAs) for machine learning or deep learning deployments (e.g., using the Theano library, the Caffe deep learning framework, etc.) orchestrated as high-performance computing (HPC) workloads requires a scalable management solution that takes into account the disaggregated nature of the hardware resources of the data center.

BRIEF DESCRIPTION OF THE DRAWINGS

The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

FIG. 1 is a simplified diagram of at least one embodiment of a data center for executing workloads with disaggregated resources;

FIG. 2 is a simplified diagram of at least one embodiment of a pod that may be included in the data center of FIG. 1;

FIG. 3 is a perspective view of at least one embodiment of a rack that may be included in the pod of FIG. 2;

FIG. 4 is a side elevation view of the rack of FIG. 3;

FIG. 5 is a perspective view of the rack of FIG. 3 having a sled mounted therein;

FIG. 6 is a is a simplified block diagram of at least one embodiment of a top side of the sled of FIG. 5;

FIG. 7 is a simplified block diagram of at least one embodiment of a bottom side of the sled of FIG. 6;

FIG. 8 is a simplified block diagram of at least one embodiment of a compute sled usable in the data center of FIG. 1;

FIG. 9 is a top perspective view of at least one embodiment of the compute sled of FIG. 8;

FIG. 10 is a simplified block diagram of at least one embodiment of an accelerator sled usable in the data center of FIG. 1;

FIG. 11 is a top perspective view of at least one embodiment of the accelerator sled of FIG. 10;

FIG. 12 is a simplified block diagram of at least one embodiment of a storage sled usable in the data center of FIG. 1;

FIG. 13 is a top perspective view of at least one embodiment of the storage sled of FIG. 12;

FIG. 14 is a simplified block diagram of at least one embodiment of a memory sled usable in the data center of FIG. 1;

FIG. 15 is a simplified block diagram of a system that may be established within the data center of FIG. 1 to execute workloads with managed nodes composed of disaggregated resources;

FIG. 16 is a simplified diagram of at least one embodiment of a system for managing disaggregated resources in a data center that includes a controller compute device;

FIG. 17 is a simplified block diagram of at least one embodiment of the controller compute device of the system of FIG. 16;

FIG. 18 is a simplified block diagram of at least one embodiment of a method for managing disaggregated resources in a data center that may be performed by the controller compute device of FIGS. 16 and 17;

FIG. 19 is a simplified block diagram of at least one embodiment of a communication data flow for performing a hardware lifecycle management operation that may be performed by the controller compute device of FIGS. 16 and 17;

FIG. 20 is a simplified block diagram of at least one embodiment of a communication data flow for scheduling and managing groups of nodes that may be performed by the controller compute device of FIGS. 16 and 17;

FIG. 21 is a simplified block diagram of at least one embodiment of a communication data flow for managing an underlay network that may be performed by the controller compute device of FIGS. 16 and 17; and

FIG. 22 is a simplified block diagram of at least one embodiment of a communication data flow for allocating a network slice that may be performed by the controller compute device of FIGS. 16 and 17.

DETAILED DESCRIPTION OF THE DRAWINGS

While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.

References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).

In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.

Referring now to FIG. 1, a data center 100 (e.g., a facility used to house computer systems and associated components, such as telecommunications and storage systems) in which disaggregated resources may cooperatively execute one or more workloads (e.g., applications on behalf of customers) includes multiple pods 110, 120, 130, 140, each of which includes one or more rows of racks. Of course, although data center 100 is shown with multiple pods, in some embodiments, the data center 100 may be embodied as a single pod. PODs by one definition are a group of racks. As described in more detail herein, each rack houses multiple sleds, each of which may be primarily equipped with a particular type of resource (e.g., memory devices, data storage devices, accelerator devices, general purpose processors), i.e., resources that can be logically coupled to form a composed node, which can act as, for example, a server.

In the illustrative embodiment, the sleds in each pod 110, 120, 130, 140 are connected to multiple pod switches (e.g., switches that route data communications to and from sleds within the pod). The pod switches, in turn, connect with spine switches 150 that switch communications among pods (e.g., the pods 110, 120, 130, 140) in the data center 100. In some embodiments, the sleds may be connected with a fabric using Intel® Omni-Path technology. In other embodiments, the sleds may be connected with other fabrics, such as InfiniBand or Ethernet. As described in more detail herein, resources within sleds in the data center 100 may be allocated to a group (referred to herein as a “managed node”) containing resources from one or more sleds to be collectively utilized in the execution of a workload. The workload can execute as if the resources belonging to the managed node were located on the same sled. The resources in a managed node may belong to sleds belonging to different racks, and even to different pods 110, 120, 130, 140. As such, some resources of a single sled may be allocated to one managed node while other resources of the same sled are allocated to a different managed node (e.g., one processor assigned to one managed node and another processor of the same sled assigned to a different managed node).

A data center comprising disaggregated resources, such as data center 100, can be used in a wide variety of contexts, such as enterprise, government, cloud service provider, and communications service provider (e.g., Telco's), as well in a wide variety of sizes, from cloud service provider mega-data centers that consume over 100,000 sq. ft. to single- or multi-rack installations for use in base stations.

The disaggregation of resources to sleds comprised predominantly of a single type of resource (e.g., compute sleds comprising primarily compute resources, memory sleds containing primarily memory resources), and the selective allocation and deallocation of the disaggregated resources to form a managed node assigned to execute a workload improves the operation and resource usage of the data center 100 relative to typical data centers comprised of hyperconverged servers containing compute, memory, storage and perhaps additional resources in a single chassis. For example, because sleds predominantly contain resources of a particular type, resources of a given type can be upgraded independently of other resources. Additionally, because different resources types (processors, storage, accelerators, etc.) typically have different refresh rates, greater resource utilization and reduced total cost of ownership may be achieved. For example, a data center operator can upgrade the processors throughout their facility by only swapping out the compute sleds. In such a case, accelerator and storage resources may not be contemporaneously upgraded and, rather, may be allowed to continue operating until those resources are scheduled for their own refresh. Resource utilization may also increase. For example, if managed nodes are composed (e.g., resources collectively combined to provide certain functionality) based on requirements of the workloads that will be running on them, resources within a node are more likely to be fully utilized. Such utilization may allow for more managed nodes to run in a data center with a given set of resources, or for a data center expected to run a given set of workloads, to be built using fewer resources.

Referring now to FIG. 2, the pod 110, in the illustrative embodiment, includes a set of rows 200, 210, 220, 230 of racks 240. Each rack 240 may house multiple sleds (e.g., sixteen sleds) and provide power and data connections to the housed sleds, as described in more detail herein. In the illustrative embodiment, the racks in each row 200, 210, 220, 230 are connected to multiple pod switches 250, 260. The pod switch 250 includes a set of ports 252 to which the sleds of the racks of the pod 110 are connected and another set of ports 254 that connect the pod 110 to the spine switches 150 to provide connectivity to other pods in the data center 100. Similarly, the pod switch 260 includes a set of ports 262 to which the sleds of the racks of the pod 110 are connected and a set of ports 264 that connect the pod 110 to the spine switches 150. As such, the use of the pair of switches 250, 260 provides an amount of redundancy to the pod 110. For example, if either of the switches 250, 260 fails, the sleds in the pod 110 may still maintain data communication with the remainder of the data center 100 (e.g., sleds of other pods) through the other switch 250, 260. Furthermore, in the illustrative embodiment, the switches 150, 250, 260 may be embodied as dual-mode optical switches, capable of routing both Ethernet protocol communications carrying Internet Protocol (IP) packets and communications according to a second, high-performance link-layer protocol (e.g., Intel's Omni-Path Architecture's, InfiniBand, PCI Express) via optical signaling media of an optical fabric.

It should be appreciated that each of the other pods 120, 130, 140 (as well as any additional pods of the data center 100) may be similarly structured as, and have components similar to, the pod 110 shown in and described in regard to FIG. 2 (e.g., each pod may have rows of racks housing multiple sleds as described above). Additionally, while two pod switches 250, 260 are shown, it should be understood that in other embodiments, each pod 110, 120, 130, 140 may be connected to a different number of pod switches, providing even more failover capacity. Of course, in other embodiments, pods may be arranged differently than the rows-of-racks configuration shown in FIGS. 1-2. For example, a pod may be embodied as multiple sets of racks in which each set of racks is arranged radially, i.e., the racks are equidistant from a center switch.

Referring now to FIGS. 3-5, each illustrative rack 240 of the data center 100 includes two elongated support posts 302, 304, which are arranged vertically. For example, the elongated support posts 302, 304 may extend upwardly from a floor of the data center 100 when deployed. The rack 240 also includes one or more horizontal pairs 310 of elongated support arms 312 (identified in FIG. 3 via a dashed ellipse) configured to support a sled of the data center 100 as discussed below. One elongated support arm 312 of the pair of elongated support arms 312 extends outwardly from the elongated support post 302 and the other elongated support arm 312 extends outwardly from the elongated support post 304.

In the illustrative embodiments, each sled of the data center 100 is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, the rack 240 is configured to receive the chassis-less sleds. For example, each pair 310 of elongated support arms 312 defines a sled slot 320 of the rack 240, which is configured to receive a corresponding chassis-less sled. To do so, each illustrative elongated support arm 312 includes a circuit board guide 330 configured to receive the chassis-less circuit board substrate of the sled. Each circuit board guide 330 is secured to, or otherwise mounted to, a top side 332 of the corresponding elongated support arm 312. For example, in the illustrative embodiment, each circuit board guide 330 is mounted at a distal end of the corresponding elongated support arm 312 relative to the corresponding elongated support post 302, 304. For clarity of the Figures, not every circuit board guide 330 may be referenced in each Figure.

Each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 configured to receive the chassis-less circuit board substrate of a sled 400 when the sled 400 is received in the corresponding sled slot 320 of the rack 240. To do so, as shown in FIG. 4, a user (or robot) aligns the chassis-less circuit board substrate of an illustrative chassis-less sled 400 to a sled slot 320. The user, or robot, may then slide the chassis-less circuit board substrate forward into the sled slot 320 such that each side edge 414 of the chassis-less circuit board substrate is received in a corresponding circuit board slot 380 of the circuit board guides 330 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320 as shown in FIG. 4. By having robotically accessible and robotically manipulable sleds comprising disaggregated resources, each type of resource can be upgraded independently of each other and at their own optimized refresh rate. Furthermore, the sleds are configured to blindly mate with power and data communication cables in each rack 240, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. As such, in some embodiments, the data center 100 may operate (e.g., execute workloads, undergo maintenance and/or upgrades, etc.) without human involvement on the data center floor. In other embodiments, a human may facilitate one or more maintenance or upgrade operations in the data center 100.

It should be appreciated that each circuit board guide 330 is dual sided. That is, each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 on each side of the circuit board guide 330. In this way, each circuit board guide 330 can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to the rack 240 to turn the rack 240 into a two-rack solution that can hold twice as many sled slots 320 as shown in FIG. 3. The illustrative rack 240 includes seven pairs 310 of elongated support arms 312 that define a corresponding seven sled slots 320, each configured to receive and support a corresponding sled 400 as discussed above. Of course, in other embodiments, the rack 240 may include additional or fewer pairs 310 of elongated support arms 312 (i.e., additional or fewer sled slots 320). It should be appreciated that because the sled 400 is chassis-less, the sled 400 may have an overall height that is different than typical servers. As such, in some embodiments, the height of each sled slot 320 may be shorter than the height of a typical server (e.g., shorter than a single rank unit, “1 U”). That is, the vertical distance between each pair 310 of elongated support arms 312 may be less than a standard rack unit “1 U.” Additionally, due to the relative decrease in height of the sled slots 320, the overall height of the rack 240 in some embodiments may be shorter than the height of traditional rack enclosures. For example, in some embodiments, each of the elongated support posts 302, 304 may have a length of six feet or less. Again, in other embodiments, the rack 240 may have different dimensions. For example, in some embodiments, the vertical distance between each pair 310 of elongated support arms 312 may be greater than a standard rack until “1 U”. In such embodiments, the increased vertical distance between the sleds allows for larger heat sinks to be attached to the physical resources and for larger fans to be used (e.g., in the fan array 370 described below) for cooling each sled, which in turn can allow the physical resources to operate at increased power levels. Further, it should be appreciated that the rack 240 does not include any walls, enclosures, or the like. Rather, the rack 240 is an enclosure-less rack that is opened to the local environment. Of course, in some cases, an end plate may be attached to one of the elongated support posts 302, 304 in those situations in which the rack 240 forms an end-of-row rack in the data center 100.

In some embodiments, various interconnects may be routed upwardly or downwardly through the elongated support posts 302, 304. To facilitate such routing, each elongated support post 302, 304 includes an inner wall that defines an inner chamber in which interconnects may be located. The interconnects routed through the elongated support posts 302, 304 may be embodied as any type of interconnects including, but not limited to, data or communication interconnects to provide communication connections to each sled slot 320, power interconnects to provide power to each sled slot 320, and/or other types of interconnects.

The rack 240, in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with a corresponding sled slot 320 and is configured to mate with an optical data connector of a corresponding sled 400 when the sled 400 is received in the corresponding sled slot 320. In some embodiments, optical connections between components (e.g., sleds, racks, and switches) in the data center 100 are made with a blind mate optical connection. For example, a door on each cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable approaches or enters the connector mechanism. Subsequently, the optical fiber inside the cable may enter a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism.

The illustrative rack 240 also includes a fan array 370 coupled to the cross-support arms of the rack 240. The fan array 370 includes one or more rows of cooling fans 372, which are aligned in a horizontal line between the elongated support posts 302, 304. In the illustrative embodiment, the fan array 370 includes a row of cooling fans 372 for each sled slot 320 of the rack 240. As discussed above, each sled 400 does not include any on-board cooling system in the illustrative embodiment and, as such, the fan array 370 provides cooling for each sled 400 received in the rack 240. Each rack 240, in the illustrative embodiment, also includes a power supply associated with each sled slot 320. Each power supply is secured to one of the elongated support arms 312 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320. For example, the rack 240 may include a power supply coupled or secured to each elongated support arm 312 extending from the elongated support post 302. Each power supply includes a power connector configured to mate with a power connector of the sled 400 when the sled 400 is received in the corresponding sled slot 320. In the illustrative embodiment, the sled 400 does not include any on-board power supply and, as such, the power supplies provided in the rack 240 supply power to corresponding sleds 400 when mounted to the rack 240. Each power supply is configured to satisfy the power requirements for its associated sled, which can vary from sled to sled. Additionally, the power supplies provided in the rack 240 can operate independent of each other. That is, within a single rack, a first power supply providing power to a compute sled can provide power levels that are different than power levels supplied by a second power supply providing power to an accelerator sled. The power supplies may be controllable at the sled level or rack level, and may be controlled locally by components on the associated sled or remotely, such as by another sled or an orchestrator.

Referring now to FIG. 6, the sled 400, in the illustrative embodiment, is configured to be mounted in a corresponding rack 240 of the data center 100 as discussed above. In some embodiments, each sled 400 may be optimized or otherwise configured for performing particular tasks, such as compute tasks, acceleration tasks, data storage tasks, etc. For example, the sled 400 may be embodied as a compute sled 800 as discussed below in regard to FIGS. 8-9, an accelerator sled 1000 as discussed below in regard to FIGS. 10-11, a storage sled 1200 as discussed below in regard to FIGS. 12-13, or as a sled optimized or otherwise configured to perform other specialized tasks, such as a memory sled 1400, discussed below in regard to FIG. 14.

As discussed above, the illustrative sled 400 includes a chassis-less circuit board substrate 602, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that the circuit board substrate 602 is “chassis-less” in that the sled 400 does not include a housing or enclosure. Rather, the chassis-less circuit board substrate 602 is open to the local environment. The chassis-less circuit board substrate 602 may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, the chassis-less circuit board substrate 602 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-less circuit board substrate 602 in other embodiments.

As discussed in more detail below, the chassis-less circuit board substrate 602 includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602. As discussed, the chassis-less circuit board substrate 602 does not include a housing or enclosure, which may improve the airflow over the electrical components of the sled 400 by reducing those structures that may inhibit air flow. For example, because the chassis-less circuit board substrate 602 is not positioned in an individual housing or enclosure, there is no vertically-arranged backplane (e.g., a backplate of the chassis) attached to the chassis-less circuit board substrate 602, which could inhibit air flow across the electrical components. Additionally, the chassis-less circuit board substrate 602 has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-less circuit board substrate 602. For example, the illustrative chassis-less circuit board substrate 602 has a width 604 that is greater than a depth 606 of the chassis-less circuit board substrate 602. In one particular embodiment, for example, the chassis-less circuit board substrate 602 has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, an airflow path 608 that extends from a front edge 610 of the chassis-less circuit board substrate 602 toward a rear edge 612 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of the sled 400. Furthermore, although not illustrated in FIG. 6, the various physical resources mounted to the chassis-less circuit board substrate 602 are mounted in corresponding locations such that no two substantively heat-producing electrical components shadow each other as discussed in more detail below. That is, no two electrical components, which produce appreciable heat during operation (i.e., greater than a nominal heat sufficient enough to adversely impact the cooling of another electrical component), are mounted to the chassis-less circuit board substrate 602 linearly in-line with each other along the direction of the airflow path 608 (i.e., along a direction extending from the front edge 610 toward the rear edge 612 of the chassis-less circuit board substrate 602).

As discussed above, the illustrative sled 400 includes one or more physical resources 620 mounted to a top side 650 of the chassis-less circuit board substrate 602. Although two physical resources 620 are shown in FIG. 6, it should be appreciated that the sled 400 may include one, two, or more physical resources 620 in other embodiments. The physical resources 620 may be embodied as any type of processor, controller, or other compute circuit capable of performing various tasks such as compute functions and/or controlling the functions of the sled 400 depending on, for example, the type or intended functionality of the sled 400. For example, as discussed in more detail below, the physical resources 620 may be embodied as high-performance processors in embodiments in which the sled 400 is embodied as a compute sled, as accelerator co-processors or circuits in embodiments in which the sled 400 is embodied as an accelerator sled, storage controllers in embodiments in which the sled 400 is embodied as a storage sled, or a set of memory devices in embodiments in which the sled 400 is embodied as a memory sled.

The sled 400 also includes one or more additional physical resources 630 mounted to the top side 650 of the chassis-less circuit board substrate 602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of the sled 400, the physical resources 630 may include additional or other electrical components, circuits, and/or devices in other embodiments.

The physical resources 620 are communicatively coupled to the physical resources 630 via an input/output (I/O) subsystem 622. The I/O subsystem 622 may be embodied as circuitry and/or components to facilitate input/output operations with the physical resources 620, the physical resources 630, and/or other components of the sled 400. For example, the I/O subsystem 622 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, waveguides, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative embodiment, the I/O subsystem 622 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDR5 data bus.

In some embodiments, the sled 400 may also include a resource-to-resource interconnect 624. The resource-to-resource interconnect 624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect 624 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the resource-to-resource interconnect 624 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.

The sled 400 also includes a power connector 640 configured to mate with a corresponding power connector of the rack 240 when the sled 400 is mounted in the corresponding rack 240. The sled 400 receives power from a power supply of the rack 240 via the power connector 640 to supply power to the various electrical components of the sled 400. That is, the sled 400 does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of the sled 400. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-less circuit board substrate 602, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602 as discussed above. In some embodiments, voltage regulators are placed on a bottom side 750 (see FIG. 7) of the chassis-less circuit board substrate 602 directly opposite of the processors 820 (see FIG. 8), and power is routed from the voltage regulators to the processors 820 by vias extending through the circuit board substrate 602. Such a configuration provides an increased thermal budget, additional current and/or voltage, and better voltage control relative to typical printed circuit boards in which processor power is delivered from a voltage regulator, in part, by printed circuit traces.

In some embodiments, the sled 400 may also include mounting features 642 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled 600 in a rack 240 by the robot. The mounting features 642 may be embodied as any type of physical structures that allow the robot to grasp the sled 400 without damaging the chassis-less circuit board substrate 602 or the electrical components mounted thereto. For example, in some embodiments, the mounting features 642 may be embodied as non-conductive pads attached to the chassis-less circuit board substrate 602. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-less circuit board substrate 602. The particular number, shape, size, and/or make-up of the mounting feature 642 may depend on the design of the robot configured to manage the sled 400.

Referring now to FIG. 7, in addition to the physical resources 630 mounted on the top side 650 of the chassis-less circuit board substrate 602, the sled 400 also includes one or more memory devices 720 mounted to a bottom side 750 of the chassis-less circuit board substrate 602. That is, the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board. The physical resources 620 are communicatively coupled to the memory devices 720 via the I/O subsystem 622. For example, the physical resources 620 and the memory devices 720 may be communicatively coupled by one or more vias extending through the chassis-less circuit board substrate 602. Each physical resource 620 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments. Alternatively, in other embodiments, each physical resource 620 may be communicatively coupled to each memory device 720.

The memory devices 720 may be embodied as any type of memory device capable of storing data for the physical resources 620 during operation of the sled 400, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4. Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.

In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include next-generation nonvolatile devices, such as Intel 3D XPoint™ memory or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.

Referring now to FIG. 8, in some embodiments, the sled 400 may be embodied as a compute sled 800. The compute sled 800 is optimized, or otherwise configured, to perform compute tasks. Of course, as discussed above, the compute sled 800 may rely on other sleds, such as acceleration sleds and/or storage sleds, to perform such compute tasks. The compute sled 800 includes various physical resources (e.g., electrical components) similar to the physical resources of the sled 400, which have been identified in FIG. 8 using the same reference numbers. The description of such components provided above in regard to FIGS. 6 and 7 applies to the corresponding components of the compute sled 800 and is not repeated herein for clarity of the description of the compute sled 800.

In the illustrative compute sled 800, the physical resources 620 are embodied as processors 820. Although only two processors 820 are shown in FIG. 8, it should be appreciated that the compute sled 800 may include additional processors 820 in other embodiments. Illustratively, the processors 820 are embodied as high-performance processors 820 and may be configured to operate at a relatively high power rating. Although the processors 820 generate additional heat operating at power ratings greater than typical processors (which operate at around 155-230 W), the enhanced thermal cooling characteristics of the chassis-less circuit board substrate 602 discussed above facilitate the higher power operation. For example, in the illustrative embodiment, the processors 820 are configured to operate at a power rating of at least 250 W. In some embodiments, the processors 820 may be configured to operate at a power rating of at least 350 W.

In some embodiments, the compute sled 800 may also include a processor-to-processor interconnect 842. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the processor-to-processor interconnect 842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 842 communications. In the illustrative embodiment, the processor-to-processor interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the processor-to-processor interconnect 842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.

The compute sled 800 also includes a communication circuit 830. The illustrative communication circuit 830 includes a network interface controller (NIC) 832, which may also be referred to as a host fabric interface (HFI). The NIC 832 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, or other devices that may be used by the compute sled 800 to connect with another compute device (e.g., with other sleds 400). In some embodiments, the NIC 832 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 832 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 832. In such embodiments, the local processor of the NIC 832 may be capable of performing one or more of the functions of the processors 820. Additionally or alternatively, in such embodiments, the local memory of the NIC 832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels.

The communication circuit 830 is communicatively coupled to an optical data connector 834. The optical data connector 834 is configured to mate with a corresponding optical data connector of the rack 240 when the compute sled 800 is mounted in the rack 240. Illustratively, the optical data connector 834 includes a plurality of optical fibers which lead from a mating surface of the optical data connector 834 to an optical transceiver 836. The optical transceiver 836 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of the optical data connector 834 in the illustrative embodiment, the optical transceiver 836 may form a portion of the communication circuit 830 in other embodiments.

In some embodiments, the compute sled 800 may also include an expansion connector 840. In such embodiments, the expansion connector 840 is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to the compute sled 800. The additional physical resources may be used, for example, by the processors 820 during operation of the compute sled 800. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-less circuit board substrate 602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.

Referring now to FIG. 9, an illustrative embodiment of the compute sled 800 is shown. As shown, the processors 820, communication circuit 830, and optical data connector 834 are mounted to the top side 650 of the chassis-less circuit board substrate 602. Any suitable attachment or mounting technology may be used to mount the physical resources of the compute sled 800 to the chassis-less circuit board substrate 602. For example, the various physical resources may be mounted in corresponding sockets (e.g., a processor socket), holders, or brackets. In some cases, some of the electrical components may be directly mounted to the chassis-less circuit board substrate 602 via soldering or similar techniques.

As discussed above, the individual processors 820 and communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. In the illustrative embodiment, the processors 820 and communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those physical resources are linearly in-line with others along the direction of the airflow path 608. It should be appreciated that, although the optical data connector 834 is in-line with the communication circuit 830, the optical data connector 834 produces no or nominal heat during operation.

The memory devices 720 of the compute sled 800 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the processors 820 located on the top side 650 via the I/O subsystem 622. Because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the processors 820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Of course, each processor 820 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments. Alternatively, in other embodiments, each processor 820 may be communicatively coupled to each memory device 720. In some embodiments, the memory devices 720 may be mounted to one or more memory mezzanines on the bottom side of the chassis-less circuit board substrate 602 and may interconnect with a corresponding processor 820 through a ball-grid array.

Each of the processors 820 includes a heatsink 850 secured thereto. Due to the mounting of the memory devices 720 to the bottom side 750 of the chassis-less circuit board substrate 602 (as well as the vertical spacing of the sleds 400 in the corresponding rack 240), the top side 650 of the chassis-less circuit board substrate 602 includes additional “free” area or space that facilitates the use of heatsinks 850 having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602, none of the processor heatsinks 850 include cooling fans attached thereto. That is, each of the heatsinks 850 is embodied as a fan-less heatsink. In some embodiments, the heat sinks 850 mounted atop the processors 820 may overlap with the heat sink attached to the communication circuit 830 in the direction of the airflow path 608 due to their increased size, as illustratively suggested by FIG. 9.

Referring now to FIG. 10, in some embodiments, the sled 400 may be embodied as an accelerator sled 1000. The accelerator sled 1000 is configured, to perform specialized compute tasks, such as machine learning, encryption, hashing, or other computational-intensive task. In some embodiments, for example, a compute sled 800 may offload tasks to the accelerator sled 1000 during operation. The accelerator sled 1000 includes various components similar to components of the sled 400 and/or compute sled 800, which have been identified in FIG. 10 using the same reference numbers. The description of such components provided above in regard to FIGS. 6, 7, and 8 apply to the corresponding components of the accelerator sled 1000 and is not repeated herein for clarity of the description of the accelerator sled 1000.

In the illustrative accelerator sled 1000, the physical resources 620 are embodied as accelerator circuits 1020. Although only two accelerator circuits 1020 are shown in FIG. 10, it should be appreciated that the accelerator sled 1000 may include additional accelerator circuits 1020 in other embodiments. For example, as shown in FIG. 11, the accelerator sled 1000 may include four accelerator circuits 1020 in some embodiments. The accelerator circuits 1020 may be embodied as any type of processor, co-processor, compute circuit, or other device capable of performing compute or processing operations. For example, the accelerator circuits 1020 may be embodied as, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), neuromorphic processor units, quantum computers, machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.

In some embodiments, the accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042. Similar to the resource-to-resource interconnect 624 of the sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the accelerator-to-accelerator interconnect 1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, the accelerator circuits 1020 may be daisy-chained with a primary accelerator circuit 1020 connected to the NIC 832 and memory 720 through the I/O subsystem 622 and a secondary accelerator circuit 1020 connected to the NIC 832 and memory 720 through a primary accelerator circuit 1020.

Referring now to FIG. 11, an illustrative embodiment of the accelerator sled 1000 is shown. As discussed above, the accelerator circuits 1020, communication circuit 830, and optical data connector 834 are mounted to the top side 650 of the chassis-less circuit board substrate 602. Again, the individual accelerator circuits 1020 and communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other as discussed above. The memory devices 720 of the accelerator sled 1000 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 600. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the accelerator circuits 1020 located on the top side 650 via the I/O subsystem 622 (e.g., through vias). Further, each of the accelerator circuits 1020 may include a heatsink 1070 that is larger than a traditional heatsink used in a server. As discussed above with reference to the heatsinks 870, the heatsinks 1070 may be larger than traditional heatsinks because of the “free” area provided by the memory resources 720 being located on the bottom side 750 of the chassis-less circuit board substrate 602 rather than on the top side 650.

Referring now to FIG. 12, in some embodiments, the sled 400 may be embodied as a storage sled 1200. The storage sled 1200 is configured, to store data in a data storage 1250 local to the storage sled 1200. For example, during operation, a compute sled 800 or an accelerator sled 1000 may store and retrieve data from the data storage 1250 of the storage sled 1200. The storage sled 1200 includes various components similar to components of the sled 400 and/or the compute sled 800, which have been identified in FIG. 12 using the same reference numbers. The description of such components provided above in regard to FIGS. 6, 7, and 8 apply to the corresponding components of the storage sled 1200 and is not repeated herein for clarity of the description of the storage sled 1200.

In the illustrative storage sled 1200, the physical resources 620 are embodied as storage controllers 1220. Although only two storage controllers 1220 are shown in FIG. 12, it should be appreciated that the storage sled 1200 may include additional storage controllers 1220 in other embodiments. The storage controllers 1220 may be embodied as any type of processor, controller, or control circuit capable of controlling the storage and retrieval of data into the data storage 1250 based on requests received via the communication circuit 830. In the illustrative embodiment, the storage controllers 1220 are embodied as relatively low-power processors or controllers. For example, in some embodiments, the storage controllers 1220 may be configured to operate at a power rating of about 75 watts.

In some embodiments, the storage sled 1200 may also include a controller-to-controller interconnect 1242. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.

Referring now to FIG. 13, an illustrative embodiment of the storage sled 1200 is shown. In the illustrative embodiment, the data storage 1250 is embodied as, or otherwise includes, a storage cage 1252 configured to house one or more solid state drives (SSDs) 1254. To do so, the storage cage 1252 includes a number of mounting slots 1256, each of which is configured to receive a corresponding solid state drive 1254. Each of the mounting slots 1256 includes a number of drive guides 1258 that cooperate to define an access opening 1260 of the corresponding mounting slot 1256. The storage cage 1252 is secured to the chassis-less circuit board substrate 602 such that the access openings face away from (i.e., toward the front of) the chassis-less circuit board substrate 602. As such, solid state drives 1254 are accessible while the storage sled 1200 is mounted in a corresponding rack 204. For example, a solid state drive 1254 may be swapped out of a rack 240 (e.g., via a robot) while the storage sled 1200 remains mounted in the corresponding rack 240.

The storage cage 1252 illustratively includes sixteen mounting slots 1256 and is capable of mounting and storing sixteen solid state drives 1254. Of course, the storage cage 1252 may be configured to store additional or fewer solid state drives 1254 in other embodiments. Additionally, in the illustrative embodiment, the solid state drivers are mounted vertically in the storage cage 1252, but may be mounted in the storage cage 1252 in a different orientation in other embodiments. Each solid state drive 1254 may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives 1254 may include volatile and non-volatile memory devices discussed above.

As shown in FIG. 13, the storage controllers 1220, the communication circuit 830, and the optical data connector 834 are illustratively mounted to the top side 650 of the chassis-less circuit board substrate 602. Again, as discussed above, any suitable attachment or mounting technology may be used to mount the electrical components of the storage sled 1200 to the chassis-less circuit board substrate 602 including, for example, sockets (e.g., a processor socket), holders, brackets, soldered connections, and/or other mounting or securing techniques.

As discussed above, the individual storage controllers 1220 and the communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. For example, the storage controllers 1220 and the communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those electrical components are linearly in-line with each other along the direction of the airflow path 608.

The memory devices 720 of the storage sled 1200 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the storage controllers 1220 located on the top side 650 via the I/O subsystem 622. Again, because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the storage controllers 1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Each of the storage controllers 1220 includes a heatsink 1270 secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602 of the storage sled 1200, none of the heatsinks 1270 include cooling fans attached thereto. That is, each of the heatsinks 1270 is embodied as a fan-less heatsink.

Referring now to FIG. 14, in some embodiments, the sled 400 may be embodied as a memory sled 1400. The storage sled 1400 is optimized, or otherwise configured, to provide other sleds 400 (e.g., compute sleds 800, accelerator sleds 1000, etc.) with access to a pool of memory (e.g., in two or more sets 1430, 1432 of memory devices 720) local to the memory sled 1200. For example, during operation, a compute sled 800 or an accelerator sled 1000 may remotely write to and/or read from one or more of the memory sets 1430, 1432 of the memory sled 1200 using a logical address space that maps to physical addresses in the memory sets 1430, 1432. The memory sled 1400 includes various components similar to components of the sled 400 and/or the compute sled 800, which have been identified in FIG. 14 using the same reference numbers. The description of such components provided above in regard to FIGS. 6, 7, and 8 apply to the corresponding components of the memory sled 1400 and is not repeated herein for clarity of the description of the memory sled 1400.

In the illustrative memory sled 1400, the physical resources 620 are embodied as memory controllers 1420. Although only two memory controllers 1420 are shown in FIG. 14, it should be appreciated that the memory sled 1400 may include additional memory controllers 1420 in other embodiments. The memory controllers 1420 may be embodied as any type of processor, controller, or control circuit capable of controlling the writing and reading of data into the memory sets 1430, 1432 based on requests received via the communication circuit 830. In the illustrative embodiment, each memory controller 1420 is connected to a corresponding memory set 1430, 1432 to write to and read from memory devices 720 within the corresponding memory set 1430, 1432 and enforce any permissions (e.g., read, write, etc.) associated with sled 400 that has sent a request to the memory sled 1400 to perform a memory access operation (e.g., read or write).

In some embodiments, the memory sled 1400 may also include a controller-to-controller interconnect 1442. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some embodiments, a memory controller 1420 may access, through the controller-to-controller interconnect 1442, memory that is within the memory set 1432 associated with another memory controller 1420. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled 1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, the memory controllers 1420 may implement a memory interleave (e.g., one memory address is mapped to the memory set 1430, the next memory address is mapped to the memory set 1432, and the third address is mapped to the memory set 1430, etc.). The interleaving may be managed within the memory controllers 1420, or from CPU sockets (e.g., of the compute sled 800) across network links to the memory sets 1430, 1432, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.

Further, in some embodiments, the memory sled 1400 may be connected to one or more other sleds 400 (e.g., in the same rack 240 or an adjacent rack 240) through a waveguide, using the waveguide connector 1480. In the illustrative embodiment, the waveguides are 64 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Tx (i.e., transmit) lanes. Each lane, in the illustrative embodiment, is either 16 GHz or 32 GHz. In other embodiments, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets 1430, 1432) to another sled (e.g., a sled 400 in the same rack 240 or an adjacent rack 240 as the memory sled 1400) without adding to the load on the optical data connector 834.

Referring now to FIG. 15, a system for executing one or more workloads (e.g., applications) may be implemented in accordance with the data center 100. In the illustrative embodiment, the system 1510 includes an orchestrator server 1520, which may be embodied as a managed node comprising a compute device (e.g., a processor 820 on a compute sled 800) executing management software (e.g., a cloud operating environment, such as OpenStack) that is communicatively coupled to multiple sleds 400 including a large number of compute sleds 1530 (e.g., each similar to the compute sled 800), memory sleds 1540 (e.g., each similar to the memory sled 1400), accelerator sleds 1550 (e.g., each similar to the memory sled 1000), and storage sleds 1560 (e.g., each similar to the storage sled 1200). One or more of the sleds 1530, 1540, 1550, 1560 may be grouped into a managed node 1570, such as by the orchestrator server 1520, to collectively perform a workload (e.g., an application 1532 executed in a virtual machine or in a container). The managed node 1570 may be embodied as an assembly of physical resources 620, such as processors 820, memory resources 720, accelerator circuits 1020, or data storage 1250, from the same or different sleds 400. Further, the managed node may be established, defined, or “spun up” by the orchestrator server 1520 at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node. In the illustrative embodiment, the orchestrator server 1520 may selectively allocate and/or deallocate physical resources 620 from the sleds 400 and/or add or remove one or more sleds 400 from the managed node 1570 as a function of quality of service (QoS) targets (e.g., performance targets associated with a throughput, latency, instructions per second, etc.) associated with a service level agreement for the workload (e.g., the application 1532). In doing so, the orchestrator server 1520 may receive telemetry data indicative of performance conditions (e.g., throughput, latency, instructions per second, etc.) in each sled 400 of the managed node 1570 and compare the telemetry data to the quality of service targets to determine whether the quality of service targets are being satisfied. The orchestrator server 1520 may additionally determine whether one or more physical resources may be deallocated from the managed node 1570 while still satisfying the QoS targets, thereby freeing up those physical resources for use in another managed node (e.g., to execute a different workload). Alternatively, if the QoS targets are not presently satisfied, the orchestrator server 1520 may determine to dynamically allocate additional physical resources to assist in the execution of the workload (e.g., the application 1532) while the workload is executing. Similarly, the orchestrator server 1520 may determine to dynamically deallocate physical resources from a managed node if the orchestrator server 1520 determines that deallocating the physical resource would result in QoS targets still being met.

Additionally, in some embodiments, the orchestrator server 1520 may identify trends in the resource utilization of the workload (e.g., the application 1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 1532) and pre-emptively identifying available resources in the data center 100 and allocating them to the managed node 1570 (e.g., within a predefined time period of the associated phase beginning). In some embodiments, the orchestrator server 1520 may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center 100. For example, the orchestrator server 1520 may utilize a model that accounts for the performance of resources on the sleds 400 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, the orchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and the sled 400 on which the resource is located).

In some embodiments, the orchestrator server 1520 may generate a map of heat generation in the data center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the sleds 400 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center 100. Additionally or alternatively, in some embodiments, the orchestrator server 1520 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center 100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. The orchestrator server 1520 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center 100.

To reduce the computational load on the orchestrator server 1520 and the data transfer load on the network, in some embodiments, the orchestrator server 1520 may send self-test information to the sleds 400 to enable each sled 400 to locally (e.g., on the sled 400) determine whether telemetry data generated by the sled 400 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Each sled 400 may then report back a simplified result (e.g., yes or no) to the orchestrator server 1520, which the orchestrator server 1520 may utilize in determining the allocation of resources to managed nodes.

Referring now to FIG. 16, a system 1600 for managing disaggregated resources in a data center (e.g., the data center 100 of FIG. 1) includes a cloud orchestrator server 1602, similar to the orchestrator server 1520 of FIG. 15, which is communicatively coupled to a controller compute device 1604. In use, as will be described in further detail below, the controller compute device 1604 is configured to function as a software defined infrastructure controller and resource manager for racks (e.g., the rack 240 in the data center 100 of FIG. 1) and pods (e.g., the pods 110, 120, 130, 140 in the data center 100 of FIG. 1). To do so, the controller compute device 1604 is configured to employ a system-level composable services framework and protocol to allow the controller compute device 1604 to function as an undercloud manager, including a task manager (e.g., functioning as a task scheduler and queue manager) with queues for asynchronous compute, network, and storage management.

Additionally, as will also be described in further detail below, the controller compute device 1604 is configured to perform hardware lifecycle management operations (e.g., discovery, composition, configuration, release, etc.) of the various disaggregated resources, dynamically and at scale. To do so, the controller compute device 1604 is configured to use a protocol of communication that can discover hardware capabilities, leverage composable services to map requests received from the orchestrator server 1520, service hardware composability requests, and perform telemetry-based autonomous actions.

The illustrative system 1600 additionally includes managed nodes 1622 communicatively coupled to the controller compute device 1604. The illustrative managed nodes 1622 includes a first managed node designated as managed node (1) 1622a and a second managed node designated as managed node (N) 1622b, in which the managed node (N) 1622b represents the “Nth” managed node 1622 and “N” is a positive integer. As described previously, one or more sleds (e.g., one or more of the sleds 1530, 1540, 1550, 1560 of FIG. 15) may be grouped into a managed node (e.g., by a pod manager service of the controller compute device 1604) to collectively perform a workload, such as an application. As such, the managed nodes 1622 may be embodied as an assembly of resources, such as compute resources, memory resources, storage resources, or other resources, from the same or different sleds or racks. Further, any of the managed nodes 1622 may be established, defined, or “spun up” by a respective pod manager service at the time a workload is to be assigned to a managed node 1622 or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node 1622.

The controller compute device 1604 may be embodied as any type of computation or computer device capable of performing the functions described herein, including, without limitation, a computer, a server (e.g., stand-alone, rack-mounted, blade, etc.), a sled (e.g., a compute sled, an accelerator sled, a storage sled, a memory sled, etc.), an enhanced or smart NIC (e.g., a host fabric interface (HFI)), a network appliance (e.g., physical or virtual), a router, a switch (e.g., a disaggregated switch, a rack-mounted switch, a standalone switch, a fully managed switch, a partially managed switch, a full-duplex switch, and/or a half-duplex communication mode enabled switch), a web appliance, a distributed computing system, a processor-based system, and/or a multiprocessor system. As shown in FIG. 16, the illustrative controller compute device 1604 includes a compute engine 1606, an I/O subsystem 1612, one or more data storage devices 1614, communication circuitry 1616, and, in some embodiments, one or more peripheral devices 1620. It should be appreciated that the controller compute device 1604 may include other or additional components, such as those commonly found in a typical computing device (e.g., various input/output devices and/or other components), in other embodiments. Additionally, in some embodiments, one or more of the illustrative components may be incorporated in, or otherwise form a portion of, another component.

The compute engine 1606 may be embodied as any type of device or collection of devices capable of performing the various compute functions as described herein. In some embodiments, the compute engine 1606 may be embodied as a single device such as an integrated circuit, an embedded system, a field-programmable-array (FPGA), a system-on-a-chip (SOC), an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein. Additionally, in some embodiments, the compute engine 1606 may include, or may otherwise be embodied as, one or more processors 1608 (i.e., one or more central processing units (CPUs)) and memory 1610.

The processor(s) 1608 may be embodied as any type of processor(s) capable of performing the functions described herein. For example, the processor(s) 1608 may be embodied as one or more single-core processors, multi-core processors, digital signal processors (DSPs), microcontrollers, or other processor(s) or processing/controlling circuit(s). In some embodiments, the processor(s) 1608 may be embodied as, include, or otherwise be coupled to an FPGA (e.g., reconfigurable circuitry), an ASIC, reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein.

The memory 1610 may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. It should be appreciated that the memory 1610 may include main memory (i.e., a primary memory) and/or cache memory (i.e., memory that can be accessed more quickly than the main memory). Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4. Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.

In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include a three dimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.

In such embodiments in which memory device includes a 3D crosspoint memory (e.g., Intel 3D XPoint™ memory), the memory 1610 may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In some embodiments, all or a portion of the memory 1610 may be integrated into a processor 1608. In operation, the memory 1610 may store various software and data used during operation such as applications, data operated on by the applications, routing rules, libraries, and drivers.

The compute engine 1606 is communicatively coupled to other components of the controller compute device 1604 via the I/O subsystem 1612, which may be embodied as circuitry and/or components to facilitate input/output operations with the processor 1608, the memory 1610, and other components of the controller compute device 1604. For example, the I/O subsystem 1612 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem 1612 may form a portion of a SoC and be incorporated, along with one or more of the processor 1608, the memory 1610, and other components of the controller compute device 1604, on a single integrated circuit chip.

The one or more data storage devices 1614 may be embodied as any type of storage device(s) configured for short-term or long-term storage of data, such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. Each data storage device 1614 may include a system partition that stores data and firmware code for the data storage device 1614. Each data storage device 1614 may also include an operating system partition that stores data files and executables for an operating system.

The communication circuitry 1616 may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications between the controller compute device 1604 and other computing devices, such as the source compute device 102, as well as any network communication enabling devices, such as an access point, network switch/router, etc., to allow communication over the network 104. Accordingly, the communication circuitry 1616 may be configured to use any one or more communication technologies (e.g., wireless or wired communication technologies) and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, LTE, 5G, etc.) to effect such communication.

It should be appreciated that, in some embodiments, the communication circuitry 1616 may include specialized circuitry, hardware, or combination thereof to perform pipeline logic (e.g., hardware algorithms) for performing the functions described herein, including processing network packets (e.g., parse received network packets, determine destination computing devices for each received network packets, forward the network packets to a particular buffer queue of a respective host buffer of the controller compute device 1604, etc.), performing computational functions, etc.

In some embodiments, performance of one or more of the functions of communication circuitry 1616 as described herein may be performed by specialized circuitry, hardware, or combination thereof of the communication circuitry 1616, which may be embodied as a SoC or otherwise form a portion of a SoC of the controller compute device 1604 (e.g., incorporated on a single integrated circuit chip along with a processor 1608, the memory 1610, and/or other components of the controller compute device 1604). Alternatively, in some embodiments, the specialized circuitry, hardware, or combination thereof may be embodied as one or more discrete processing units of the controller compute device 1604, each of which may be capable of performing one or more of the functions described herein.

The illustrative communication circuitry 1616 includes a network interface controller (NIC) 1618, which may also be referred to as a host fabric interface (HFI) in some embodiments (e.g., high performance computing (HPC) environments). The NIC 1618 may be embodied as any type of firmware, hardware, software, or any combination thereof that facilities communications access between the controller compute device 1604 and a network (e.g., the network 104). For example, the NIC 1618 may be embodied as one or more add-in-boards, daughtercards, network interface cards, controller chips, chipsets, or other devices that may be used by the controller compute device 1604 to connect with another compute device (e.g., the source compute device 102).

In some embodiments, the NIC 1618 may be embodied as part of a SoC that includes one or more processors, or included on a multichip package that also contains one or more processors. Additionally or alternatively, in some embodiments, the NIC 1618 may include one or more processing cores (not shown) local to the NIC 1618. In such embodiments, the processing core(s) may be capable of performing one or more of the functions described herein. In some embodiments, the NIC 1618 may additionally include a local memory (not shown). In such embodiments, the local memory of the NIC 1618 may be integrated into one or more components of the controller compute device 1604 at the board level, socket level, chip level, and/or other levels.

The one or more peripheral devices 1620 may include any type of device that is usable to input information into the controller compute device 1604 and/or receive information from the controller compute device 1604. The peripheral devices 1620 may be embodied as any auxiliary device usable to input information into the controller compute device 1604, such as a keyboard, a mouse, a microphone, a barcode reader, an image scanner, etc., or output information from the controller compute device 1604, such as a display, a speaker, graphics circuitry, a printer, a projector, etc. It should be appreciated that, in some embodiments, one or more of the peripheral devices 1620 may function as both an input device and an output device (e.g., a touchscreen display, a digitizer on top of a display screen, etc.). It should be further appreciated that the types of peripheral devices 1620 connected to the controller compute device 1604 may depend on, for example, the type and/or intended use of the controller compute device 1604. Additionally or alternatively, in some embodiments, the peripheral devices 1620 may include one or more ports, such as a universal serial bus (USB) port, for example, for connecting external peripheral devices to the controller compute device 1604.

The cloud orchestrator server 1602 may have components similar to those described in reference to the illustrative controller compute device 1604. As such, the description of those like and/or similar components of the controller compute device 1604 are equally applicable to the description of components of the orchestrator server 1602, and are not repeated herein for clarity of the description. Further, it should be appreciated that the orchestrator server 1602 may include other components, sub-components, and devices commonly found in a computing device, which are not discussed above in reference to the controller compute device 1604 and not discussed herein for clarity of the description. While illustratively shown as being a separate computing device from the orchestrator server 1602, it should be appreciated that, in other embodiments, at least a portion of the functions described herein as being performed by the controller compute device 1604 may be performed by the orchestrator server 1602.

Referring now to FIG. 17, in use, the controller compute device 1604 establishes an environment 1700 during operation. The illustrative environment 1700 includes a network traffic ingress/egress manager 1708, an application programming interface (API) manager 1710, a task manager 1714, a microservice resource controller 1716, and a microtask resource controller 1718. The various components of the environment 1700 may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of the environment 1700 may be embodied as circuitry or a collection of electrical devices (e.g., network traffic ingress/egress management circuitry 1708, API management circuitry 1710, task management circuitry 1714, microservice resource controller circuitry 1716, microtask resource controller circuitry 1718, etc.).

It should be appreciated that, in some embodiments, each of the one or more functions described herein as being performed by the controller compute device 1604 may be performed, at least in part, by one or more components of the controller compute device 1604, such as the compute engine 1606, the I/O subsystem 1612, and/or other components of the controller compute device 1604. As described previously, at least a portion of the functions described herein as being performed by the controller compute device 1604 may be performed by the orchestrator server 1602 in other embodiments. Accordingly, in such embodiments, it should be appreciated that one or more of the network traffic ingress/egress management circuitry 1708, the API management circuitry 1710, the task management circuitry 1714, the microservice resource controller circuitry 1716, and the microtask resource controller circuitry 1718 may reside on the orchestrator server 1602.

Additionally, in some embodiments, one or more of the illustrative components may form a portion of another component and/or one or more of the illustrative components may be independent of one another. Further, in some embodiments, one or more of the components of the environment 1700 may be embodied as virtualized hardware components or emulated architecture, which may be established and maintained by the compute engine 1606, the NIC 1618, and/or other software/hardware components of the controller compute device 1604. It should be appreciated that the controller compute device 1604 may include other components, sub-components, modules, sub-modules, logic, sub-logic, and/or devices commonly found in a computing device (e.g., device drivers, interfaces, etc.), which are not illustrated in FIG. 17 for clarity of the description.

In the illustrative environment 1700, the controller compute device 1604 additionally includes pod manager data 1702, task data 1704, and compose service data 1706, each of which may be accessed by the various components and/or sub-components of the controller compute device 1604. Further, each of the pod manager data 1702, the task data 1704, and the compose service data 1706 may be accessed by the various components of the controller compute device 1604. Additionally, it should be appreciated that in some embodiments the data stored in, or otherwise represented by, each of the pod manager data 1702, the task data 1704, and the compose service data 1706 may not be mutually exclusive relative to each other. For example, in some implementations, data stored in the pod manager data 1702 may also be stored as a portion of one or more of the task data 1704 and/or the compose service data 1706, or in another alternative arrangement. As such, although the various data utilized by the controller compute device 1604 is described herein as particular discrete data, such data may be combined, aggregated, and/or otherwise form portions of a single or multiple data sets, including duplicative copies, in other embodiments.

The network traffic ingress/egress manager 1708, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to receive inbound and route/transmit outbound network traffic. To do so, the illustrative network traffic ingress/egress manager 1708 is configured to facilitate inbound network communications (e.g., network traffic, network packets, network flows, etc.) to the controller compute device 1604. Accordingly, the network traffic ingress/egress manager 1708 is configured to manage (e.g., create, modify, delete, etc.) connections to physical and virtual network ports (i.e., virtual network interfaces) of the controller compute device 1604 (e.g., via the communication circuitry 1616), as well as the ingress buffers/queues associated therewith.

The API manager 1710, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to manage the API service 1712 instance to perform the functions as described herein. To do so, the API manager 1710 may be configured to instantiate the API service 1712 based on one or more characteristics, such as supported protocols (e.g., Representational State Transfer (REST), Extensible Markup Language (XML), etc.), libraries, etc. The API service 1712 is configured to provide multiple points for inbound API calls, and perform a translation thereof into corresponding message(s), as necessary, for internal consumption (e.g., by the task manager 1714). The API service 1712 is additionally configured to generate outbound calls (e.g., to the cloud orchestrator server 1602) based on messages received internally (e.g., from the task manager 1714).

The task manager 1714, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to schedule tasks received at the controller compute device 1604, such as may be received from an orchestrator server (e.g., the cloud orchestrator server 1602 of FIG. 16) communicatively coupled to the controller compute device 1604. In some embodiments, workload processing requests may be transmitted between the task manager 1714 and a pooled system management engine (PSME). In such embodiments, certain processing tasks may be coordinated between the task manager 1714 and the applicable PSME (e.g., via a corresponding pod manager service) for fulfillment by one or more devices associated with the PSME. It should be understood that the term “PSME” is nomenclature used by Intel Corporation and is used herein merely for convenience. It should be further understood that the PSME may be embodied as any sled-level, rack-level, or tray-level management engine.

In an illustrative example, the task manager 1714 is configured receive an indication that a request for the initiation of a service managed by the controller compute device 1604 has been received by the controller compute device 1604. In some embodiments, the task scheduler may receive such initialization requests via the API service 1712. The task manager 1714 is further configured to create tasks and any messages associated therewith that are usable to identify information associated with the created task (e.g., for the execution thereof). In an illustrative embodiment, the task manager 1714 may be configured to create a task-related message (e.g., based on a task management application protocol) that includes a header, a destination service, a source service, a task identifier, a task timestamp, a state of the task, and a request body. It should be appreciated that such tasks may be performed synchronously or asynchronously, and such task related information may be stored in the task data 1704. The task manager 1714 is further configured to post the created tasks to the appropriate task queue. Accordingly, the task manager 1714 is further configured to manage the queue of created tasks and the messages associated therewith for performing the tasks. In other words, the task manager 1714 is additionally configured to function as a task queue manager.

The microservice resource controller 1716, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to control the composition of disaggregated service resources (i.e., microservice resources) to compose a host (e.g., a node that can function as a server) to perform the requested services. It should be understood that a microservice is a software development technique that structures an application as a collection of loosely coupled services. Furthermore, in a microservices architecture, services are fine-grained and the protocols are lightweight. It should be further appreciated that such services are often processes that communicate over a network to fulfill a goal using technology-agnostic protocols or inter-process communication mechanisms (e.g., shared memory). As such, services in a microservice architecture are independently deployable, easy to replace, organized around capabilities, small in size, messaging enabled, bounded by contexts, autonomously developed, and decentralized.

The microservice resource controller 1716 is additionally configured to initialize any additional services associated with the operation of the composed nodes, such as a communication network, for example. To do so, the microservice resource controller 1716 is configured to manage disaggregated network resources, compute resources, storage resources, accelerator resources, etc., using an associated microservice (e.g., a network service, a storage service, a compute service, etc.) Accordingly, the microservice resource controller 1716 is configured to pick up (e.g., retrieve from the applicable task queue) and execute the tasks. It should be appreciated that each service controlled by the controller compute device 1604 is comprised of one or more microservices capable of providing one or more services thereof.

As such, the illustrative microservice resource controller 1716 includes a network service 1718, a storage service 1720, a compute service 1722, and a telemetry service 1724. The network service 1718 is configured to use network-related resources to perform a particular task associated with a requested controller service. The storage service 1720 is configured to use storage resources to perform particular storage-related tasks associated with a requested controller service. The compute service 1722 is configured to use compute and/or accelerator resources to perform particular storage-related tasks associated with a requested controller service. The telemetry service 1724 is configured to collect/store telemetry data in accordance with a requested controller service. It should be appreciated that the microservice resource controller 1716 may include additional and/or alternative services in other embodiments. In some embodiments, information associated with the composed resources may be stored in the composed service data 1706.

The microtask resource controller 1726, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to control the composition of disaggregated microservice resources (i.e., microtask resources) to perform the requested services. To do so, the illustrative microtask resource controller 1726 includes a database service 1728 configured to manage one or more databases, a timestamp service 1730 configured to apply timestamps, and a compose service 1732 configured to compose services via the microtask resources. The resource allocator 1734 is configured to allocate resources for each microtask, as may be requested by the other microtasks (e.g., the database service 1728, the timestamp service 1730, the compose service 1732, etc.) via a corresponding thread. It should be appreciated that the resource allocator 1734 is at the lowest level in the hierarchy of microtasks.

In other words, the compose service 1732 is configured to manage the composable hardware dynamically as necessary to scale up or down. Accordingly, the compose service 1732 can call the resource allocator 1734 to compose (e.g., configure, group, etc.) various resources, such as by workload for a particular service. For example, the compose service 1732 may be configured to initiate a discovery operation, create zones, provision a network, compose a host, release a host, provision storage, provision a node, etc.

To do so, for example, a PSME may be configured to detect resources (e.g., via a discovery that may be initiated by the controller compute device 1604), such that information related thereto (e.g., processing power, configuration, specialized functionality, average utilization, or the like) can be retrieved and provided to the resource allocator 1734. In such embodiments, for example, each sled (e.g., one of the compute sleds 1530) equipped with a PSME may detect device resources (e.g., NICs, ports, memory, CPUs, etc.) within the data center (e.g., the system 1510), including discovering information about each detected device (e.g., processing power, configuration, specialized functionality, average utilization, and/or the like) that is usable to schedule one or more portions (e.g., tasks) of an application to be processed by device(s) available in the system 1510 suited to performing the respective task. In some embodiments, the resource data may be stored in the pod manager data 1702.

Referring now to FIG. 18, in operation, the controller compute device 1604 may execute a method 1800 for managing disaggregated resources in a data center. As described previously, the disaggregated resources may include managing distributed pooled storage, distributed pooled compute, distributed pooled accelerators, etc. The method 1800 begins in block 1802, in which the controller compute device 1604 determines whether to initialize a service. It should be appreciated that initializing the service may include initializing a service to perform a particular function and/or composing one or more nodes to execute the initialized service. If so, the method 1800 advances to block 1804, in which the controller compute device 1604 stores information associated with the service to be initialized. In block 1806, the controller compute device 1604 creates a task based on the service to be initialized. In block 1808, the controller compute device 1604 inserts the created task into a corresponding task message queue.

In block 1810, the controller compute device 1604 determines whether the created task is to be processed, such as may be determinable when the created task is at a head of the task message queue. In other words, the controller compute device 1604 determines whether to compose the requested service. If so, the method 1800 advances to block 1812, in which the controller compute device 1604 creates a microservice to perform the created task. It should be appreciated that the controller compute device 1604 may create the microservice to be hosted on more than one host device. Accordingly, under such conditions, the host devices may be configured to communicate between the pod manager services (e.g., using a main service over Advanced Message Queuing Protocol (AMQP)).

To create the microservice, in block 1814, the controller compute device 1604 composes the microservice as a collection of services, which can be instantiated within their respective namespace by any service, for example the illustrative network service 1718, storage service 1720, compute service 1722, and/or telemetry service 1724 of FIG. 17, or any other service/microservice that may be associated with the microservice resource controller 1716 of FIG. 17 in other embodiments. In block 1816, the controller compute device 1604 creates each of the collection of services as a collection of microtasks (e.g., via the resource allocator 1734 of FIG. 17), such as, for example, the illustrative database service 1728, timestamp service 1730, and/or compose service 1732 of FIG. 17, or any other service/microtask that may be associated with the microtask resource controller 1726 of FIG. 17 in other embodiments.

From block 1816, the method 1800 advances to blocks 1818 and 1822, either serially or in parallel. In other words, blocks 1818 and 1822 can be performed in parallel. In block 1818, the controller compute device 1604 creates one or more threads to perform any asynchronous task(s) associated with the created microservice, including any hardware management lifecycle operations, network management operations, network slice allocations, etc., as described herein (see, e.g., the communication flows 1900 of FIG. 19, 2000 of FIG. 20, 2100 of FIG. 21, and 2200 of FIG. 22). In block 1820, the controller compute device 1604 completes any asynchronous tasks associated with the created threads in the background. In block 1822, the controller compute device 1604 completes any synchronous task(s) associated with the created microservice.

It should be appreciated that, depending on the conditions at the time at which the service initialization request was received, the relevant microservice may have already been created, but that additional microtasks may be required to be spun-up in support of that microservice. It should be further appreciated that such spun-up microtasks can either be shut down when the work has completed or maintain a live state for future use, depending on the embodiment.

Referring now to FIG. 19, an embodiment of an illustrative communication flow 1900 for performing hardware lifecycle management operations is shown that includes the cloud orchestrator server 1602 and the controller compute device 1604 of FIG. 16. The illustrative controller compute device 1604 includes the API service 1712, the task manager 1714, the microservice resource controller 1716, and the microtask resource controller of FIG. 17. The illustrative communication flow 1900 includes a number of data flows, some of which may be executed separately or together, depending on the embodiment. In data flow 1902, the cloud orchestrator server 1602 determines to orchestrate a VM to run an application which requires various compute resources.

To do so, in data flow 1904, the cloud orchestrator server 1602 transmits a service orchestration request (e.g., via an applicable API call) that includes a list of resources (e.g., compute resources, storage resources, network resources, accelerator resources, etc.) to the API service 1712 that are usable to identify which resources are required to compose a node. As described previously, system resources (e.g., memory devices, data storage devices, accelerator devices, general purpose processors, etc.) can be logically coupled to form a composed node, which can act as, for example, a server. In data flow 1906, the API service 1712 forwards the received service orchestration request to the task manager 1714. It should be appreciated that the API service 1712 may generate a new message that effectively translates the received service orchestration request into a message interpretable by the task manager 1714 to perform the requested service orchestration. Upon receipt of the message, the task manager 1714 determines that a node is to be composed and storage allocated thereto. As such, in data flow 1908, the task manager 1714 generates and enqueues a task to orchestrate the requested node.

In data flow 1910, the microservice resource controller 1716 allocates the task (e.g., via one or more services) to initiate composition of the requested node and, in data flow 1912, transmits a notification of the allocated task to the microtask resource controller 1726. In data flow 1914, the microtask resource controller 1726 (e.g., via the compose service 1732 of FIG. 17) allocates a thread (e.g., from a thread pool) to call a pod manager (e.g., a via a pod manager service) to discover resources of the associated hardware cluster. Additionally, in data flow 1916, the microtask resource controller 1726 (e.g., via the resource allocator 1734 of FIG. 17) allocates a thread to call a compose API of the pod manager to compose a portion of the discovered resources. Further, in data flow 1918, the microtask resource controller 1726 (e.g., via the resource allocator 1734 of FIG. 17) allocates a thread to deploy a storage volume. In data flow 1920, the microtask resource controller 1726 transmits a notification of the composed node resources to the microservice resource controller 1716. In data flow 1922, the microservice resource controller 1716 transmits a notification of completion to the cloud orchestrator server 1602 (e.g., via the task manager 1714 and the API service 1712) that includes an identifier of the composed node.

Referring now to FIG. 20, an embodiment of an illustrative communication flow 2000 for scheduling and managing groups of nodes (e.g., the managed nodes 1622 of FIG. 16) is shown that includes the cloud orchestrator server 1602 and the controller compute device 1604 of FIG. 16. The illustrative controller compute device 1604 includes the API service 1712, the task manager 1714, the microservice resource controller 1716, and the microtask resource controller of FIG. 17. The illustrative communication flow 2000 includes a number of data flows, some of which may be executed separately or together, depending on the embodiment. In data flow 2002, the cloud orchestrator server 1602 determines a set of VMs or containers and wants to compose and provision a group of nodes.

To do so, in data flow 2004, the cloud orchestrator server 1602 transmits a service orchestration request (e.g., via an applicable API call) to the API service 1712 that includes a list of required node characteristics (e.g., compute resources, storage resources, network resources, accelerator resources, configuration settings, etc.). In data flow 2006, the API service 1712 forwards the received service orchestration request to the task manager 1714 with a system group notification. It should be appreciated that the API service 1712 may generate a new message that effectively translates the received service orchestration request into a message interpretable by the task manager 1714 to perform the requested service orchestration. Upon receipt of the message, the task manager 1714 determines that a group of nodes are to be composed and storage allocated thereto. As such, in data flow 2008, the task manager 1714 spawns and enqueues multiple tasks to orchestrate the requested nodes.

In data flow 2010, the microservice resource controller 1716 allocates each task (e.g., via one or more services) to initiate composition of the requested nodes and, in data flow 2012, transmits a notification of the allocated tasks to the microtask resource controller 1726. In data flow 2014, the microtask resource controller 1726 (e.g., via the compose service 1732 of FIG. 17) allocates threads (e.g., from a thread pool) to call a pod manager to discover resources of the associated hardware cluster. Additionally, in data flow 2016, the microtask resource controller 1726 (e.g., via the resource allocator 1734 of FIG. 17) allocates threads to call a compose API of the pod manager to compose a portion of the discovered resources. Further, in data flow 2018, the microtask resource controller 1726 (e.g., via the resource allocator 1734 of FIG. 17) allocates threads to deploy a storage volumes, as necessary. In data flow 2020, the microtask resource controller 1726 transmits a notification of the composed nodes to the microservice resource controller 1716. In data flow 2022, the microservice resource controller 1716 transmits a notification of completion to the cloud orchestrator server 1602 (e.g., via the task manager 1714 and the API service 1712) that includes an identifier of each of the composed nodes and an identifier of the group of composed nodes.

Referring now to FIG. 21, an embodiment of an illustrative communication flow 2100 for managing an underlay network is shown that includes the cloud orchestrator server 1602 and the controller compute device 1604 of FIG. 16. The illustrative controller compute device 1604 includes the API service 1712, the task manager 1714, the microservice resource controller 1716, and the microtask resource controller of FIG. 17. The illustrative communication flow 2100 includes a number of data flows, some of which may be executed separately or together, depending on the embodiment. In data flow 2102, the cloud orchestrator server 1602 determines that an underlay network (e.g., a virtual local area network (VLAN), a Virtual Extensible LAN (VxLAN), etc.) is required with specific configurations for particular network traffic associated with a tenant (e.g., based on a service-level agreement (SLA)).

To do so, in data flow 2104, the cloud orchestrator server 1602 transmits a service orchestration request (e.g., via an applicable API call) to the API service 1712 that includes a set of configuration settings of the underlay network. In data flow 2106, the API service 1712 forwards the request to the task manager 1714. As described previously, it should be appreciated that the API service 1712 may generate a new message that effectively translates the received service orchestration request into a message interpretable by the task manager 1714 to perform the requested service orchestration. In data flow 2108, the task manager 1714 spawns a task to compose network resources (e.g., via the network service 1718). Upon receipt of the network resource composition task, in data flow 2110, the microservice resource controller 1716 starts one or more threads (e.g., one or more master threads) to allocate the requested network resources.

In data flow 2112, the microtask resource controller 1726 allocates a thread to configure one or more ports of a switch of the system (e.g., the switch 150 of FIG. 1 or one of the switches 250, 260 of FIG. 2). In data flow 2114, the microtask resource controller 1726 allocates another thread to configure one or more ports of one or more end-hosts (e.g., composed node(s)). In some embodiments, the configuration may be performed via a communicatively coupled pod manager (not shown), such as may be performed via one or more pod manager network API calls. It should be appreciated that, depending on the embodiment, the task manager 1714 may be configured to spawn additional tasks for the microservice resource controller 1716 to start additional threads to provision other network services (e.g., a VLAN on the host and switch). Accordingly, in such embodiments, the pod manager network API and a switch API may be called at that time. Upon completion, the microservice resource controller 1716 transmits a notification of completion to the cloud orchestrator server 1602 (e.g., via the task manager 1714 and the API service 1712) that includes a completion code and an identifier of the underlay network.

Referring now to FIG. 22, an embodiment of an illustrative communication flow 2200 for allocating a network slice is shown that includes the cloud orchestrator server 1602 and the controller compute device 1604 of FIG. 16. The illustrative controller compute device 1604 includes the API service 1712, the task manager 1714, the microservice resource controller 1716, and the microtask resource controller of FIG. 17. The illustrative communication flow 2200 includes a number of data flows, some of which may be executed separately or together, depending on the embodiment. In data flow 2202, the cloud orchestrator server 1602 determines that a network slice is required with specific configurations for a telecommunications network. It should be understood that vetwork slicing is a form of virtual network architecture using the same/similar principles as software defined networks (SDNs) and network function virtualization (NFV) architectures in fixed networks that allows multiple logical networks to run on top of a shared physical network infrastructure.

To do so, in data flow 2204, the cloud orchestrator server 1602 transmits a service orchestration request (e.g., via an applicable API call) to the API service 1712 that includes a list of required resources for the network slice, such as a specific accelerator resource for performing certain functions of the network slice. In data flow 2206, the API service 1712 transmits a request to the task manager 1714 to attach resources to a composed node (see, e.g., the communication flow 1900 of FIG. 19). In data flow 2208, the API service 1712 transmits a request to the task manager 1714 to start a service and network to communicate with the attached resources. In data flow 2210, the task manager 1714 spawns the appropriate tasks to attach the resources, and start the communication service and network. In data flow 2212, the microservice resource controller 1716 allocates tasks to initiate composition of the requested resources and services.

In data flow 2214, the microservice resource controller 1716 transmits a notification of the allocated tasks. Accordingly, in data flow 2216, the microtask resource controller 1726 allocates a thread to call a pod manager (e.g., via the applicable API calls to that pod manager) to attach the required resources to a composed node. Additionally, in data flow 2218, the microtask resource controller 1726 allocates a thread to communicate with the switch (e.g., the switch 150 of FIG. 1 or one of the switches 250, 260 of FIG. 2) to create a network to the attached resources of the composed node. In data flow 2220, the microtask resource controller 1726 transmits a notification that the allocation threads have completed. In data flow 2222, the microservice resource controller 1716 transmits a notification of completion to the cloud to the cloud orchestrator server 1602 (e.g., via the task manager 1714 and the API service 1712) that includes an identifier of each allocated resource.

EXAMPLES

Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.

Example 1 includes a compute device for managing disaggregated resources in a data center, the compute device comprising microservice resource controller circuitry to (i) determine that a service related task has been generated and (ii) create one or more microservices to perform the determined service related task using at least one of a plurality of services managed by the microservice resource controller circuitry; and microtask resource controller circuitry to generate one or more microtasks to compose at least one service based on the one or more microservices.

Example 2 includes the subject matter of Example 1, and wherein to generate the one or more microtasks comprises to create one or more threads for each of the one or more microservices, and wherein each of the one or more threads is to execute a respective one of the one or more microtasks.

Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to create the one or more threads comprises to allocate a first thread to call a pod manager of the data center to discover resources of a hardware cluster of the data center.

Example 4 includes the subject matter of any of Examples 1-3, and wherein to create the one or more threads further comprises to allocate a second thread to compose a portion of the discovered resources into a composed node that is configured to function as a server.

Example 5 includes the subject matter of any of Examples 1-4, and wherein to create the one or more threads further comprises to allocate a third thread to deploy a storage volume to be associated with the composed node.

Example 6 includes the subject matter of any of Examples 1-5, and wherein the microservice resource controller circuitry is further to transmit a notification of completion to an entity that requested composition of the composed node, and wherein the notification of completion includes an identifier of the composed node.

Example 7 includes the subject matter of any of Examples 1-6, and wherein to create the one or more threads further comprises to allocate a plurality of threads to compose a portion of the discovered resources into a group of composed nodes, wherein each composed node of the group of composed nodes is configured to function as a server.

Example 8 includes the subject matter of any of Examples 1-7, and wherein the microservice resource controller circuitry is further to transmit a notification of completion to an entity that requested composition of the composed node, and wherein the notification of completion includes an identifier of each composed node of the group of composed nodes and a group identifier that identifies the group of composed nodes.

Example 9 includes the subject matter of any of Examples 1-8, and wherein to determine that the service related task has been generated comprises to determine that an underlay network of the data center is to be orchestrated, wherein to create the one or more threads comprises to start a master thread to compose network resources, and wherein the master thread is to (i) allocate a child thread to configure one or more switch ports of a switch of the data center and (ii) allocate one or more threads to configured one or more host ports of a node of the data center.

Example 10 includes the subject matter of any of Examples 1-9, and wherein the microservice resource controller circuitry is further to transmit a notification of completion to an entity that requested the underlay network to be orchestrated, and wherein the notification of completion includes a completion code and an identifier of the underlay network.

Example 11 includes the subject matter of any of Examples 1-10, and wherein to determine that the service related task has been generated comprises to determine that the generated service related task indicates that at least one node is to be orchestrated.

Example 12 includes the subject matter of any of Examples 1-11, and wherein the resources include compute resources, storage resources, and network resources.

Example 13 includes a compute device for managing disaggregated resources in a data center, the compute device comprising a compute engine to determine that a service related task has been generated and (ii) create one or more microservices to perform the determined service related task using at least one of a plurality of services managed by the compute engine; and microtask resource controller circuitry to generate one or more microtasks to compose at least one service based on the one or more microservices.

Example 14 includes the subject matter of Example 13, and wherein to generate the microtask comprises to create one or more threads for each of the one or more microservices, and wherein each of the one or more threads is to execute a respective one of the one or more microtasks.

Example 15 includes the subject matter of any of Examples 13 and 14, and wherein to determine that the service related task has been generated comprises to determine that the generated service related task indicates that at least one node is to be orchestrated, and wherein to create the one or more threads comprises to allocate a first thread to call a pod manager of the data center to discover resources of a hardware cluster of the data center, wherein the resources include compute resources, storage resources, and network resources.

Example 16 includes the subject matter of any of Examples 13-15, and wherein to create the one or more threads further comprises to allocate a second thread to compose a portion of the discovered resources into a composed node that is configured to function as a server.

Example 17 includes the subject matter of any of Examples 13-16, and wherein to create the one or more threads further comprises to allocate a third thread to deploy a storage volume to be associated with the composed node.

Example 18 includes the subject matter of any of Examples 13-17, and wherein the compute engine is further to transmit a notification of completion to an entity that requested composition of the composed node, and wherein the notification of completion includes an identifier of the composed node.

Example 19 includes the subject matter of any of Examples 13-18, and wherein to create the one or more threads further comprises to allocate a plurality of threads to compose a portion of the discovered resources into a group of composed nodes, wherein each composed node of the group of composed nodes is configured to function as a server.

Example 20 includes the subject matter of any of Examples 13-19, and wherein the compute engine is further to transmit a notification of completion to an entity that requested composition of the composed node, and wherein the notification of completion includes an identifier of each composed node of the group of composed nodes and a group identifier that identifies the group of composed nodes.

Example 21 includes the subject matter of any of Examples 13-20, and wherein to determine that the service related task has been generated comprises to determine that an underlay network of the data center is to be orchestrated, wherein to create the one or more threads comprises to start a master thread to compose network resources of the data center, and wherein the master thread is to (i) allocate a child thread to configure one or more switch ports of a switch of the data center and (ii) allocate one or more threads to configured one or more host ports of a node of the data center.

Example 22 includes the subject matter of any of Examples 13-21, and wherein the compute engine is further to transmit a notification of completion to an entity that requested the underlay network to be orchestrated, and wherein the notification of completion includes a completion code and an identifier of the underlay network.

Example 23 includes a method for managing disaggregated resources in a data center, the method comprising determining, by a compute device, that a service related task has been generated; creating, by the compute device, one or more microservices to perform the determined service related task using at least one of a plurality of services managed by the compute device; and generating, by the compute device, one or more microtasks to compose at least one service based on the one or more microservices.

Example 24 includes the subject matter of Example 23, and wherein generating the microtask comprises creating one or more threads for each of the one or more microservices, and wherein each of the one or more threads is to execute a respective one of the one or more microtasks.

Example 25 includes the subject matter of any of Examples 23 and 24, and wherein determining that the service related task has been generated comprises determining that the generated service related task indicates that at least one node is to be orchestrated, and wherein creating the one or more threads comprises allocating a first thread to call a pod manager of the data center to discover resources of a hardware cluster of the data center, wherein the resources include compute resources, storage resources, and network resources.

TECHNOLOGIES FOR MANAGING DISAGGREGATED RESOURCES IN A DATA CENTER

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