Patent Application
20190065231
Network operators and service providers typically rely on various network virtualization technologies to manage complex, large-scale computing environments, such as high-performance computing (HPC) and cloud computing environments. Typically, these computing environments, or data centers, are comprised of a multitude of network computing devices (e.g., servers, switches, routers, etc.) which are configured to perform various operations (e.g., process network traffic through the data center, store data, perform computations, etc.). In order to provide scalability to meet demand and reduce operational costs, certain data center operations are typically run inside containers or virtual machines (VMs) in a virtualized environment of one or more of the network computing devices.
Oftentimes, for various reasons (e.g., data center closures, compromised server security, disaster recovery, network infrastructure upgrades, etc.), a container or VM being executed on one network computing device needs to be migrated to another. Although container/VM migration can be a useful tool, the migrations typically require the copying of data (e.g., the container/VM requirements, the workload, the stored data associated with the workload, etc.) across the network between the network computing devices. The data copy typically introduces network traffic, resulting in bandwidth consumption that could otherwise be used for other operations.
The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).
In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.
Referring now to
Referring now to
It should be appreciated that each of the other pods 120, 130, 140 (as well as any additional pods of the data center 100) may be similarly structured as, and have components similar to, the pod 110 shown in and described in regard to
Referring now to
In the illustrative embodiments, each sled of the data center 100 is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, the rack 240 is configured to receive the chassis-less sleds. For example, each pair 310 of elongated support arms 312 defines a sled slot 320 of the rack 240, which is configured to receive a corresponding chassis-less sled. To do so, each illustrative elongated support arm 312 includes a circuit board guide 330 configured to receive the chassis-less circuit board substrate of the sled. Each circuit board guide 330 is secured to, or otherwise mounted to, a top side 332 of the corresponding elongated support arm 312. For example, in the illustrative embodiment, each circuit board guide 330 is mounted at a distal end of the corresponding elongated support arm 312 relative to the corresponding elongated support post 302, 304. For clarity of the Figures, not every circuit board guide 330 may be referenced in each Figure.
Each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 configured to receive the chassis-less circuit board substrate of a sled 400 when the sled 400 is received in the corresponding sled slot 320 of the rack 240. To do so, as shown in
It should be appreciated that each circuit board guide 330 is dual sided. That is, each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 on each side of the circuit board guide 330. In this way, each circuit board guide 330 can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to the rack 240 to turn the rack 240 into a two-rack solution that can hold twice as many sled slots 320 as shown in
In some embodiments, various interconnects may be routed upwardly or downwardly through the elongated support posts 302, 304. To facilitate such routing, each elongated support post 302, 304 includes an inner wall that defines an inner chamber in which the interconnect may be located. The interconnects routed through the elongated support posts 302, 304 may be embodied as any type of interconnects including, but not limited to, data or communication interconnects to provide communication connections to each sled slot 320, power interconnects to provide power to each sled slot 320, and/or other types of interconnects.
The rack 240, in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with a corresponding sled slot 320 and is configured to mate with an optical data connector of a corresponding sled 400 when the sled 400 is received in the corresponding sled slot 320. In some embodiments, optical connections between components (e.g., sleds, racks, and switches) in the data center 100 are made with a blind mate optical connection. For example, a door on each cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable enters the connector mechanism. Subsequently, the optical fiber inside the cable enters a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism.
The illustrative rack 240 also includes a fan array 370 coupled to the cross-support arms of the rack 240. The fan array 370 includes one or more rows of cooling fans 372, which are aligned in a horizontal line between the elongated support posts 302, 304. In the illustrative embodiment, the fan array 370 includes a row of cooling fans 372 for each sled slot 320 of the rack 240. As discussed above, each sled 400 does not include any on-board cooling system in the illustrative embodiment and, as such, the fan array 370 provides cooling for each sled 400 received in the rack 240. Each rack 240, in the illustrative embodiment, also includes a power supply associated with each sled slot 320. Each power supply is secured to one of the elongated support arms 312 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320. For example, the rack 240 may include a power supply coupled or secured to each elongated support arm 312 extending from the elongated support post 302. Each power supply includes a power connector configured to mate with a power connector of the sled 400 when the sled 400 is received in the corresponding sled slot 320. In the illustrative embodiment, the sled 400 does not include any on-board power supply and, as such, the power supplies provided in the rack 240 supply power to corresponding sleds 400 when mounted to the rack 240.
Referring now to
As discussed above, the illustrative sled 400 includes a chassis-less circuit board substrate 602, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that the circuit board substrate 602 is “chassis-less” in that the sled 400 does not include a housing or enclosure. Rather, the chassis-less circuit board substrate 602 is open to the local environment. The chassis-less circuit board substrate 602 may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, the chassis-less circuit board substrate 602 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-less circuit board substrate 602 in other embodiments.
As discussed in more detail below, the chassis-less circuit board substrate 602 includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602. As discussed, the chassis-less circuit board substrate 602 does not include a housing or enclosure, which may improve the airflow over the electrical components of the sled 400 by reducing those structures that may inhibit air flow. For example, because the chassis-less circuit board substrate 602 is not positioned in an individual housing or enclosure, there is no backplane (e.g., a backplate of the chassis) to the chassis-less circuit board substrate 602, which could inhibit air flow across the electrical components. Additionally, the chassis-less circuit board substrate 602 has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-less circuit board substrate 602. For example, the illustrative chassis-less circuit board substrate 602 has a width 604 that is greater than a depth 606 of the chassis-less circuit board substrate 602. In one particular embodiment, for example, the chassis-less circuit board substrate 602 has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, an airflow path 608 that extends from a front edge 610 of the chassis-less circuit board substrate 602 toward a rear edge 612 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of the sled 400. Furthermore, although not illustrated in
As discussed above, the illustrative sled 400 includes one or more physical resources 620 mounted to a top side 650 of the chassis-less circuit board substrate 602. Although two physical resources 620 are shown in
The sled 400 also includes one or more additional physical resources 630 mounted to the top side 650 of the chassis-less circuit board substrate 602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of the sled 400, the physical resources 630 may include additional or other electrical components, circuits, and/or devices in other embodiments.
The physical resources 620 are communicatively coupled to the physical resources 630 via an input/output (I/O) subsystem 622. The I/O subsystem 622 may be embodied as circuitry and/or components to facilitate input/output operations with the physical resources 620, the physical resources 630, and/or other components of the sled 400. For example, the I/O subsystem 622 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative embodiment, the I/O subsystem 622 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDR5 data bus.
In some embodiments, the sled 400 may also include a resource-to-resource interconnect 624. The resource-to-resource interconnect 624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect 624 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the resource-to-resource interconnect 624 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.
The sled 400 also includes a power connector 640 configured to mate with a corresponding power connector of the rack 240 when the sled 400 is mounted in the corresponding rack 240. The sled 400 receives power from a power supply of the rack 240 via the power connector 640 to supply power to the various electrical components of the sled 400. That is, the sled 400 does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of the sled 400. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-less circuit board substrate 602, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602 as discussed above. In some embodiments, power is provided to the processors 820 through vias directly under the processors 820 (e.g., through the bottom side 750 of the chassis-less circuit board substrate 602), providing an increased thermal budget, additional current and/or voltage, and better voltage control over typical boards.
In some embodiments, the sled 400 may also include mounting features 642 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled 600 in a rack 240 by the robot. The mounting features 642 may be embodied as any type of physical structures that allow the robot to grasp the sled 400 without damaging the chassis-less circuit board substrate 602 or the electrical components mounted thereto. For example, in some embodiments, the mounting features 642 may be embodied as non-conductive pads attached to the chassis-less circuit board substrate 602. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-less circuit board substrate 602. The particular number, shape, size, and/or make-up of the mounting feature 642 may depend on the design of the robot configured to manage the sled 400.
Referring now to
The memory devices 720 may be embodied as any type of memory device capable of storing data for the physical resources 620 during operation of the sled 400, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include next-generation nonvolatile devices, such as Intel 3D XPoint™ memory or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
Referring now to
In the illustrative compute sled 800, the physical resources 620 are embodied as processors 820. Although only two processors 820 are shown in
In some embodiments, the compute sled 800 may also include a processor-to-processor interconnect 842. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the processor-to-processor interconnect 842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 842 communications. In the illustrative embodiment, the processor-to-processor interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the processor-to-processor interconnect 842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
The compute sled 800 also includes a communication circuit 830. The illustrative communication circuit 830 includes a network interface controller (NIC) 832, which may also be referred to as a host fabric interface (HFI). The NIC 832 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, other devices that may be used by the compute sled 800 to connect with another compute device (e.g., with other sleds 400). In some embodiments, the NIC 832 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 832 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 832. In such embodiments, the local processor of the NIC 832 may be capable of performing one or more of the functions of the processors 820. Additionally or alternatively, in such embodiments, the local memory of the NIC 832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels.
The communication circuit 830 is communicatively coupled to an optical data connector 834. The optical data connector 834 is configured to mate with a corresponding optical data connector of the rack 240 when the compute sled 800 is mounted in the rack 240. Illustratively, the optical data connector 834 includes a plurality of optical fibers which lead from a mating surface of the optical data connector 834 to an optical transceiver 836. The optical transceiver 836 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of the optical data connector 834 in the illustrative embodiment, the optical transceiver 836 may form a portion of the communication circuit 830 in other embodiments.
In some embodiments, the compute sled 800 may also include an expansion connector 840. In such embodiments, the expansion connector 840 is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to the compute sled 800. The additional physical resources may be used, for example, by the processors 820 during operation of the compute sled 800. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-less circuit board substrate 602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.
Referring now to
As discussed above, the individual processors 820 and communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. In the illustrative embodiment, the processors 820 and communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those physical resources are linearly in-line with others along the direction of the airflow path 608. It should be appreciated that, although the optical data connector 834 is in-line with the communication circuit 830, the optical data connector 834 produces no or nominal heat during operation.
The memory devices 720 of the compute sled 800 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the processors 820 located on the top side 650 via the I/O subsystem 622. Because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the processors 820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Of course, each processor 820 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments. Alternatively, in other embodiments, each processor 820 may be communicatively coupled to each memory device 720. In some embodiments, the memory devices 720 may be mounted to one or more memory mezzanines on the bottom side of the chassis-less circuit board substrate 602 and may interconnect with a corresponding processor 820 through a ball-grid array.
Each of the processors 820 includes a heatsink 850 secured thereto. Due to the mounting of the memory devices 720 to the bottom side 750 of the chassis-less circuit board substrate 602 (as well as the vertical spacing of the sleds 400 in the corresponding rack 240), the top side 650 of the chassis-less circuit board substrate 602 includes additional “free” area or space that facilitates the use of heatsinks 850 having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602, none of the processor heatsinks 850 include cooling fans attached thereto. That is, each of the heatsinks 850 is embodied as a fan-less heatsinks.
Referring now to
In the illustrative accelerator sled 1000, the physical resources 620 are embodied as accelerator circuits 1020. Although only two accelerator circuits 1020 are shown in
In some embodiments, the accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042. Similar to the resource-to-resource interconnect 624 of the sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the accelerator-to-accelerator interconnect 1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, the accelerator circuits 1020 may be daisy-chained with a primary accelerator circuit 1020 connected to the NIC 832 and memory 720 through the I/O subsystem 622 and a secondary accelerator circuit 1020 connected to the NIC 832 and memory 720 through a primary accelerator circuit 1020.
Referring now to
Referring now to
In the illustrative storage sled 1200, the physical resources 620 are embodied as storage controllers 1220. Although only two storage controllers 1220 are shown in
In some embodiments, the storage sled 1200 may also include a controller-to-controller interconnect 1242. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
Referring now to
The storage cage 1252 illustratively includes sixteen mounting slots 1256 and is capable of mounting and storing sixteen solid state drives 1254. Of course, the storage cage 1252 may be configured to store additional or fewer solid state drives 1254 in other embodiments. Additionally, in the illustrative embodiment, the solid state drivers are mounted vertically in the storage cage 1252, but may be mounted in the storage cage 1252 in a different orientation in other embodiments. Each solid state drive 1254 may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives 1254 may include volatile and non-volatile memory devices discussed above.
As shown in
As discussed above, the individual storage controllers 1220 and the communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. For example, the storage controllers 1220 and the communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those electrical components are linearly in-line with other along the direction of the airflow path 608.
The memory devices 720 of the storage sled 1200 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the storage controllers 1220 located on the top side 650 via the I/O subsystem 622. Again, because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the storage controllers 1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Each of the storage controllers 1220 includes a heatsink 1270 secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602 of the storage sled 1200, none of the heatsinks 1270 include cooling fans attached thereto. That is, each of the heatsinks 1270 is embodied as a fan-less heatsink.
Referring now to
In the illustrative memory sled 1400, the physical resources 620 are embodied as memory controllers 1420. Although only two memory controllers 1420 are shown in
In some embodiments, the memory sled 1400 may also include a controller-to-controller interconnect 1442. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some embodiments, a memory controller 1420 may access, through the controller-to-controller interconnect 1442, memory that is within the memory set 1432 associated with another memory controller 1420. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled 1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, the memory controllers 1420 may implement a memory interleave (e.g., one memory address is mapped to the memory set 1430, the next memory address is mapped to the memory set 1432, and the third address is mapped to the memory set 1430, etc.). The interleaving may be managed within the memory controllers 1420, or from CPU sockets (e.g., of the compute sled 800) across network links to the memory sets 1430, 1432, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.
Further, in some embodiments, the memory sled 1400 may be connected to one or more other sleds 400 (e.g., in the same rack 240 or an adjacent rack 240) through a waveguide, using the waveguide connector 1480. In the illustrative embodiment, the waveguides are 64 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Rt (i.e., transmit) lanes. Each lane, in the illustrative embodiment, is either 16 Ghz or 32 Ghz. In other embodiments, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets 1430, 1432) to another sled (e.g., a sled 400 in the same rack 240 or an adjacent rack 240 as the memory sled 1400) without adding to the load on the optical data connector 834.
Referring now to
Additionally, in some embodiments, the orchestrator server 1520 may identify trends in the resource utilization of the workload (e.g., the application 1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 1532) and pre-emptively identifying available resources in the data center 100 and allocating them to the managed node 1570 (e.g., within a predefined time period of the associated phase beginning). In some embodiments, the orchestrator server 1520 may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center 100. For example, the orchestrator server 1520 may utilize a model that accounts for the performance of resources on the sleds 400 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, the orchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and the sled 400 on which the resource is located).
In some embodiments, the orchestrator server 1520 may generate a map of heat generation in the data center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the sleds 400 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center 100. Additionally or alternatively, in some embodiments, the orchestrator server 1520 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center 100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. The orchestrator server 1520 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center 100.
To reduce the computational load on the orchestrator server 1520 and the data transfer load on the network, in some embodiments, the orchestrator server 1520 may send self-test information to the sleds 400 to enable each sled 400 to locally (e.g., on the sled 400) determine whether telemetry data generated by the sled 400 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Each sled 400 may then report back a simplified result (e.g., yes or no) to the orchestrator server 1520, which the orchestrator server 1520 may utilize in determining the allocation of resources to managed nodes.
Referring now to
In use, the resource manager server 1606 receives an indication or otherwise identifies that a VM instance (e.g., the virtual machine 1616) presently being executed on one compute sled 1602 (e.g., compute sled (1) 1602a) is to be migrated to another compute sled 1602 (e.g., compute sled (2) 1602b). Accordingly, as will be described in further detail below, the resource manager server 1606 manages the migration. However, unlike present technologies in which the VM instance 1616 and all associated data would be required to be migrated from the initial compute sled 1602a to the other compute sled 1602b, a previously allocated region of memory in a memory pool (e.g., the memory 1612 of the memory pool 1614) which was associated with (i.e., mapped to) the initial compute sled 1602a is re-mapped to be associated with the other compute sled 1602b. As such, the data stored in the memory pool 1614 does not need to be transferred across the network fabric at any point in the migration of the VM, thereby eliminating the bandwidth consumption associated with the network traffic which would have otherwise been required to copy the data across the network fabric.
The resource manager server 1606 may be embodied as any type of computing device capable of monitoring and managing resources of the compute sleds 1602, as well as performing the other functions described herein. For example, the resource manager server 1606 may be embodied as a computer, a distributed computing system, one or more sleds, a server (e.g., stand-alone, rack-mounted, blade, etc.), a multiprocessor system, a network appliance (e.g., physical or virtual), a desktop computer, a workstation, a laptop computer, a notebook computer, a processor-based system, or a network appliance. As shown in
The compute engine 1702 may be embodied as any type of device or collection of devices capable of performing the various compute functions as described herein. In some embodiments, the compute engine 1702 may be embodied as a single device such as an integrated circuit, an embedded system, a field-programmable-array (FPGA), a system-on-a-chip (SOC), an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein. Additionally, in some embodiments, the compute engine 1702 may include, or may be embodied as, a processor 1704 (i.e., a central processing unit (CPU)) and memory 1706.
The processor 1704 may be embodied as any type of processor capable of performing the functions described herein. For example, the processor 1704 may be embodied as a single or multi-core processor(s), digital signal processor, microcontroller, or other processor or processing/controlling circuit. In some embodiments, the processor 1704 may be embodied as, include, or otherwise be coupled to a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein.
The memory 1706 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein. It should be appreciated that the memory 1706 may include main memory (i.e., a primary memory) and/or cache memory (i.e., memory that can be accessed more quickly than the main memory). Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM).
One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include future generation nonvolatile devices, such as a three dimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.
In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™ memory) may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In some embodiments, all or a portion of the memory 1706 may be integrated into the processor 1704. In operation, the memory 1706 may store various software and data used during operation such as job request data, kernel map data, telemetry data, applications, programs, libraries, and drivers.
The compute engine 1702 is communicatively coupled to other components of the resource manager server 1606 via the I/O subsystem 1708, which may be embodied as circuitry and/or components to facilitate input/output operations with the processor 1704, the memory 1706, and other components of the resource manager server 1606. For example, the I/O subsystem 1708 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem 1708 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with one or more of the processor 1704, the memory 1706, and other components of the resource manager server 1606, on a single integrated circuit chip.
The one or more data storage devices 1710 may be embodied as any type of storage device(s) configured for short-term or long-term storage of data, such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. Each data storage device 1710 may include a system partition that stores data and firmware code for the data storage device 1710. Each data storage device 1710 may also include an operating system partition that stores data files and executables for an operating system.
The communication circuitry 1712 may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications between the resource manager server 1606 and other compute devices (e.g., the compute sleds 1602 of
The illustrative communication circuitry 1712 includes a network interface controller (NIC) 1714, which may also be referred to as a host fabric interface (HFI). The NIC 1714 may be embodied as one or more add-in-boards, daughtercards, network interface cards, controller chips, chipsets, or other devices that may be used by the resource manager server 1606 to connect with another compute device (e.g., one of the compute sleds 1602 of
The one or more peripheral devices 1716 may include any type of device that is usable to input information into the resource manager server 1606 and/or receive information from the resource manager server 1606. The peripheral devices 1716 may be embodied as any auxiliary device usable to input information into the resource manager server 1606, such as a keyboard, a mouse, a microphone, a barcode reader, an image scanner, etc., or output information from the resource manager server 1606, such as a display, a speaker, graphics circuitry, a printer, a projector, etc. It should be appreciated that, in some embodiments, one or more of the peripheral devices 1716 may function as both an input device and an output device (e.g., a touchscreen display, a digitizer on top of a display screen, etc.). It should be further appreciated that the types of peripheral devices 1716 connected to the resource manager server 1606 may depend on, for example, the type and/or intended use of the resource manager server 1606. Additionally or alternatively, in some embodiments, the peripheral devices 1716 may include one or more ports, such as a USB port, for example, for connecting external peripheral devices to the resource manager server 1606.
Referring back to
The compute sleds 1602 may be embodied as any type of compute device capable of performing the functions described herein, including instantiating/stopping/starting a VM instance and executing a workload (e.g., within the VM instance). As shown in
Referring again to
The memory 1612 of the memory pool 1614 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM).
One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory 1612 may be embodied as a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include future generation nonvolatile devices, such as a three dimensional (3D) crosspoint memory device (e.g., Intel 3D XPoint™ memory), or other byte addressable write-in-place nonvolatile memory devices. In such embodiments, the 3D crosspoint memory (e.g., Intel 3D XPoint™ memory) may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
In another embodiment, the memory 1612 may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.
The illustrative compute sleds 1602 include a first compute sled, designated as compute sled (1) 1602a, a second compute sled, designated as compute sled (2) 1602b, and a third compute sled, designated as compute sled (N) 1602c (e.g., in which the compute sled (N) 1602c represents the “Nth” compute sled 1602, wherein “N” is a positive integer). It should be appreciated that, in some embodiments, one or more of the compute sleds 1602 may be grouped into a managed node, such as by the resource manager server 1606, to collectively perform a workload, such as an application. A managed node may be embodied as an assembly of resources, such as compute resources, memory resources, storage resource, or other resources, from the same or different sleds or racks.
Further, a managed node may be established, defined, or “spun up” by the resource manager server 1606 at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node. The resource manager server 1606 may, in some embodiments, perform one or more orchestration operations in support of a cloud operating environment, such as OpenStack, and managed nodes established by the resource manager server 1606 may execute one or more applications or processes (i.e., workloads), such as in the VMs or containers, on behalf of a user of a client device (not shown) communicatively coupled to the resource manager server 1606 (e.g., via a network).
Referring now to
In the illustrative embodiment, the environment 1900 additionally includes resource data 1902 and virtual machine data 1904, each of which may be embodied as any data established by the resource manager server 1606. The resource data 1902 may include any data usable to identify and/or allocate resources of the compute sleds 1602 and/or the memory sled 1608. The virtual machine data 1904 may include any data usable to identify VM instances (e.g., the VM instance 1616 of
The network connection manager 1910, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from the resource manager server 1606, respectively. To do so, the network connection manager 1910 is configured to receive and process data packets from one system or computing device (e.g., one of the compute sleds 1602) and to prepare and send data packets to another computing device or system (e.g., one of the compute sleds 1602). Accordingly, in some embodiments, at least a portion of the functionality of the network connection manager 1910 may be performed by the communication circuitry 1712, or more particularly by the NIC 1714.
The memory pool communicator 1920, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate transmissions between the resource manager server 1606 and a memory pool controller of a memory pool (e.g., the memory pool controller 1610 of the memory pool 1614 of
The resource allocator 1930, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to manage the available and allocated resources of the compute sleds 1602. To do so, the resource allocator 1930 may be configured to identify data associated with the resources, such as a compute capacity/availability, a memory bandwidth capacity/availability, a data storage capacity/availability, and/or a level of reliability, resiliency, and/or availability of the resources. In some embodiments, the resource allocator 1930 may be configured to store data related to the presently and/or historically available and/or allocated resources in the resource data 1902.
The VM instance manager 1940, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to manage the creation, migration, and deletion of VM instances on the compute sleds 1602. To do so, the illustrative VM instance manager 1940 includes a resource identifier 1942 and a migration manager 1944. The resource identifier 1942 is configured to identify which resources to allocate for a particular purpose (e.g., a workload). Such resources may be allocated by type, amount, performance, intended use, etc., and may include network communication resources, storage resources, compute resources, etc.
The migration manager 1944 is configured to detect whether a migration trigger has been detected. To do so, for example, the migration manager 1944 may be configured to collect or otherwise analyze collected telemetry data to determine whether certain conditions exist such that a migration of a VM from one compute sled 1602 to another compute sled 1602, or more particularly from a CPU on a compute sled 1602 (e.g., the processor 1804 of the illustrative compute sled 1602 of
Additionally, the migration manager 1944 is configured to manage the migration of a VM instance in response to having detected a migration triggering event. To do so, the migration manager 1944 may be configured to identify the compute sled 1602 on which the VM instance to be migrated is presently being executed and transmit an indication to the identified compute sled 1602 that indicates which VM instance is to be migrated. Accordingly, upon receipt, the compute sled 1602 can stop the VM instance and initiate a data flush to a mapped region of memory in a memory pool (e.g., the memory 1612 in the memory pool 1614 of
Referring now to
In block 2006, the resource manager server 1606 determines a compute sled 1602 (e.g., one of the compute sled (1) 1602a, the compute sled (2) 1602b, the compute sled (N) 1602c of
In block 2012, the resource manager server 1606 allocates resources of the determined compute sled for use by the VM instance. In block 2014, the resource manager server 1606 allocates a region of memory in a memory pool (e.g., the memory 1612 in the memory pool 1614 of
Referring now to
In block 2106, the resource manager server 1606 determines another compute sled 1602 on which to migrate the VM instance 1616 to. To do so, in block 2108, the resource manager server 1606 first identifies the available resources of each of the other available compute sleds 1602. Additionally, in block 2110, the resource manager server 1606 determines the compute sled to migrate the VM instance 1616 to based on the retrieved resources required by the workload and the identified available resources of each of the other available compute sleds 1602.
In block 2112, the resource manager server 1606 allocates resources of the determined other compute sled for use by the VM instance 1616 upon being migrated. In block 2114, the resource manager server 1606 migrates the VM instance 1616 to the other determined compute sled 1602. In other words, the data (e.g., software/hardware thread states) associated with the workload being processed by the VM instance 1616 and/or data corresponding to the VM instance 1616 itself are migrated to the other compute sled 1602. In block 2116, the resource manager server 1606 re-maps the region of memory in the memory pool from the previously associated compute sled 1602 (i.e., from which the VM instance 1616 is being migrated from) to the other compute sled 1602 (i.e., to which the VM instance 1616 is being migrated to). To do so, in block 2118, the resource manager server 1606 transmits a memory re-map request to a memory pool controller (e.g., the memory pool controller 1610) of the memory pool 1614. Additionally, in block 2120, the resource manager server 1606 includes information usable to re-map the allocated memory region from the previously associated compute sled 1602 to the compute sled 1602 which the VM instance 1616 is being migrated to. In block 2122, the resource manager server 1606 starts-up the VM instance 1616 on the other compute sled 1602.
Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
Example 1 includes a resource manager server for migrating virtual machines, the resource manager server comprising a compute engine to identify a compute sled of a plurality of compute sleds for a virtual machine (VM) instance, wherein each of the compute sleds is communicatively coupled to the resource manager server; allocate a first set of resources of the identified compute sled for the VM instance; associate a region of memory in a memory pool of a memory sled with the compute sled, wherein the memory sled is communicatively coupled to the resource manager server; create the VM instance on the compute sled; allocate, in response to determined determination that the VM instance is to be migrated, a second set of resources of another compute sled of the plurality of compute sleds for the VM instance; migrate the VM instance to the other compute sled; associate the region of memory in the memory pool with the other compute sled; and start-up the VM instance on the other compute sled.
Example 2 includes the subject matter of Example 1, and wherein to allocate the first set of resources of the compute sled comprises to (i) determine a set of resources required by a workload to be processed by the VM instance and (ii) allocate the first set of resources of the compute sled as a function of the determined required set of resources.
Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to allocate the first set of resources of the compute sled further comprises to (i) identify available resources of each of the plurality of compute sleds and (ii) allocate the first set of resources of the compute sled as a function of the identified available resources.
Example 4 includes the subject matter of any of Examples 1-3, and wherein to associate the region of memory in the memory pool of the memory sled with the compute sled comprises to transmit a memory allocation request to a memory pool controller of the memory pool that is usable to allocate the region of memory and map the allocated region of memory to the compute sled.
Example 5 includes the subject matter of any of Examples 1-4, and wherein to migrate the VM instance to the other compute sled comprises to transmit one or more threads associated with the workload associated with the VM instance to the other compute sled.
Example 6 includes the subject matter of any of Examples 1-5, and wherein to associate the region of memory in the memory pool of the memory sled with the other compute sled comprises to transmit a memory allocation request to a memory pool controller of the memory pool that is usable to map the allocated region of memory to the other compute sled.
Example 7 includes the subject matter of any of Examples 1-6, and wherein to allocate the second set of resources of the compute sled comprises to (i) retrieve a set of resources required by a workload being processed by the VM instance and (ii) allocate the second set of resources of the compute sled as a function of the retrieved required set of resources.
Example 8 includes the subject matter of any of Examples 1-7, and wherein to allocate the second set of resources of the other compute sled further comprises to (i) identify available resources of each of the plurality of compute sleds and (ii) allocate the second set of resources of the other compute sled as a function of the identified available resources.
Example 9 includes a method for migrating virtual machines, the comprising identifying, by a compute engine of a resource manager server, a compute sled of a plurality of compute sleds for a virtual machine (VM) instance, wherein each of the compute sleds is communicatively coupled to the resource manager server; allocating, by the compute engine, a first set of resources of the identified compute sled for the VM instance; associating, by the compute engine, a region of memory in a memory pool of a memory sled with the compute sled, wherein the memory sled is communicatively coupled to the resource manager server; creating, by the compute engine, the VM instance on the compute sled; allocating, by the compute engine and in response to determined determination that the VM instance is to be migrated, a second set of resources of another compute sled of the plurality of compute sleds for the VM instance; migrating, by the compute engine, the VM instance to the other compute sled; associating, by the compute engine, the region of memory in the memory pool with the other compute sled; and starting-up, by the compute engine, the VM instance on the other compute sled.
Example 10 includes the subject matter of Example 9, and wherein allocating the first set of resources of the compute sled comprises determining a set of resources required by a workload to be processed by the VM instance; and allocating the first set of resources of the compute sled as a function of the determined required set of resources.
Example 11 includes the subject matter of any of Examples 9 and 10, and wherein allocating the first set of resources of the compute sled further comprises identifying available resources of each of the plurality of compute sleds; and allocating the first set of resources of the compute sled as a function of the identified available resources.
Example 12 includes the subject matter of any of Examples 9-11, and wherein associating the region of memory in the memory pool of the memory sled with the compute sled comprises transmitting a memory allocation request to a memory pool controller of the memory pool that is usable to allocate the region of memory and map the allocated region of memory to the compute sled.
Example 13 includes the subject matter of any of Examples 9-12, and wherein migrating the VM instance to the other compute sled comprises transmitting one or more threads associated with the workload associated with the VM instance to the other compute sled.
Example 14 includes the subject matter of any of Examples 9-13, and wherein associating the region of memory in the memory pool of the memory sled with the other compute sled comprises transmitting a memory allocation request to a memory pool controller of the memory pool that is usable to map the allocated region of memory to the other compute sled.
Example 15 includes the subject matter of any of Examples 9-14, and wherein allocating the second set of resources of the compute sled comprises retrieving a set of resources required by a workload being processed by the VM instance; and allocating the second set of resources of the compute sled as a function of the retrieved required set of resources.
Example 16 includes the subject matter of any of Examples 9-15, and wherein allocating the second set of resources of the other compute sled further comprises identifying available resources of each of the plurality of compute sleds; and allocating the second set of resources of the other compute sled as a function of the identified available resources.
Example 17 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a resource manager server to perform the method of any of Examples 9-16.
Example 18 includes a resource manager server for improving throughput in a network, the resource manager server comprising one or more processors; one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the resource manager server to perform the method of any of Examples 9-16.
Example 19 includes a resource manager server for migrating virtual machines, the resource manager server comprising virtual machine instance management circuitry to identify a compute sled of a plurality of compute sleds for a virtual machine (VM) instance, wherein each of the compute sleds is communicatively coupled to the resource manager server; allocate a first set of resources of the identified compute sled for the VM instance; associate a region of memory in a memory pool of a memory sled with the compute sled, wherein the memory sled is communicatively coupled to the resource manager server; create the VM instance on the compute sled; allocate, in response to determined determination that the VM instance is to be migrated, a second set of resources of another compute sled of the plurality of compute sleds for the VM instance; migrate the VM instance to the other compute sled; associate the region of memory in the memory pool with the other compute sled; and start-up the VM instance on the other compute sled.
Example 20 includes the subject matter of Example 19, and wherein to allocate the first set of resources of the compute sled comprises to (i) determine a set of resources required by a workload to be processed by the VM instance and (ii) allocate the first set of resources of the compute sled as a function of the determined required set of resources.
Example 21 includes the subject matter of any of Examples 19 and 20, and wherein to allocate the first set of resources of the compute sled further comprises to (i) identify available resources of each of the plurality of compute sleds and (ii) allocate the first set of resources of the compute sled as a function of the identified available resources.
Example 22 includes the subject matter of any of Examples 19-21, and wherein to associate the region of memory in the memory pool of the memory sled with the compute sled comprises to transmit a memory allocation request to a memory pool controller of the memory pool that is usable to allocate the region of memory and map the allocated region of memory to the compute sled.
Example 23 includes the subject matter of any of Examples 19-22, and wherein to migrate the VM instance to the other compute sled comprises to transmit one or more threads associated with the workload associated with the VM instance to the other compute sled.
Example 24 includes the subject matter of any of Examples 19-23, and wherein to associate the region of memory in the memory pool of the memory sled with the other compute sled comprises to transmit a memory allocation request to a memory pool controller of the memory pool that is usable to map the allocated region of memory to the other compute sled.
Example 25 includes the subject matter of any of Examples 19-24, and wherein to allocate the second set of resources of the compute sled comprises to (i) retrieve a set of resources required by a workload being processed by the VM instance and (ii) allocate the second set of resources of the compute sled as a function of the retrieved required set of resources.
Example 26 includes the subject matter of any of Examples 19-25, and wherein to allocate the second set of resources of the other compute sled further comprises to (i) identify available resources of each of the plurality of compute sleds and (ii) allocate the second set of resources of the other compute sled as a function of the identified available resources.
Example 27 includes a resource manager server for migrating virtual machines, the resource manager server comprising circuitry for identifying, by a compute engine of the resource manager server, a compute sled of a plurality of compute sleds for a virtual machine (VM) instance, wherein each of the compute sleds is communicatively coupled to the resource manager server; circuitry for allocating, by the compute engine, a first set of resources of the identified compute sled for the VM instance; means for associating, by the compute engine, a region of memory in a memory pool of a memory sled with the compute sled, wherein the memory sled is communicatively coupled to the resource manager server; circuitry for creating, by the compute engine, the VM instance on the compute sled; circuitry for allocating, by the compute engine and in response to determined determination that the VM instance is to be migrated, a second set of resources of another compute sled of the plurality of compute sleds for the VM instance; circuitry for migrating, by the compute engine, the VM instance to the other compute sled; means for associating, by the compute engine, the region of memory in the memory pool with the other compute sled; and circuitry for starting-up, by the compute engine, the VM instance on the other compute sled.
Example 28 includes the subject matter of Example 27, and wherein the circuitry for allocating the first set of resources of the compute sled comprises means for determining a set of resources required by a workload to be processed by the VM instance; and circuitry for allocating the first set of resources of the compute sled as a function of the determined required set of resources.
Example 29 includes the subject matter of any of Examples 27 and 28, and wherein the circuitry for allocating the first set of resources of the compute sled further comprises means for identifying available resources of each of the plurality of compute sleds; and circuitry for allocating the first set of resources of the compute sled as a function of the identified available resources.
Example 30 includes the subject matter of any of Examples 27-29, and wherein the means for associating the region of memory in the memory pool of the memory sled with the compute sled comprises means for transmitting a memory allocation request to a memory pool controller of the memory pool that is usable to allocate the region of memory and map the allocated region of memory to the compute sled.
Example 31 includes the subject matter of any of Examples 27-30, and wherein the circuitry for migrating the VM instance to the other compute sled comprises circuitry for transmitting one or more threads associated with the workload associated with the VM instance to the other compute sled.
Example 32 includes the subject matter of any of Examples 27-31, and wherein the means for associating the region of memory in the memory pool of the memory sled with the other compute sled comprises means for transmitting a memory allocation request to a memory pool controller of the memory pool that is usable to map the allocated region of memory to the other compute sled.
Example 33 includes the subject matter of any of Examples 27-32, and wherein the circuitry for allocating the second set of resources of the compute sled comprises circuitry for retrieving a set of resources required by a workload being processed by the VM instance; and circuitry for allocating the second set of resources of the compute sled as a function of the retrieved required set of resources.
Example 34 includes the subject matter of any of Examples 27-33, and wherein the circuitry for allocating the second set of resources of the other compute sled further comprises means for identifying available resources of each of the plurality of compute sleds; and circuitry for allocating the second set of resources of the other compute sled as a function of the identified available resources.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201741030632 | Aug 2017 | IN | national |
The present application claims the benefit of U.S. Provisional Patent Application No. 62/427,268, filed Nov. 29, 2016 and Indian Provisional Patent Application No. 201741030632, filed Aug. 30, 2017.
| Number | Date | Country | |
|---|---|---|---|
| 62584401 | Nov 2017 | US |
