Patent Application
20190065083
The present application claims the benefit of Indian Provisional Patent Application No. 201741030632, filed Aug. 30, 2017, and U.S. Provisional Patent Application No. 62/584,401, filed Nov. 10, 2017.
Accelerator devices, such as field programmable gate arrays (FPGA) or other devices capable of accelerating the execution of a function are usually directly attached to a central processing unit (CPU) using a high-speed interconnect (e.g., PCI Express, RLink, etc.). In some data centers, however, accelerator devices may be decoupled from a host (e.g., a compute device executing an application that may periodically request acceleration of a function) such that applications executing on a multitude of hosts can access the accelerator devices as needed. There are myriad application frameworks as well as applications that have custom stacks to access accelerator devices. Further, the use of accelerator devices by an application may range from using a single accelerator device to using multiple accelerator devices concurrently. The wide gamut of application programming models, frameworks, and protocols used to access accelerator devices typically results in a significant amount of the available capacity (e.g., logic gates, processing cycles, etc.) of each accelerator device being devoted to managing communications with the hosts (e.g., parsing requests submitted in various protocols), when that capacity could otherwise be allocated to accelerating functions on behalf of the hosts in the data center.
The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).
In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.
Referring now to
Referring now to
It should be appreciated that each of the other pods 120, 130, 140 (as well as any additional pods of the data center 100) may be similarly structured as, and have components similar to, the pod 110 shown in and described in regard to
Referring now to
In the illustrative embodiments, each sled of the data center 100 is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, the rack 240 is configured to receive the chassis-less sleds. For example, each pair 310 of elongated support arms 312 defines a sled slot 320 of the rack 240, which is configured to receive a corresponding chassis-less sled. To do so, each illustrative elongated support arm 312 includes a circuit board guide 330 configured to receive the chassis-less circuit board substrate of the sled. Each circuit board guide 330 is secured to, or otherwise mounted to, a top side 332 of the corresponding elongated support arm 312. For example, in the illustrative embodiment, each circuit board guide 330 is mounted at a distal end of the corresponding elongated support arm 312 relative to the corresponding elongated support post 302, 304. For clarity of the Figures, not every circuit board guide 330 may be referenced in each Figure.
Each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 configured to receive the chassis-less circuit board substrate of a sled 400 when the sled 400 is received in the corresponding sled slot 320 of the rack 240. To do so, as shown in
It should be appreciated that each circuit board guide 330 is dual sided. That is, each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 on each side of the circuit board guide 330. In this way, each circuit board guide 330 can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to the rack 240 to turn the rack 240 into a two-rack solution that can hold twice as many sled slots 320 as shown in
In some embodiments, various interconnects may be routed upwardly or downwardly through the elongated support posts 302, 304. To facilitate such routing, each elongated support post 302, 304 includes an inner wall that defines an inner chamber in which the interconnect may be located. The interconnects routed through the elongated support posts 302, 304 may be embodied as any type of interconnects including, but not limited to, data or communication interconnects to provide communication connections to each sled slot 320, power interconnects to provide power to each sled slot 320, and/or other types of interconnects.
The rack 240, in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with a corresponding sled slot 320 and is configured to mate with an optical data connector of a corresponding sled 400 when the sled 400 is received in the corresponding sled slot 320. In some embodiments, optical connections between components (e.g., sleds, racks, and switches) in the data center 100 are made with a blind mate optical connection. For example, a door on each cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable enters the connector mechanism. Subsequently, the optical fiber inside the cable enters a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism.
The illustrative rack 240 also includes a fan array 370 coupled to the cross-support arms of the rack 240. The fan array 370 includes one or more rows of cooling fans 372, which are aligned in a horizontal line between the elongated support posts 302, 304. In the illustrative embodiment, the fan array 370 includes a row of cooling fans 372 for each sled slot 320 of the rack 240. As discussed above, each sled 400 does not include any on-board cooling system in the illustrative embodiment and, as such, the fan array 370 provides cooling for each sled 400 received in the rack 240. Each rack 240, in the illustrative embodiment, also includes a power supply associated with each sled slot 320. Each power supply is secured to one of the elongated support arms 312 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320. For example, the rack 240 may include a power supply coupled or secured to each elongated support arm 312 extending from the elongated support post 302. Each power supply includes a power connector configured to mate with a power connector of the sled 400 when the sled 400 is received in the corresponding sled slot 320. In the illustrative embodiment, the sled 400 does not include any on-board power supply and, as such, the power supplies provided in the rack 240 supply power to corresponding sleds 400 when mounted to the rack 240.
Referring now to
As discussed above, the illustrative sled 400 includes a chassis-less circuit board substrate 602, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that the circuit board substrate 602 is “chassis-less” in that the sled 400 does not include a housing or enclosure. Rather, the chassis-less circuit board substrate 602 is open to the local environment. The chassis-less circuit board substrate 602 may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, the chassis-less circuit board substrate 602 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-less circuit board substrate 602 in other embodiments.
As discussed in more detail below, the chassis-less circuit board substrate 602 includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602. As discussed, the chassis-less circuit board substrate 602 does not include a housing or enclosure, which may improve the airflow over the electrical components of the sled 400 by reducing those structures that may inhibit air flow. For example, because the chassis-less circuit board substrate 602 is not positioned in an individual housing or enclosure, there is no backplane (e.g., a backplate of the chassis) to the chassis-less circuit board substrate 602, which could inhibit air flow across the electrical components. Additionally, the chassis-less circuit board substrate 602 has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-less circuit board substrate 602. For example, the illustrative chassis-less circuit board substrate 602 has a width 604 that is greater than a depth 606 of the chassis-less circuit board substrate 602. In one particular embodiment, for example, the chassis-less circuit board substrate 602 has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, an airflow path 608 that extends from a front edge 610 of the chassis-less circuit board substrate 602 toward a rear edge 612 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of the sled 400. Furthermore, although not illustrated in
As discussed above, the illustrative sled 400 includes one or more physical resources 620 mounted to a top side 650 of the chassis-less circuit board substrate 602. Although two physical resources 620 are shown in
The sled 400 also includes one or more additional physical resources 630 mounted to the top side 650 of the chassis-less circuit board substrate 602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of the sled 400, the physical resources 630 may include additional or other electrical components, circuits, and/or devices in other embodiments.
The physical resources 620 are communicatively coupled to the physical resources 630 via an input/output (I/O) subsystem 622. The I/O subsystem 622 may be embodied as circuitry and/or components to facilitate input/output operations with the physical resources 620, the physical resources 630, and/or other components of the sled 400. For example, the I/O subsystem 622 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative embodiment, the I/O subsystem 622 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDR5 data bus.
In some embodiments, the sled 400 may also include a resource-to-resource interconnect 624. The resource-to-resource interconnect 624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect 624 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the resource-to-resource interconnect 624 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.
The sled 400 also includes a power connector 640 configured to mate with a corresponding power connector of the rack 240 when the sled 400 is mounted in the corresponding rack 240. The sled 400 receives power from a power supply of the rack 240 via the power connector 640 to supply power to the various electrical components of the sled 400. That is, the sled 400 does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of the sled 400. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-less circuit board substrate 602, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602 as discussed above. In some embodiments, power is provided to the processors 820 through vias directly under the processors 820 (e.g., through the bottom side 750 of the chassis-less circuit board substrate 602), providing an increased thermal budget, additional current and/or voltage, and better voltage control over typical boards.
In some embodiments, the sled 400 may also include mounting features 642 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled 600 in a rack 240 by the robot. The mounting features 642 may be embodied as any type of physical structures that allow the robot to grasp the sled 400 without damaging the chassis-less circuit board substrate 602 or the electrical components mounted thereto. For example, in some embodiments, the mounting features 642 may be embodied as non-conductive pads attached to the chassis-less circuit board substrate 602. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-less circuit board substrate 602. The particular number, shape, size, and/or make-up of the mounting feature 642 may depend on the design of the robot configured to manage the sled 400.
Referring now to
The memory devices 720 may be embodied as any type of memory device capable of storing data for the physical resources 620 during operation of the sled 400, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include next-generation nonvolatile devices, such as Intel 3D XPoint™ memory or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
Referring now to
In the illustrative compute sled 800, the physical resources 620 are embodied as processors 820. Although only two processors 820 are shown in
In some embodiments, the compute sled 800 may also include a processor-to-processor interconnect 842. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the processor-to-processor interconnect 842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 842 communications. In the illustrative embodiment, the processor-to-processor interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the processor-to-processor interconnect 842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
The compute sled 800 also includes a communication circuit 830. The illustrative communication circuit 830 includes a network interface controller (NIC) 832, which may also be referred to as a host fabric interface (HFI). The NIC 832 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, other devices that may be used by the compute sled 800 to connect with another compute device (e.g., with other sleds 400). In some embodiments, the NIC 832 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 832 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 832. In such embodiments, the local processor of the NIC 832 may be capable of performing one or more of the functions of the processors 820. Additionally or alternatively, in such embodiments, the local memory of the NIC 832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels.
The communication circuit 830 is communicatively coupled to an optical data connector 834. The optical data connector 834 is configured to mate with a corresponding optical data connector of the rack 240 when the compute sled 800 is mounted in the rack 240. Illustratively, the optical data connector 834 includes a plurality of optical fibers which lead from a mating surface of the optical data connector 834 to an optical transceiver 836. The optical transceiver 836 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of the optical data connector 834 in the illustrative embodiment, the optical transceiver 836 may form a portion of the communication circuit 830 in other embodiments.
In some embodiments, the compute sled 800 may also include an expansion connector 840. In such embodiments, the expansion connector 840 is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to the compute sled 800. The additional physical resources may be used, for example, by the processors 820 during operation of the compute sled 800. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-less circuit board substrate 602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.
Referring now to
As discussed above, the individual processors 820 and communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. In the illustrative embodiment, the processors 820 and communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those physical resources are linearly in-line with others along the direction of the airflow path 608. It should be appreciated that, although the optical data connector 834 is in-line with the communication circuit 830, the optical data connector 834 produces no or nominal heat during operation.
The memory devices 720 of the compute sled 800 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the processors 820 located on the top side 650 via the I/O subsystem 622. Because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the processors 820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Of course, each processor 820 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments. Alternatively, in other embodiments, each processor 820 may be communicatively coupled to each memory device 720. In some embodiments, the memory devices 720 may be mounted to one or more memory mezzanines on the bottom side of the chassis-less circuit board substrate 602 and may interconnect with a corresponding processor 820 through a ball-grid array.
Each of the processors 820 includes a heatsink 850 secured thereto. Due to the mounting of the memory devices 720 to the bottom side 750 of the chassis-less circuit board substrate 602 (as well as the vertical spacing of the sleds 400 in the corresponding rack 240), the top side 650 of the chassis-less circuit board substrate 602 includes additional “free” area or space that facilitates the use of heatsinks 850 having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602, none of the processor heatsinks 850 include cooling fans attached thereto. That is, each of the heatsinks 850 is embodied as a fan-less heatsinks.
Referring now to
In the illustrative accelerator sled 1000, the physical resources 620 are embodied as accelerator circuits 1020. Although only two accelerator circuits 1020 are shown in
In some embodiments, the accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042. Similar to the resource-to-resource interconnect 624 of the sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the accelerator-to-accelerator interconnect 1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, the accelerator circuits 1020 may be daisy-chained with a primary accelerator circuit 1020 connected to the NIC 832 and memory 720 through the I/O subsystem 622 and a secondary accelerator circuit 1020 connected to the NIC 832 and memory 720 through a primary accelerator circuit 1020.
Referring now to
Referring now to
In the illustrative storage sled 1200, the physical resources 620 are embodied as storage controllers 1220. Although only two storage controllers 1220 are shown in
In some embodiments, the storage sled 1200 may also include a controller-to-controller interconnect 1242. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
Referring now to
The storage cage 1252 illustratively includes sixteen mounting slots 1256 and is capable of mounting and storing sixteen solid state drives 1254. Of course, the storage cage 1252 may be configured to store additional or fewer solid state drives 1254 in other embodiments. Additionally, in the illustrative embodiment, the solid state drivers are mounted vertically in the storage cage 1252, but may be mounted in the storage cage 1252 in a different orientation in other embodiments. Each solid state drive 1254 may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives 1254 may include volatile and non-volatile memory devices discussed above.
As shown in
As discussed above, the individual storage controllers 1220 and the communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. For example, the storage controllers 1220 and the communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those electrical components are linearly in-line with other along the direction of the airflow path 608.
The memory devices 720 of the storage sled 1200 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the storage controllers 1220 located on the top side 650 via the I/O subsystem 622. Again, because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the storage controllers 1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Each of the storage controllers 1220 includes a heatsink 1270 secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602 of the storage sled 1200, none of the heatsinks 1270 include cooling fans attached thereto. That is, each of the heatsinks 1270 is embodied as a fan-less heatsink.
Referring now to
In the illustrative memory sled 1400, the physical resources 620 are embodied as memory controllers 1420. Although only two memory controllers 1420 are shown in
In some embodiments, the memory sled 1400 may also include a controller-to-controller interconnect 1442. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some embodiments, a memory controller 1420 may access, through the controller-to-controller interconnect 1442, memory that is within the memory set 1432 associated with another memory controller 1420. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled 1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, the memory controllers 1420 may implement a memory interleave (e.g., one memory address is mapped to the memory set 1430, the next memory address is mapped to the memory set 1432, and the third address is mapped to the memory set 1430, etc.). The interleaving may be managed within the memory controllers 1420, or from CPU sockets (e.g., of the compute sled 800) across network links to the memory sets 1430, 1432, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.
Further, in some embodiments, the memory sled 1400 may be connected to one or more other sleds 400 (e.g., in the same rack 240 or an adjacent rack 240) through a waveguide, using the waveguide connector 1480. In the illustrative embodiment, the waveguides are 64 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Rt (i.e., transmit) lanes. Each lane, in the illustrative embodiment, is either 16 Ghz or 32 Ghz. In other embodiments, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets 1430, 1432) to another sled (e.g., a sled 400 in the same rack 240 or an adjacent rack 240 as the memory sled 1400) without adding to the load on the optical data connector 834.
Referring now to
Additionally, in some embodiments, the orchestrator server 1520 may identify trends in the resource utilization of the workload (e.g., the application 1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 1532) and pre-emptively identifying available resources in the data center 100 and allocating them to the managed node 1570 (e.g., within a predefined time period of the associated phase beginning). In some embodiments, the orchestrator server 1520 may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center 100. For example, the orchestrator server 1520 may utilize a model that accounts for the performance of resources on the sleds 400 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, the orchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and the sled 400 on which the resource is located).
In some embodiments, the orchestrator server 1520 may generate a map of heat generation in the data center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the sleds 400 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center 100. Additionally or alternatively, in some embodiments, the orchestrator server 1520 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center 100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. The orchestrator server 1520 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center 100.
To reduce the computational load on the orchestrator server 1520 and the data transfer load on the network, in some embodiments, the orchestrator server 1520 may send self-test information to the sleds 400 to enable each sled 400 to locally (e.g., on the sled 400) determine whether telemetry data generated by the sled 400 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Each sled 400 may then report back a simplified result (e.g., yes or no) to the orchestrator server 1520, which the orchestrator server 1520 may utilize in determining the allocation of resources to managed nodes.
Referring now to
In the illustrative embodiment, the compute sled 1630 executes an application 1638 (e.g., a workload). The accelerator sled 1640 includes multiple accelerator devices 1644, 1646 coupled to a controller 1642, which, in the illustrative embodiment, abstracts away details of the accelerator devices 1644, 1646 and presents the accelerator devices 1644, 1646 as one or more logical devices usable by the compute sled 1630 on an as-requested basis. Further, the controller 1642, in operation, converts between a message format (e.g., a protocol) used between the compute sled 1630 and the accelerator sled 1640 through the network 1612 and a message format used internally for communications between the controller 1642 and the accelerator devices 1644, 1646, such as messages formatted for use with a local bus (e.g., Peripheral Component Interconnect Express (PCIe)).
Referring now to
The compute engine 1702 may be embodied as any type of device or collection of devices capable of performing various compute functions described below. In some embodiments, the compute engine 1702 may be embodied as a single device such as an integrated circuit, an embedded system, a field-programmable gate array (FPGA), a system-on-a-chip (SOC), or other integrated system or device. In the illustrative embodiment, the compute engine 1702 includes or is embodied as a controller 1642 and a memory 1706. The controller 1642 may be embodied as any type of processor capable of performing the functions described herein. For example, the controller 1642 may be embodied as a microcontroller, a single or multi-core processor(s), or other processor or processing/controlling circuit. In some embodiments, the controller 1642 may be embodied as, include, or be coupled to an FPGA, an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein. In the illustrative embodiment, the controller 1642 includes an abstraction logic unit 1708 which may be embodied as any device or circuitry (e.g., a co-processor, an ASIC, etc.) capable of representing the accelerator devices 1716 to other compute devices (e.g., the compute sled 1630) as one or more logical devices (e.g., devices accessible using a network communication protocol, such as TCP/IP, rather than a local bus protocol, such as PCIe) and enabling access to regions of the accelerator devices (e.g., memory regions) through a proxy mode (e.g., intermediating between the compute sled 1630 and the target accelerator device 1720, 1722) and/or a direct access mode (e.g., remote direct memory access).
The memory 1706 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include future generation nonvolatile devices, such as a three dimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.
In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™ memory) may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In some embodiments, all or a portion of the memory 1706 may be integrated into the controller 1642. In operation, the memory 1706 may store various software and data used during operation such as accelerator abstraction data, access policy data, applications, programs, and libraries.
The compute engine 1702 is communicatively coupled to other components of the accelerator sled 1640 via the I/O subsystem 1710, which may be embodied as circuitry and/or components to facilitate input/output operations with the compute engine 1702 (e.g., with the controller 1642 and/or the memory 1706) and other components of the accelerator sled 1640. For example, the I/O subsystem 1710 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem 1710 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with one or more of the controller 1642, the memory 1706, and other components of the accelerator sled 1640, into the compute engine 1702.
The communication circuitry 1712 may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications over the network 1612 between the accelerator sled 1640 and another compute device (e.g., the compute sled 1630, the orchestrator server 1620). The communication circuitry 1712 may be configured to use any one or more communication technology (e.g., wired or wireless communications) and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, etc.) to effect such communication.
The communication circuitry 1712 may include a network interface controller (NIC) 1714 (e.g., as an add-in device), which may also be referred to as a host fabric interface (HFI). The NIC 1714 may be embodied as one or more add-in-boards, daughter cards, network interface cards, controller chips, chipsets, or other devices that may be used by the accelerator sled 1640 to connect with another compute device (e.g., the compute sled 1630, the orchestrator server 1620, etc.). In some embodiments, the NIC 1714 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 1714 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 1714. In such embodiments, the local processor of the NIC 1714 may be capable of performing one or more of the functions of the compute engine 1702 described herein. Additionally or alternatively, in such embodiments, the local memory of the NIC 1714 may be integrated into one or more components of the accelerator sled 1640 at the board level, socket level, chip level, and/or other levels.
The accelerator devices 1716, similar to the accelerator devices 1644, 1646, of
The accelerator sled 1640 may also include one or more data storage devices 1718, which may be embodied as any type of devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. Each data storage device 1718 may include a system partition that stores data and firmware code for the data storage device 1718. Each data storage device 1718 may also include one or more operating system partitions that store data files and executables for operating systems.
The orchestrator server 1620, the compute sled 1630, and the client device 1614 may have components similar to those described in
As described above, the orchestrator server 1620, the sleds 1630, 1640, and the client device 1614 are illustratively in communication via the network 1612, which may be embodied as any type of wired or wireless communication network, including global networks (e.g., the Internet), local area networks (LANs) or wide area networks (WANs), cellular networks (e.g., Global System for Mobile Communications (GSM), 3G, Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), etc.), digital subscriber line (DSL) networks, cable networks (e.g., coaxial networks, fiber networks, etc.), or any combination thereof.
Referring now to
In the illustrative environment 1800, the network communicator 1820, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from the accelerator sled 1640, respectively. To do so, the network communicator 1820 is configured to receive and process data packets from one system or computing device (e.g., the compute sled 1630, the orchestrator server 1620, etc.) and to prepare and send data packets to a computing device or system (e.g., the compute sled 1630, the orchestrator server 1620, etc.). Accordingly, in some embodiments, at least a portion of the functionality of the network communicator 1820 may be performed by the communication circuitry 1712, and, in the illustrative embodiment, by the NIC 1714.
The access manager 1830, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to identify the accelerator devices 1716 present on the accelerator sled 1630, produce the accelerator abstraction data 1802 to represent the accelerator devices 1716 as one or more logical devices to any remote compute devices (e.g., the compute sled 1630), and enable access to memory regions of the accelerator devices 1716 through a proxy mode or a direct access mode. To do so, in the illustrative embodiment, the access manager 1830 includes an accelerator device identifier 1832, a proxy access manager 1834, and a direct access manager 1836.
The accelerator device identifier 1832, in the illustrative embodiment, is configured to identify the accelerator devices 1716, including their attributes (e.g., accelerator device types, number of FPGA slots, memory regions) and available capacity, and produce the accelerator abstraction data 1802 representing the accelerator devices 1716 as one or more logical devices for use by a remote compute device (e.g., the compute sled 1630). In the illustrative embodiment, the accelerator device identifier 1832 provides, in the accelerator abstraction data 1802, an indication of an access mode associated with each identified region of each accelerator device. For example, the accelerator device identifier 1832 may enable only a proxy mode for regions of memory (e.g., administrative command register regions) that could present a security risk to the system 1610, could damage the accelerator sled 1640, or could interrupt operations of the accelerator sled 1640 that are being performed on behalf of other customers (e.g., on behalf of applications being executed on the compute sled 1630 or another sled (not shown)) and may enable direct access for other regions of memory (e.g., user command register regions, memory regions reserved for bit streams, input parameters, output data, etc.). The proxy access manager 1834, in the illustrative embodiment, is configured to receive requests from the remote compute device (e.g., the compute sled 1630), determine whether operations (e.g., commands) associated with the requests are allowed or disallowed (e.g., as a function of the access policy data 1804), and pass allowed requests to the corresponding accelerator devices 1716. The direct access manager 1836, by contrast, is configured to provide direct access (e.g., direct read or write access) to the memory regions of the corresponding accelerator devices 1716.
It should be appreciated that each of the accelerator device identifier 1832, the proxy access manager 1834, and the direct access manager 1836 may be separately embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof. For example, the accelerator device identifier 1832 may be embodied as a hardware component, while the proxy access manager 1834 and the direct access manager 1836 are embodied as virtualized hardware components or as some other combination of hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof.
Referring now to
In block 1914, the accelerator sled 1640, in the illustrative embodiment, identifies regions of the memory 1734, 1744, that are available for access by a remote compute device (e.g., the compute sled 1630). In doing so, the accelerator sled 1640 identifies random access memory regions, as indicated in block 1916, identifies user command register regions, as indicated in block 1918, and identifies administrative command register regions, as indicated in block 1920, such as by querying each accelerator device 1716 for address ranges associated with the regions. As described in more detail herein, the accelerator sled 1640 may associate each type of memory region with a corresponding access mode (e.g., proxy or direct) to be used by a remote compute device (e.g., the compute sled 1630). In block 1922, the accelerator sled 1640 may further identify the available capacity of each of the accelerator devices 1716 (e.g., a number of slots that have not been allocated to the execution a function on behalf of a remote compute device, a percentage of total processing capacity still available, etc.).
Subsequently, in block 1924, the accelerator sled 1640 determines whether to provide acceleration for a compute device (e.g., the compute sled 1630). For example, the accelerator sled 1640 may receive a request from the compute sled 1630 for data indicative of the available acceleration capacity on the accelerator sled 1640 in preparation to request acceleration of a particular function. In response to a determination that the accelerator sled 1640 has not been requested to provide acceleration for a compute device, the method 1900 loops back to block 1902 to continue to monitor the attributes and available capacity of the accelerator devices 1716 on the accelerator sled 1640. Otherwise, the method 1900 advances to block 1926 of
Referring now to
Referring now to
In block 1960, the accelerator sled 1640 compares the parameters of the request to the allowed access mode (e.g., the access mode indicated in block 1944) associated with the memory region to be accessed. Afterwards, in block 1962, the accelerator sled 1640 determines a subsequent course of action based on whether the compute sled 1630 requested an access mode that is allowed for the corresponding memory region. If not, the method 1900 advances to block 1964, in which the accelerator sled 1640 returns an error message indicative of an incorrect access mode for the memory region, and subsequently loops back to block 1950 of
Referring now to
Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
Example 1 includes an accelerator sled comprising an accelerator device; a controller connected to the accelerator device, wherein the controller is to (i) provide, to a compute sled, accelerator abstraction data, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and defines an access mode usable to access each corresponding memory region, (ii) receive, from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode, (iii) convert the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation, and (iv) perform, in response to the request, the operation on the identified memory region of the accelerator device with the corresponding access mode.
Example 2 includes the subject matter of Example 1, and wherein to perform the operation on the identified memory region comprises to perform the operation in a proxy mode.
Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to perform the operation in a proxy mode comprises to compare the requested operation to policy data indicative of whether one or more operations are allowed or disallowed; and perform, in response to a determination that the requested operation is allowed, the requested operation on the identified memory region of the accelerator device.
Example 4 includes the subject matter of any of Examples 1-3, and wherein to perform the requested operation comprises to perform the requested operation on an administrative command register.
Example 5 includes the subject matter of any of Examples 1-4, and wherein to perform the requested operation comprises to reprogram the accelerator device or reset the accelerator device.
Example 6 includes the subject matter of any of Examples 1-5, and wherein to perform the operation on the identified memory region of the accelerator device comprises to perform a direct access operation.
Example 7 includes the subject matter of any of Examples 1-6, and wherein to perform the direct access operation comprises to enable the compute sled to write data to the identified memory region of the accelerator device.
Example 8 includes the subject matter of any of Examples 1-7, and wherein to perform the direct access operation comprises to enable the compute sled to read data from the identified memory region of the accelerator device.
Example 9 includes the subject matter of any of Examples 1-8, and wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and wherein to provide the accelerator abstraction data comprises to provide accelerator abstraction data that represents the plurality of accelerator devices as a single logical device.
Example 10 includes the subject matter of any of Examples 1-9, and wherein to provide the accelerator abstraction data comprises to provide accelerator abstraction data that represents the accelerator device as multiple logical devices.
Example 11 includes the subject matter of any of Examples 1-10, and wherein the accelerator device is a field programmable gate array with multiple slots and to provide the accelerator abstraction data that represents the accelerator device as multiple logical devices comprises to provide accelerator abstraction data that represents each slot as a different logical device.
Example 12 includes the subject matter of any of Examples 1-11, and wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled and the controller is further to identify the accelerator devices present on the sled and the memory regions of each accelerator device that are accessible by the compute sled.
Example 13 includes the subject matter of any of Examples 1-12, and wherein to identify the regions of each accelerator device that are accessible by the compute sled comprises to identify one or more of a random access memory region, a user command register region, or an administrative command register region.
Example 14 includes a method comprising providing, by an accelerator sled that includes an accelerator device connected to a controller, accelerator abstraction data to a compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and defines an access mode usable to access each corresponding memory region; receiving, by the accelerator sled and from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode; converting, with the controller, the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; and performing, by the accelerator sled and in response to the request, the operation on the identified memory region of the accelerator device with the corresponding access mode.
Example 15 includes the subject matter of Example 14, and wherein performing the operation on the identified memory region comprises performing the operation in a proxy mode.
Example 16 includes the subject matter of any of Examples 14 and 15, and wherein performing the operation in a proxy mode comprises comparing the requested operation to policy data indicative of whether one or more operations are allowed or disallowed; and performing, in response to a determination that the requested operation is allowed, the requested operation on the identified memory region of the accelerator device.
Example 17 includes the subject matter of any of Examples 14-16, and wherein performing the requested operation comprises performing the requested operation on an administrative command register.
Example 18 includes the subject matter of any of Examples 14-17, and wherein performing the requested operation comprises reprogramming the accelerator device or resetting the accelerator device.
Example 19 includes the subject matter of any of Examples 14-18, and wherein performing the operation on the identified memory region of the accelerator device comprises performing a direct access operation.
Example 20 includes the subject matter of any of Examples 14-19, and wherein performing the direct access operation comprises enabling the compute sled to write data to the identified memory region of the accelerator device.
Example 21 includes the subject matter of any of Examples 14-20, and wherein performing the direct access operation comprises enabling the compute sled to read data from the identified memory region of the accelerator device.
Example 22 includes the subject matter of any of Examples 14-21, and wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and wherein providing the accelerator abstraction data comprises providing accelerator abstraction data that represents the plurality of accelerator devices as a single logical device.
Example 23 includes the subject matter of any of Examples 14-22, and wherein providing the accelerator abstraction data comprises providing accelerator abstraction data that represents the accelerator device as multiple logical devices.
Example 24 includes the subject matter of any of Examples 14-23, and wherein the accelerator device is a field programmable gate array with multiple slots and wherein providing the accelerator abstraction data that represents the accelerator device as multiple logical devices comprises providing accelerator abstraction data that represents each slot as a different logical device.
Example 25 includes the subject matter of any of Examples 14-24, and wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled, the method further comprising identifying, by the accelerator sled, the accelerator devices present on the accelerator sled and the memory regions of each accelerator device that are accessible by the compute sled.
Example 26 includes the subject matter of any of Examples 14-25, and wherein identifying the regions of each accelerator device that are accessible by the compute sled comprises identifying one or more of a random access memory region, a user command register region, or an administrative command register region.
Example 27 includes an accelerator sled comprising means for performing the method of any of Examples 14-26.
Example 28 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause an accelerator sled to perform the method of any of Examples 14-26.
Example 29 includes an accelerator sled comprising a compute engine to perform the method of any of Examples 14-26.
Example 30 includes an accelerator sled comprising an accelerator device; access manager circuitry to provide, to a compute sled, accelerator abstraction data, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and defines an access mode usable to access each corresponding memory region; and network communicator circuitry to receive, from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode, wherein the access manager circuitry is further to convert the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; perform, in response to the request, the operation on the identified memory region of the accelerator device with the corresponding access mode.
Example 31 includes the subject matter of Example 30, and wherein to perform the operation on the identified memory region comprises to perform the operation in a proxy mode.
Example 32 includes the subject matter of any of Examples 30 and 31, and wherein to perform the operation in a proxy mode comprises to compare the requested operation to policy data indicative of whether one or more operations are allowed or disallowed; and perform, in response to a determination that the requested operation is allowed, the requested operation on the identified memory region of the accelerator device.
Example 33 includes the subject matter of any of Examples 30-32, and wherein to perform the requested operation comprises to perform the requested operation on an administrative command register.
Example 34 includes the subject matter of any of Examples 30-33, and wherein to perform the requested operation comprises to reprogram the accelerator device or reset the accelerator device.
Example 35 includes the subject matter of any of Examples 30-34, and wherein to perform the operation on the identified memory region of the accelerator device comprises to perform a direct access operation.
Example 36 includes the subject matter of any of Examples 30-35, and wherein to perform the direct access operation comprises to enable the compute sled to write data to the identified memory region of the accelerator device.
Example 37 includes the subject matter of any of Examples 30-36, and wherein to perform the direct access operation comprises to enable the compute sled to read data from the identified memory region of the accelerator device.
Example 38 includes the subject matter of any of Examples 30-37, and wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and wherein to provide the accelerator abstraction data comprises to provide accelerator abstraction data that represents the plurality of accelerator devices as a single logical device.
Example 39 includes the subject matter of any of Examples 30-38, and wherein to provide the accelerator abstraction data comprises to provide accelerator abstraction data that represents the accelerator device as multiple logical devices.
Example 40 includes the subject matter of any of Examples 30-39, and wherein the accelerator device is a field programmable gate array with multiple slots and to provide the accelerator abstraction data that represents the accelerator device as multiple logical devices comprises to provide accelerator abstraction data that represents each slot as a different logical device.
Example 41 includes the subject matter of any of Examples 30-40, and wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled and the access manager circuitry is further to identify the accelerator devices present on the sled and the memory regions of each accelerator device that are accessible by the compute sled.
Example 42 includes the subject matter of any of Examples 30-41, and wherein to identify the regions of each accelerator device that are accessible by the compute sled comprises to identify one or more of a random access memory region, a user command register region, or an administrative command register region.
Example 43 includes an accelerator sled comprising an accelerator device; means for providing, to a compute sled, accelerator abstraction data, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and defines an access mode usable to access each corresponding memory region; circuitry for receiving, from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode; means for converting the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; means for performing, in response to the request, the operation on the identified memory region of the accelerator device with the corresponding access mode.
Example 44 includes the subject matter of Example 43, and wherein the means for performing the operation on the identified memory region comprises means for performing the operation in a proxy mode.
Example 45 includes the subject matter of any of Examples 43 and 44, and wherein the means for performing the operation in a proxy mode comprises means for comparing the requested operation to policy data indicative of whether one or more operations are allowed or disallowed; and means for performing, in response to a determination that the requested operation is allowed, the requested operation on the identified memory region of the accelerator device.
Example 46 includes the subject matter of any of Examples 43-45, and wherein the means for performing the requested operation comprises circuitry for performing the requested operation on an administrative command register.
Example 47 includes the subject matter of any of Examples 43-46, and wherein the means for performing the requested operation comprises circuitry for reprogramming the accelerator device or resetting the accelerator device.
Example 48 includes the subject matter of any of Examples 43-47, and wherein the means for performing the operation on the identified memory region of the accelerator device comprises circuitry for performing a direct access operation.
Example 49 includes the subject matter of any of Examples 43-48, and wherein the means for performing the direct access operation comprises circuitry for enabling the compute sled to write data to the identified memory region of the accelerator device.
Example 50 includes the subject matter of any of Examples 43-49, and wherein the circuitry for performing the direct access operation comprises circuitry for enabling the compute sled to read data from the identified memory region of the accelerator device.
Example 51 includes the subject matter of any of Examples 43-50, and wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and wherein the means for providing the accelerator abstraction data comprises circuitry for providing accelerator abstraction data that represents the plurality of accelerator devices as a single logical device.
Example 52 includes the subject matter of any of Examples 43-51, and wherein the means for providing the accelerator abstraction data comprises circuitry for providing accelerator abstraction data that represents the accelerator device as multiple logical devices.
Example 53 includes the subject matter of any of Examples 43-52, and wherein the accelerator device is a field programmable gate array with multiple slots and the circuitry for providing the accelerator abstraction data that represents the accelerator device as multiple logical devices comprises circuitry for providing accelerator abstraction data that represents each slot as a different logical device.
Example 54 includes the subject matter of any of Examples 43-53, and wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled and the compute device further comprises circuitry for identifying the accelerator devices present on the sled and the memory regions of each accelerator device that are accessible by the compute sled.
Example 55 includes the subject matter of any of Examples 43-54, and wherein the circuitry for identifying the regions of each accelerator device that are accessible by the compute sled comprises circuitry for identifying one or more of a random access memory region, a user command register region, and an administrative command register region.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201741030632 | Aug 2017 | IN | national |
| Number | Date | Country | |
|---|---|---|---|
| 62584401 | Nov 2017 | US |
