TECHNOLOGIES FOR STRUCTURED DATABASE QUERY FOR FINDING UNIQUE ELEMENT VALUES

Abstract

Technologies for determining unique values include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data, and generate, in response to receiving the query configuration data, a bit-map output table based on the query configuration data, generate a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element. Subsequently, the accelerator device is further to set the corresponding bit-map output bit to indicate a presence of the corresponding element and output the bit-map output table indicative of unique elements that are present in the input data.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of Indian Provisional Patent Application No. 201741030632, filed Aug. 30, 2017, and U.S. Provisional Patent Application No. 62/584,401, filed Nov. 10, 2017.

BACKGROUND

Unique values queries are typically performed by processors of a computing device to determine a presence of distinct or unique values in database. The unique values queries are often used to filter large database columns to obtain unique element values that are present in the database. However, processor-based implementations may require consumption of large amounts of power and other resources due to the amount of data that is required to be read into the processors.

Modern computing devices may include general-purpose processor cores as well as a variety of hardware accelerators for performing specialized tasks. Certain computing devices may include one or more accelerators embodied as field-programmable gate arrays (FPGAs), which may include programmable digital logic resources that may be configured by the end user or system integrator.

BRIEF DESCRIPTION OF THE DRAWINGS

The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

FIG. 1 is a diagram of a conceptual overview of a data center in which one or more techniques described herein may be implemented according to various embodiments;

FIG. 2 is a diagram of an example embodiment of a logical configuration of a rack of the data center of FIG. 1;

FIG. 3 is a diagram of an example embodiment of another data center in which one or more techniques described herein may be implemented according to various embodiments;

FIG. 4 is a diagram of another example embodiment of a data center in which one or more techniques described herein may be implemented according to various embodiments;

FIG. 5 is a diagram of a connectivity scheme representative of link-layer connectivity that may be established among various sleds of the data centers of FIGS. 1, 3, and 4;

FIG. 6 is a diagram of a rack architecture that may be representative of an architecture of any particular one of the racks depicted in FIGS. 1-4 according to some embodiments;

FIG. 7 is a diagram of an example embodiment of a sled that may be used with the rack architecture of FIG. 6;

FIG. 8 is a diagram of an example embodiment of a rack architecture to provide support for sleds featuring expansion capabilities;

FIG. 9 is a diagram of an example embodiment of a rack implemented according to the rack architecture of FIG. 8;

FIG. 10 is a diagram of an example embodiment of a sled designed for use in conjunction with the rack of FIG. 9;

FIG. 11 is a diagram of an example embodiment of a data center in which one or more techniques described herein may be implemented according to various embodiments;

FIG. 12 is a simplified block diagram of at least one embodiment of a computing device for determining unique values;

FIG. 13 is a simplified block diagram of at least one embodiment of an environment that may be established by an accelerator of the computing device of FIG. 12; and

FIGS. 14 and 15 are a simplified flow diagram of at least one embodiment of a method for determining unique values that may be executed by the accelerator of FIGS. 12 and 13.

DETAILED DESCRIPTION OF THE DRAWINGS

While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.

References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).

In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.

FIG. 1 illustrates a conceptual overview of a data center 100 that may generally be representative of a data center or other type of computing network in/for which one or more techniques described herein may be implemented according to various embodiments. As shown in FIG. 1, data center 100 may generally contain a plurality of racks, each of which may house computing equipment comprising a respective set of physical resources. In the particular non-limiting example depicted in FIG. 1, data center 100 contains four racks 102A to 102D, which house computing equipment comprising respective sets of physical resources (PCRs) 105A to 105D. According to this example, a collective set of physical resources 106 of data center 100 includes the various sets of physical resources 105A to 105D that are distributed among racks 102A to 102D. Physical resources 106 may include resources of multiple types, such as—for example—processors, co-processors, accelerators, field programmable gate arrays (FPGAs), memory, and storage. The embodiments are not limited to these examples.

The illustrative data center 100 differs from typical data centers in many ways. For example, in the illustrative embodiment, the circuit boards (“sleds”) on which components such as CPUs, memory, and other components are placed for increased thermal performance In particular, in the illustrative embodiment, the sleds are shallower than typical boards. In other words, the sleds are shorter from the front to the back, where cooling fans are located. This decreases the length of the path that air must to travel across the components on the board. Further, the components on the sled are spaced further apart than in typical circuit boards, and the components are arranged to reduce or eliminate shadowing (i.e., one component in the air flow path of another component). In the illustrative embodiment, processing components such as the processors are located on a top side of a sled while near memory, such as DIMMs, are located on a bottom side of the sled. As a result of the enhanced airflow provided by this design, the components may operate at higher frequencies and power levels than in typical systems, thereby increasing performance Furthermore, the sleds are configured to blindly mate with power and data communication cables in each rack 102A, 102B, 102C, 102D, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. Similarly, individual components located on the sleds, such as processors, accelerators, memory, and data storage drives, are configured to be easily upgraded due to their increased spacing from each other. In the illustrative embodiment, the components additionally include hardware attestation features to prove their authenticity.

Furthermore, in the illustrative embodiment, the data center 100 utilizes a single network architecture (“fabric”) that supports multiple other network architectures including Ethernet and Omni-Path. The sleds, in the illustrative embodiment, are coupled to switches via optical fibers, which provide higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high bandwidth, low latency interconnections and network architecture, the data center 100 may, in use, pool resources, such as memory, accelerators (e.g., graphics accelerators, FPGAs, ASICs, etc.), and data storage drives that are physically disaggregated, and provide them to compute resources (e.g., processors) on an as needed basis, enabling the compute resources to access the pooled resources as if they were local. The illustrative data center 100 additionally receives utilization information for the various resources, predicts resource utilization for different types of workloads based on past resource utilization, and dynamically reallocates the resources based on this information.

The racks 102A, 102B, 102C, 102D of the data center 100 may include physical design features that facilitate the automation of a variety of types of maintenance tasks. For example, data center 100 may be implemented using racks that are designed to be robotically-accessed, and to accept and house robotically-manipulatable resource sleds. Furthermore, in the illustrative embodiment, the racks 102A, 102B, 102C, 102D include integrated power sources that receive a greater voltage than is typical for power sources. The increased voltage enables the power sources to provide additional power to the components on each sled, enabling the components to operate at higher than typical frequencies.

FIG. 2 illustrates an exemplary logical configuration of a rack 202 of the data center 100. As shown in FIG. 2, rack 202 may generally house a plurality of sleds, each of which may comprise a respective set of physical resources. In the particular non-limiting example depicted in FIG. 2, rack 202 houses sleds 204-1 to 204-4 comprising respective sets of physical resources 205-1 to 205-4, each of which constitutes a portion of the collective set of physical resources 206 comprised in rack 202. With respect to FIG. 1, if rack 202 is representative of—for example—rack 102A, then physical resources 206 may correspond to the physical resources 105A comprised in rack 102A. In the context of this example, physical resources 105A may thus be made up of the respective sets of physical resources, including physical storage resources 205-1, physical accelerator resources 205-2, physical memory resources 205-3, and physical compute resources 205-4 comprised in the sleds 204-1 to 204-4 of rack 202. The embodiments are not limited to this example. Each sled may contain a pool of each of the various types of physical resources (e.g., compute, memory, accelerator, storage). By having robotically accessible and robotically manipulatable sleds comprising disaggregated resources, each type of resource can be upgraded independently of each other and at their own optimized refresh rate.

FIG. 3 illustrates an example of a data center 300 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. In the particular non-limiting example depicted in FIG. 3, data center 300 comprises racks 302-1 to 302-32. In various embodiments, the racks of data center 300 may be arranged in such fashion as to define and/or accommodate various access pathways. For example, as shown in FIG. 3, the racks of data center 300 may be arranged in such fashion as to define and/or accommodate access pathways 311A, 311B, 311C, and 311D. In some embodiments, the presence of such access pathways may generally enable automated maintenance equipment, such as robotic maintenance equipment, to physically access the computing equipment housed in the various racks of data center 300 and perform automated maintenance tasks (e.g., replace a failed sled, upgrade a sled). In various embodiments, the dimensions of access pathways 311A, 311B, 311C, and 311D, the dimensions of racks 302-1 to 302-32, and/or one or more other aspects of the physical layout of data center 300 may be selected to facilitate such automated operations. The embodiments are not limited in this context.

FIG. 4 illustrates an example of a data center 400 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. As shown in FIG. 4, data center 400 may feature an optical fabric 412. Optical fabric 412 may generally comprise a combination of optical signaling media (such as optical cabling) and optical switching infrastructure via which any particular sled in data center 400 can send signals to (and receive signals from) each of the other sleds in data center 400. The signaling connectivity that optical fabric 412 provides to any given sled may include connectivity both to other sleds in a same rack and sleds in other racks. In the particular non-limiting example depicted in FIG. 4, data center 400 includes four racks 402A to 402D. Racks 402A to 402D house respective pairs of sleds 404A-1 and 404A-2, 404B-1 and 404B-2, 404C-1 and 404C-2, and 404D-1 and 404D-2. Thus, in this example, data center 400 comprises a total of eight sleds. Via optical fabric 412, each such sled may possess signaling connectivity with each of the seven other sleds in data center 400. For example, via optical fabric 412, sled 404A-1 in rack 402A may possess signaling connectivity with sled 404A-2 in rack 402A, as well as the six other sleds 404B-1, 404B-2, 404C-1, 404C-2, 404D-1, and 404D-2 that are distributed among the other racks 402B, 402C, and 402D of data center 400. The embodiments are not limited to this example.

FIG. 5 illustrates an overview of a connectivity scheme 500 that may generally be representative of link-layer connectivity that may be established in some embodiments among the various sleds of a data center, such as any of example data centers 100, 300, and 400 of FIGS. 1, 3, and 4. Connectivity scheme 500 may be implemented using an optical fabric that features a dual-mode optical switching infrastructure 514. Dual-mode optical switching infrastructure 514 may generally comprise a switching infrastructure that is capable of receiving communications according to multiple link-layer protocols via a same unified set of optical signaling media, and properly switching such communications. In various embodiments, dual-mode optical switching infrastructure 514 may be implemented using one or more dual-mode optical switches 515. In various embodiments, dual-mode optical switches 515 may generally comprise high-radix switches. In some embodiments, dual-mode optical switches 515 may comprise multi-ply switches, such as four-ply switches. In various embodiments, dual-mode optical switches 515 may feature integrated silicon photonics that enable them to switch communications with significantly reduced latency in comparison to conventional switching devices. In some embodiments, dual-mode optical switches 515 may constitute leaf switches 530 in a leaf-spine architecture additionally including one or more dual-mode optical spine switches 520.

In various embodiments, dual-mode optical switches may be capable of receiving both Ethernet protocol communications carrying Internet Protocol (IP packets) and communications according to a second, high-performance computing (HPC) link-layer protocol (e.g., Intel's Omni-Path Architecture's, InfiniBand™) via optical signaling media of an optical fabric. As reflected in FIG. 5, with respect to any particular pair of sleds 504A and 504B possessing optical signaling connectivity to the optical fabric, connectivity scheme 500 may thus provide support for link-layer connectivity via both Ethernet links and HPC links. Thus, both Ethernet and HPC communications can be supported by a single high-bandwidth, low-latency switch fabric. The embodiments are not limited to this example.

FIG. 6 illustrates a general overview of a rack architecture 600 that may be representative of an architecture of any particular one of the racks depicted in FIGS. 1 to 4 according to some embodiments. As reflected in FIG. 6, rack architecture 600 may generally feature a plurality of sled spaces into which sleds may be inserted, each of which may be robotically-accessible via a rack access region 601. In the particular non-limiting example depicted in FIG. 6, rack architecture 600 features five sled spaces 603-1 to 603-5. Sled spaces 603-1 to 603-5 feature respective multi-purpose connector modules (MPCMs) 616-1 to 616-5.

FIG. 7 illustrates an example of a sled 704 that may be representative of a sled of such a type. As shown in FIG. 7, sled 704 may comprise a set of physical resources 705, as well as an MPCM 716 designed to couple with a counterpart MPCM when sled 704 is inserted into a sled space such as any of sled spaces 603-1 to 603-5 of FIG. 6. Sled 704 may also feature an expansion connector 717. Expansion connector 717 may generally comprise a socket, slot, or other type of connection element that is capable of accepting one or more types of expansion modules, such as an expansion sled 718. By coupling with a counterpart connector on expansion sled 718, expansion connector 717 may provide physical resources 705 with access to supplemental computing resources 705B residing on expansion sled 718. The embodiments are not limited in this context.

FIG. 8 illustrates an example of a rack architecture 800 that may be representative of a rack architecture that may be implemented in order to provide support for sleds featuring expansion capabilities, such as sled 704 of FIG. 7. In the particular non-limiting example depicted in FIG. 8, rack architecture 800 includes seven sled spaces 803-1 to 803-7, which feature respective MPCMs 816-1 to 816-7. Sled spaces 803-1 to 803-7 include respective primary regions 803-1A to 803-7A and respective expansion regions 803-1B to 803-7B. With respect to each such sled space, when the corresponding MPCM is coupled with a counterpart MPCM of an inserted sled, the primary region may generally constitute a region of the sled space that physically accommodates the inserted sled. The expansion region may generally constitute a region of the sled space that can physically accommodate an expansion module, such as expansion sled 718 of FIG. 7, in the event that the inserted sled is configured with such a module.

FIG. 9 illustrates an example of a rack 902 that may be representative of a rack implemented according to rack architecture 800 of FIG. 8 according to some embodiments. In the particular non-limiting example depicted in FIG. 9, rack 902 features seven sled spaces 903-1 to 903-7, which include respective primary regions 903-1A to 903-7A and respective expansion regions 903-1B to 903-7B. In various embodiments, temperature control in rack 902 may be implemented using an air cooling system. For example, as reflected in FIG. 9, rack 902 may feature a plurality of fans 921 that are generally arranged to provide air cooling within the various sled spaces 903-1 to 903-7. In some embodiments, the height of the sled space is greater than the conventional “1 U” server height. In such embodiments, fans 921 may generally comprise relatively slow, large diameter cooling fans as compared to fans used in conventional rack configurations. Running larger diameter cooling fans at lower speeds may increase fan lifetime relative to smaller diameter cooling fans running at higher speeds while still providing the same amount of cooling. The sleds are physically shallower than conventional rack dimensions. Further, components are arranged on each sled to reduce thermal shadowing (i.e., not arranged serially in the direction of air flow). As a result, the wider, shallower sleds allow for an increase in device performance because the devices can be operated at a higher thermal envelope (e.g., 250 W) due to improved cooling (i.e., no thermal shadowing, more space between devices, more room for larger heat sinks, etc.).

MPCMs 916-1 to 916-7 may be configured to provide inserted sleds with access to power sourced by respective power modules 920-1 to 920-7, each of which may draw power from an external power source 919. In various embodiments, external power source 919 may deliver alternating current (AC) power to rack 902, and power modules 920-1 to 920-7 may be configured to convert such AC power to direct current (DC) power to be sourced to inserted sleds. In some embodiments, for example, power modules 920-1 to 920-7 may be configured to convert 277-volt AC power into 12-volt DC power for provision to inserted sleds via respective MPCMs 916-1 to 916-7. The embodiments are not limited to this example.

MPCMs 916-1 to 916-7 may also be arranged to provide inserted sleds with optical signaling connectivity to a dual-mode optical switching infrastructure 914, which may be the same as—or similar to—dual-mode optical switching infrastructure 514 of FIG. 5. In various embodiments, optical connectors contained in MPCMs 916-1 to 916-7 may be designed to couple with counterpart optical connectors contained in MPCMs of inserted sleds to provide such sleds with optical signaling connectivity to dual-mode optical switching infrastructure 914 via respective lengths of optical cabling 922-1 to 922-7. In some embodiments, each such length of optical cabling may extend from its corresponding MPCM to an optical interconnect loom 923 that is external to the sled spaces of rack 902. In various embodiments, optical interconnect loom 923 may be arranged to pass through a support post or other type of load-bearing element of rack 902. The embodiments are not limited in this context. Because inserted sleds connect to an optical switching infrastructure via MPCMs, the resources typically spent in manually configuring the rack cabling to accommodate a newly inserted sled can be saved.

FIG. 10 illustrates an example of a sled 1004 that may be representative of a sled designed for use in conjunction with rack 902 of FIG. 9 according to some embodiments. Sled 1004 may feature an MPCM 1016 that comprises an optical connector 1016A and a power connector 1016B, and that is designed to couple with a counterpart MPCM of a sled space in conjunction with insertion of MPCM 1016 into that sled space. Coupling MPCM 1016 with such a counterpart MPCM may cause power connector 1016 to couple with a power connector comprised in the counterpart MPCM. This may generally enable physical resources 1005 of sled 1004 to source power from an external source, via power connector 1016 and power transmission media 1024 that conductively couples power connector 1016 to physical resources 1005.

Sled 1004 may also include dual-mode optical network interface circuitry 1026. Dual-mode optical network interface circuitry 1026 may generally comprise circuitry that is capable of communicating over optical signaling media according to each of multiple link-layer protocols supported by dual-mode optical switching infrastructure 914 of FIG. 9. In some embodiments, dual-mode optical network interface circuitry 1026 may be capable both of Ethernet protocol communications and of communications according to a second, high-performance protocol. In various embodiments, dual-mode optical network interface circuitry 1026 may include one or more optical transceiver modules 1027, each of which may be capable of transmitting and receiving optical signals over each of one or more optical channels. The embodiments are not limited in this context.

Coupling MPCM 1016 with a counterpart MPCM of a sled space in a given rack may cause optical connector 1016A to couple with an optical connector comprised in the counterpart MPCM. This may generally establish optical connectivity between optical cabling of the sled and dual-mode optical network interface circuitry 1026, via each of a set of optical channels 1025. Dual-mode optical network interface circuitry 1026 may communicate with the physical resources 1005 of sled 1004 via electrical signaling media 1028. In addition to the dimensions of the sleds and arrangement of components on the sleds to provide improved cooling and enable operation at a relatively higher thermal envelope (e.g., 250 W), as described above with reference to FIG. 9, in some embodiments, a sled may include one or more additional features to facilitate air cooling, such as a heatpipe and/or heat sinks arranged to dissipate heat generated by physical resources 1005. It is worthy of note that although the example sled 1004 depicted in FIG. 10 does not feature an expansion connector, any given sled that features the design elements of sled 1004 may also feature an expansion connector according to some embodiments. The embodiments are not limited in this context.

FIG. 11 illustrates an example of a data center 1100 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. As reflected in FIG. 11, a physical infrastructure management framework 1150A may be implemented to facilitate management of a physical infrastructure 1100A of data center 1100. In various embodiments, one function of physical infrastructure management framework 1150A may be to manage automated maintenance functions within data center 1100, such as the use of robotic maintenance equipment to service computing equipment within physical infrastructure 1100A. In some embodiments, physical infrastructure 1100A may feature an advanced telemetry system that performs telemetry reporting that is sufficiently robust to support remote automated management of physical infrastructure 1100A. In various embodiments, telemetry information provided by such an advanced telemetry system may support features such as failure prediction/prevention capabilities and capacity planning capabilities. In some embodiments, physical infrastructure management framework 1150A may also be configured to manage authentication of physical infrastructure components using hardware attestation techniques. For example, robots may verify the authenticity of components before installation by analyzing information collected from a radio frequency identification (RFID) tag associated with each component to be installed. The embodiments are not limited in this context.

As shown in FIG. 11, the physical infrastructure 1100A of data center 1100 may comprise an optical fabric 1112, which may include a dual-mode optical switching infrastructure 1114. Optical fabric 1112 and dual-mode optical switching infrastructure 1114 may be the same as—or similar to—optical fabric 412 of FIG. 4 and dual-mode optical switching infrastructure 514 of FIG. 5, respectively, and may provide high-bandwidth, low-latency, multi-protocol connectivity among sleds of data center 1100. As discussed above, with reference to FIG. 1, in various embodiments, the availability of such connectivity may make it feasible to disaggregate and dynamically pool resources such as accelerators, memory, and storage. In some embodiments, for example, one or more pooled accelerator sleds 1130 may be included among the physical infrastructure 1100A of data center 1100, each of which may comprise a pool of accelerator resources—such as co-processors and/or FPGAs, for example—that is globally accessible to other sleds via optical fabric 1112 and dual-mode optical switching infrastructure 1114.

In another example, in various embodiments, one or more pooled storage sleds 1132 may be included among the physical infrastructure 1100A of data center 1100, each of which may comprise a pool of storage resources that is globally accessible to other sleds via optical fabric 1112 and dual-mode optical switching infrastructure 1114. In some embodiments, such pooled storage sleds 1132 may comprise pools of solid-state storage devices such as solid-state drives (SSDs). In various embodiments, one or more high-performance processing sleds 1134 may be included among the physical infrastructure 1100A of data center 1100. In some embodiments, high-performance processing sleds 1134 may comprise pools of high-performance processors, as well as cooling features that enhance air cooling to yield a higher thermal envelope of up to 250 W or more. In various embodiments, any given high-performance processing sled 1134 may feature an expansion connector 1117 that can accept a far memory expansion sled, such that the far memory that is locally available to that high-performance processing sled 1134 is disaggregated from the processors and near memory comprised on that sled. In some embodiments, such a high-performance processing sled 1134 may be configured with far memory using an expansion sled that comprises low-latency SSD storage. The optical infrastructure allows for compute resources on one sled to utilize remote accelerator/FPGA, memory, and/or SSD resources that are disaggregated on a sled located on the same rack or any other rack in the data center. The remote resources can be located one switch jump away or two-switch jumps away in the spine-leaf network architecture described above with reference to FIG. 5. The embodiments are not limited in this context.

In various embodiments, one or more layers of abstraction may be applied to the physical resources of physical infrastructure 1100A in order to define a virtual infrastructure, such as a software-defined infrastructure 1100B. In some embodiments, virtual computing resources 1136 of software-defined infrastructure 1100B may be allocated to support the provision of cloud services 1140. In various embodiments, particular sets of virtual computing resources 1136 may be grouped for provision to cloud services 1140 in the form of software-defined infrastructure (SDI) services 1138. Examples of cloud services 1140 may include—without limitation—software as a service (SaaS) services 1142, platform as a service (PaaS) services 1144, and infrastructure as a service (IaaS) services 1146.

In some embodiments, management of software-defined infrastructure 1100B may be conducted using a virtual infrastructure management framework 1150B. In various embodiments, virtual infrastructure management framework 1150B may be designed to implement workload fingerprinting techniques and/or machine-learning techniques in conjunction with managing allocation of virtual computing resources 1136 and/or SDI services 1138 to cloud services 1140. In some embodiments, virtual infrastructure management framework 1150B may use/consult telemetry data in conjunction with performing such resource allocation. In various embodiments, an application/service management framework 1150C may be implemented in order to provide QoS management capabilities for cloud services 1140. The embodiments are not limited in this context.

Referring now to FIG. 12, an illustrative system 1200 for determining unique values, which may be implemented in accordance with the data centers 100, 300, 400, 1100 described above with reference to FIGS. 1, 3, 4, and 11, is shown. The illustrative system 1200 includes a compute device 1202 that includes an accelerator 1204, a memory 1206, one or more processors 1208, and one or more storage devices 1210. In use, as described further below, the accelerator 1204 may filter a database to determine unique values. In the illustrative embodiment, the accelerator 1204 may receive input data, which is a packed array of unsigned integers of column data from the database, to determine unique element values of the input data. To do so, the accelerator 1204 may construct a bit-map output table configured to store bit-map output bits based on query configuration data received from a processor 1208, which includes a number of elements and an element width (N) of the input data and a hash width (K). It should be appreciated that the hash width (K) is less than or equal to the element width (N). Accordingly, the bit-map output table is sized to store 2^K number of bit-map output bits, each bit-map output bit corresponds to a unique element value of the input data or a unique hash value that may be generated from the input data. In the illustrative embodiment, the accelerator 1240 may construct a different type of bit-map output tables on the accelerator 1240 based on the hash width (K). For example, if the hash width (K) is less than 8 bits, the accelerator 1240 may construct a small bit-map output table with multiple write ports (e.g., muxes) to provide multiple writes per cycle. Alternatively, if the hash width (K) is greater than 8 bits, the accelerator 1240 may construct a large bit-map output table. The accelerator 1204 may configure the large bit-map output table to store duplicate copies of the bit-map output bits to support parallel accesses, including parallel writes during input data processing into the large bit-map output table and parallel reads during read out processing of the large bit-map output table.

Subsequently, the accelerator 1204 may generate a write request for each element to access the corresponding bit-map output table to set a bit-map output bit that corresponds to the element value of the corresponding element. To do so, the accelerator 1204 may adjust the element width (N) of the input data by pre-processing the packed bit vector of column data. The pre-processing of the input data may support unique values queries on any bit-width of elements of the database based on a data path width of the accelerator 1240 and may also ensure that a largest number of elements are processed in each cycle. Since the input data is pre-processed and aligned with the bit-map output table, the accelerator 1204 may use a corresponding element value of each element as a write request address to issue the write request to the corresponding bit-map output bit. Alternatively, if the element width (N) is different than the hash width (K), the accelerator 1204 may perform the hash function on each element value to generate a hash value that is to be used as a write request address to access the bit-map output table to set the corresponding bit-map output bit. After multiple passes to process all elements of the input data, the accelerator 1204 may output the bit-map output table that includes 2^K bit-map output bits, where each set bit-map output bit indicates a presence of a corresponding unique element value or hash value. The accelerator 1204 may then transfer the bit-map output table to the memory 1206 of the compute device 1202 for further analysis or processing by one or more processors 1208. By performing the unique values queries on the hardware accelerator 1204 instead of the processor 1208, the system 1200 may increase performance and power efficiency by avoiding moving a large amount of data to the processor(s) 1208 for the set membership queries.

For example, the database stored in the memory 1206 of the compute device 1202 includes a table with a list of names of people, their residency information, and their income. The processor 1208 requests the accelerator 1204 to find how many unique state(s) there are in the database. In response, the accelerator 1204 generates a bit-map output table, which is configured to store bit-map output bits for every possible state of the input data. In other words, the bit-map output table includes 50 bit-map output bits to represent 50 states. Subsequently, the accelerator 1204 receives the residency information column data from the memory 1206, determines the state that each element or people live in, and sets a bit-map output bit that corresponds to each state. For example, if a person lives in Indiana, the accelerator 1204 sets a bit-map output bit of the bit-map output table that corresponds to Indiana to 1. Accordingly, if there are 10 unique states in the database, meaning that all people live in one of those 10 states, the accelerator 1204 outputs the bit-map output table that includes 10 bit-map output bits that have value of 1.

The accelerator 1204 may be embodied as any coprocessor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), a system-on-a-chip (SOC), an application specific integrated circuit (ASIC), functional block, IP core, or other hardware accelerator of the compute device 1202 capable of performing the functions described herein. As discussed above, the accelerator 1204 is configured to determine unique element values from the database. To do so, as shown in FIG. 12, the accelerator 1204 includes a decompressor 1212, an input pre-processing unit 1214, a write request generator unit 1216, and an output processing unit 1218. As discussed above, the accelerator 1204 also includes a definition table 1220 that may be stored in external memory 1222 of the accelerator 1204 and local memory 1224 of the accelerator 1204.

The decompressor 1212 may be embodied as any hardware component(s) or circuitry capable of decompressing the input data. Typically, the input data is compressed column data stored in the memory 1206. As such, the decompressor 1212 may determine whether the input data is compressed data and decompress the compressed input data in response to determining that the input data is compressed.

The input pre-processing unit 1214 may be embodied as any hardware component(s) or circuitry capable of pre-processing the input data to support unique values queries on any bit-width of elements of the database. To do so, the input pre-processing unit 1214 may determine a largest power of 2 elements (i.e., 2^m elements) that is to be processed in each cycle as a function of an element width of the input data and a data path width of the accelerator 1204. The input pre-processing unit 1214 may align the elements of the uncompressed input data (e.g., the packed bit vector of column data) and prepend zero to each element of the input data based on the data path width in order to process the largest power of 2 elements per cycle. For example, if the accelerator 1204 has a 32 bit wide data path, the input pre-processing unit 1214 may process 32 elements for an element width of 1 bit, 16 elements for an element width of 2 bits, 8 elements for element widths 3 or 4 bits, 4 elements for element widths from 5 to 8 bits, and so on.

The write request generator unit 1216 may be embodied as any hardware component(s) or circuitry capable of generating a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element. To do so, the write request generator unit 1216 may generate a write request address for the corresponding element to access a corresponding bit-map output bit of the bit-map output table. Since the input data is pre-processed, the write request generator unit 1216 may extract each element and use the corresponding element value as a write request address to issue a write request to the corresponding bit-map output table. Alternatively, if the hash width (K) is less than the element width (N), the write request generator unit 1216 may compute a K-bit hash value that corresponds to the element value of the corresponding element and use the hash value as a write request address for the corresponding element to access the bit-map output table. It should be appreciated that the hash function may be programmed based on the element width (N) of the input data and the hash width (K) indicated in the query configuration data. For example, the write request generator unit 1216 may extract K bits of the N-bit element by truncating a number of upper and/or lower bits of the N-bit element. In some embodiments, the hash function may be performed prior to pre-processing the input data.

The output processing unit 1218 may be embodied as any hardware component(s) or circuitry capable of outputting the bit-map output table, where each set bit-map output bit of the bit-map output table (e.g., a bit-map output bit that has a value of 1) indicates a presence of a unique element value corresponds to the bit-map output bit. The output processing unit 1218 may be further configured to accumulate the bit-map output bits until a width of the bit-map output bits reaches the data path width to transmit the bit-map output bits to the memory 1206 for further analysis by one or more processors 1208. In some embodiments, the output processing unit 1218 may directly communicate with one or more processors 1208 to transmit the bit-map output table.

The processor 1208 may be embodied as any type of processor capable of performing the functions described herein. For example, the processor 1208 may be embodied as a single or multi-core processor(s), digital signal processor, microcontroller, or other processor or processing/controlling circuit. Similarly, the memory 1206 may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. In operation, the memory 1206 may store various data and software used during operation of the compute device 1202 such operating systems, applications, programs, libraries, and drivers. The memory 1206 is communicatively coupled to the processor 1208 via the input/output (I/O) subsystem (not shown), which may be embodied as circuitry and/or components to facilitate input/output operations with the processor 1208, the accelerator 1204, the memory 1206, the one or more storage devices 1210, and other components of the compute device 1202. For example, the I/O subsystem may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, sensor hubs, firmware devices, communication links (i.e., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.) and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 1208, the memory 1206, and other components of the compute device 1202, on a single integrated circuit chip.

The memory 1206 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.

In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include future generation nonvolatile devices, such as a three dimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.

In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™ memory) may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In some embodiments, all or a portion of the memory 1206 may be integrated into the processor 1208. In operation, the memory 1206 may store various software and data used during operation such as resource utilization data, resource availability data, application programming interface (API) data, applications, programs, and libraries.

The illustrative storage devices 1210 may be embodied as any type of devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. Each storage device 1210 may include a system partition that stores data and firmware code for the storage device 1210. Each storage device 1210 may also include one or more operating system partitions that store data files and executables for operating systems.

Although illustrated in FIG. 12 as a single compute device 1202, it should be understood that in some embodiments the functions of the compute device 1202 may be performed by one or more sleds in a data center. In such embodiments, the accelerator 1204 may be embodied as one or more accelerator sled 204-2 (e.g., physical accelerator resources 205-2), the memory 1206 may be embodied as one or more memory sled 204-3 (e.g., physical memory resources 205-3), one or more processors 1208 may be embodied as one or more compute sled 204-4 (e.g., physical compute resources 205-4), one or more storage devices 1210 may be embodied as one or more storage sleds 204-1 (e.g., physical storage resources 205-1).

Referring now to FIG. 13, in the illustrative embodiment, the accelerator 1204 of the compute device 1202 may establish an environment 1300 during operation. In the illustrative embodiment, the environment 1300 includes a large bit-map output table 1340 and a small bit-map output table 1350. The large bit-map output table 1340 may be embodied as any data indicative of bit-map output bits for elements that have a bit-width greater than a predefined number of bit-width. Whereas, the small bit-map output table 1350 may be embodied as any data indicative of bit-map output bits for elements that have a bit-width smaller than the predefined number of bit-width. As discussed above, each bit-map output bit that is set indicates a presence of unique element value. It should be appreciated that, in the embodiment where the hash width (K) is less than the element width (N), each bit-map output bit that is set indicates a presence of a hash value, which corresponds to a unique element value. Additionally, the illustrative environment 1300 includes an input/output (I/O) communicator 1310, a decompressor 1320, and complex filter 1330. The complex filter 1330 further includes a bit-map table generator 1332, an input data pre-processor 1334, a write request generator 1336, and a bit-map output generator 1338. Each of the components of the environment 1300 may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of the environment 1300 may be embodied as circuitry or a collection of electrical devices (e.g., I/O communicator circuitry 1310, decompressor circuitry 1320, complex filter circuitry 1330, bit-map table generator circuitry 1332, input data pre-processor circuitry 1334, write request generator circuitry 1336, bit-map output generator circuitry 1338, etc.).

In the illustrative environment 1300, the I/O communicator 1310 is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from the accelerator 1204, respectively. To do so, the I/O communicator 1310 is configured to receive and process data from the memory 1206 based on unique values queries received from a processor 1208 of the compute device 1202. The I/O communicator 1310 is further configured to transmit a bit-map output data to the memory 1206. In some embodiments, the accelerator 1204 may receive from or transmit to one or more storage devices 1210. Accordingly, in some embodiments, at least a portion of the functionality of the I/O communicator 1310 may be performed by communication circuitry of the compute device 1202.

The decompressor 1320, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to decompress the input data. The decompressor 1212 is configured to determine whether the input data is compressed data and decompress the compressed input data in response to determining that the input data is compressed.

The complex filter 1330, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to filter the input data to determine unique element values of the input data. To do so, the complex filter 1330 includes the bit-map table generator 1332, the input data pre-processor 1334, the write request generator 1336, and the bit-map output generator 1338.

The bit-map table generator 1332 is configured to generate a bit-map output table. As described above, the bit-map output table is configured to store bit-map output bits, where each bit-map output bit corresponds to a unique element value or hash value of the input data. As such, the bit-map output table has 2^K number of bit-map output bits to represent 2^K unique element values. In the illustrative embodiment, the bit-map table generator 1332 is configured to construct a different type of definition table (e.g., a small or large bit-map output table) on the accelerator 1240 based on the hash width (K). If the bit-map table generator 1332 determines that the hash width (K) is less than a predefined width, the bit-map table generator 1332 constructs a small bit-map output table that has many write ports as necessary to satisfy a target throughput based on the width of the data path of the accelerator 1204. For example, if the hash width (K) is less than 8 bits, the bit-map output bits are stored in a small bit-map output table with multiple write ports to provide multiple writes per cycle. To generate a bit-map output table that supports elements up to 8 bits, the bit-map table generator 1332 implements 256 flip flops to construct a small bit-map output table. In this example, if the width of the data path of the accelerator 1204 is 32 bit, the bit-map table generator 1332 constructs the small bit-map output table with 2 flip flops for 32 write ports of a 1 bit element (e.g., 2:1 multiplexers), 4 flip flops for 16 write ports of a 2 bit element (e.g., 4:1 multiplexers), 16 flip flops for 8 write ports of a 3 or 4 bit element (e.g., 16:1 multiplexers), and remaining flip flops for 4 write ports. Alternatively, if the hash width (K) is greater than 8 bits, the bit-map output bits are stored in a large bit-map output table. The accelerator 1204 may configure the large bit-map output table to store duplicate copies of the bit-map output bits to support parallel accesses. It should be appreciated that, in some embodiments, the accelerator 1204 may also configure the small bit-map output table to store multiple copies of the bit-map output bits to support multiple accesses.

The input data pre-processor 1334 is configured to pre-process the input data to support unique element values queries on any bit-width of elements of the database. To do so, the input data pre-processor 1334 is configured to determine a largest power of 2 elements (i.e., 2^m elements) that is to be processed in each cycle as a function of an element width of the input data and a data path width of the accelerator 1204. The input data pre-processor 1334 is further configured to align the elements of the uncompressed input data (i.e., the packed bit vector of column data) and prepend zero to each element of the input data based on the data path width in order to process the largest power of 2 elements per cycle. For example, if the accelerator 1204 has a 32 bit wide data path, the input data pre-processor 1334 may process 32 elements for element with 1 bit, 16 elements for element width of 2 bits, 8 elements for element widths 3 or 4 bits, or 4 elements for element widths from 5 to 8 bits, and so on.

The write request generator 1336 is configured to generate a write request for each element of the input data to access the corresponding bit-map output table to set a corresponding bit-map output bit of the bit-map output table. To do so, the accelerator 1204 may generate a write request address for the corresponding element to access the bit-map output table. Since the input data is pre-processed and aligned with the bit-map output table, if the element width (N) and the hash width (K) are the same, the accelerator 1204 may extract each element and use the corresponding element value as a write request address to issue a write request to the corresponding bit-map output table. However, if the element width (N) is different than the hash width (K), the accelerator 1204 may extract each element and use a corresponding hash value as a write request address to issue a write request to the corresponding bit-map output table. To do so, the accelerator 1204 is configured to generate a hash value that corresponds to each element value for every element of the input data using a hash function that is configured based the element width (N) and the hash width (N).

The bit-map output generator 1338 is configured to output the bit-map output table that indicates unique element values that are present in the input data. As described above, in some embodiments, the bit-map output table may include duplicate copies of the bit-map output to support parallel accesses by mimicking multiple write ported memory. In such embodiments, the bit-map output generator 1338 may combine the corresponding bits from each copy of the bit-map output by using a logical OR operation to generate the true bit-map output bit of the bit-map output table. It should be appreciated that each bit-map output bit of the bit-map output table that has been set indicates a presence of a unique element value that corresponds to the bit-map output bit. As such, the bit-map output generator 1338 may be configured to determine a total number of unique element values that are present in the input data by adding a number of bit-map output bits that have been set. The bit-map output generator 1338 may be further configured to accumulate the bit-map output bit data until a width of the bit-map output reaches the data path width and transmit the bit-map output bit data to the memory 1206 for further analysis or processing by one or more processors 1208. In some embodiments, the bit-map output generator 1338 may directly communicate with one or more processors 1208 to transmit the bit-map output bit table.

Referring now to FIGS. 14 and 15, in use, the accelerator 1204 of the compute device 1202 may execute a method 1400 for determining unique element values. The method 1400 begins with block 1402, in which the accelerator 1204 imports input data from the memory 1206 of the compute device 1202. Typically, the input data is compressed data stored in the memory 1206. As such, the accelerator 1204 decompresses the compressed input data as indicated in block 1404.

In block 1406, the accelerator 1204 receives query configuration data from a requesting processor 1208 of the compute device 1202. For example, the accelerator 1204 may receive from the processor 1208 a pointer to query configuration data in the memory 1206. However, it should be appreciated that, in some embodiments, the query configuration data may be received from other components of the compute device 1202. As described above, the query configuration data may include a number of elements and an element width (N) of the input data and a hash width (K). Accordingly, in block 1408, the accelerator 1204 determines a number elements and an element width (N) of the input data. In some embodiments, in block 1410 the accelerator 1204 may determine a hash width (K) if the element width (N) of the input data is different from the hash width (K). Additionally, in block 1412, the accelerator 1204 determines a number of elements to be processed per cycle based on the element width (N) and a data path width of the accelerator 1204.

Subsequently, the accelerator 1204 constructs a bit-map output table that is configured to store bit-map output bits. The bit-map output bits represent all possible element values of the input data, such that each bit-map output bit represents a unique element value of the input data. Accordingly, the bit-map output table includes two to the hash width (K) power number of bit-map output bits. For example, the bit-map output bits for a 8-bit hash width includes 2⁸ or 256 bits, the bit-map output bits for a 32-bit hash width includes 2³² bits or 512 MB, and so on. It should be appreciated that, in the illustrative embodiment, all bit-map output bits stored in the bit-map output table are initially cleared (e.g., a default value of 0).

As described above, the accelerator 1240 configures a different bit-map output table on the accelerator 1240 based on the hash width (K). To do so, in block 1414, the accelerator 1204 determines whether the hash width (K) is greater than a predefined width. If the accelerator 1204 determines that the hash width (K) is smaller than the predefined threshold of element width, the method 1400 advances to block 1416. In block 1416, the accelerator 1204 constructs a small bit-map output table to store the bit-map output bits. The small bit-map output table is to support multiple write ports to provide multiple writes per cycle as indicated in block 1418. For example, if the element width is less than 8 bits, the bit-map output bits are stored in a small bit-map output table with multiple write ports to provide multiple writes per cycle.

Alternatively, if the accelerator 1204 determines that the hash width (K) is greater than the predefined threshold width in block 1414, the method 1400 advances to block 1420. In block 1420, the accelerator 1204 constructs a large bit-map output table to store the bit-map output bits. Although multiple write ports may be implemented to construct a small bit-map output table for processing data having a small element width, implementing multiple write ports for a large data having a large element width may be impractical and costly. As such, the accelerator 1204 may store duplicate copies of the bit-map output bits to support parallel accesses per cycle as indicated in block 1422. To do so, the bit-map output bits are stored in different banks such that each membership bit vector in each bank is accessed simultaneously, thereby supporting parallel accesses. For example, if the width of each element is greater than 8 bits, the accelerator 1204 may configure a large bit-map output table to store duplicate copies of the bit-map output bits to support parallel accesses.

Subsequent to constructing the bit-map output table, in block 1424, the accelerator 1204 determines whether the element width (N) equals to the hash width (K). If the accelerator 1204 determines that the element width (N) and the hash width (K) are the same, the method 1400 skips ahead to block 1428 shown in FIG. 15. If, however, the accelerator 1204 determines that the element width (N) is different than the hash width (K), the method 1400 advances to block 1426, in which the accelerator 1204 programs a hash function that is configured to generate a K-bit hash value from a N-bit element value for every elements of the input data.

Subsequently, in block 1428 shown in FIG. 15, the accelerator 1204 pre-processes the input data to prepare the elements of the input data for the unique element value function. To do so, the accelerator 1204 may align the elements of the input data (i.e., the packed array of unsigned integers of column data) based on the number of elements that is to be processed in each cycle as indicated in block 1430. As described above, the number of elements that is to be processed in each cycle is determined based on the element width (N) of the input data and a data path width of the accelerator 1204. Additionally, in block 1432 the accelerator 1204 may prepend zeros to each element of the input data based on the data path width in order to process a largest power of 2 elements per cycle (i.e., largest 2^m elements/cycle). For example, if the accelerator 1204 has a 32 bit wide data path, the accelerator 1204 may process 32 elements for element with 1 bit, 16 elements for element width of 2 bits, 8 elements for element widths 3 or 4 bits, or 4 elements for element widths from 5 to 8 bits, and so on.

In block 1434, the accelerator 1204 generates a write request for each element of the input data to access the corresponding bit-map output table to set a corresponding bit-map output bit of the bit-map output table. To do so, the accelerator 1204 may generate a write request address for the corresponding element to access the bit-map output table. Since the input data is pre-processed and aligned with the bit-map output table, if the element width (N) and the hash width (K) are the same, the accelerator 1204 may extract each element and use the corresponding element value as a write request address to issue a write request to the corresponding bit-map output table as indicated in block 1436. However, if the element width (N) is different than the hash width (K), the accelerator 1204 may use a corresponding hash value as a write request address to issue a write request to the corresponding bit-map output table as indicated in block 1438. To do so, in block 1440, the accelerator 1204 generates a hash value that corresponds to each element value for every element of the input data. In block 1442, the write request is transmitted to the corresponding bit-map output table. In response to generating the write requests for each element of the input data, in block 1444, the accelerator 1204 accesses the corresponding bit-map output table to set the corresponding bit-map output bits based on the write requests.

Subsequently, in block 1446, the accelerator 1204 output the bit-map output table that includes the bit-map output bits indicating unique element values that are present in the input data. As discussed above, each output bit of the bit-map output table that has been set corresponds to a presence of a unique element value. As such, in some embodiments, a total number of unique elements present in the input data may be determined by generating a population count by adding a number of bit-map output bits that have been set as indicated in block 1448. In some embodiments, in block 1450, the accelerator 1204 may accumulate the bit-map output table data until a width of the bit-map output table data reaches the data path width of the accelerator and transmit the bit-map output table to the memory 1206 for further processing by one or more processors 1208. In some embodiments, the bit-map output table may be directly transmitted to the processor 1208.

EXAMPLES

Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.

Example 1 includes a compute device for determining unique values, the compute device comprising one or more accelerator devices, each accelerator device is to receive input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data; generate, in response to receiving the query configuration data, a bit-map output table based on the query configuration data; generate a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element; set the corresponding bit-map output bit to indicate a presence of the corresponding element in response to generation of the write request; and output the bit-map output table indicative of unique elements that are present in the input data in response to setting of the corresponding bit-map output bit.

Example 2 includes the subject matter of Example 1, and wherein the each accelerator is further to decompress, in response to importation of the input data, the input data; and pre-process, in response to decompression of the input data, the decompressed input data.

Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to pre-process the decompressed input data comprises to align elements of the packed bit vector of the input data based on a width of elements of the decompressed input data and prepend zeroes to match a data path width.

Example 4 includes the subject matter of any of Examples 1-3, and wherein the query configuration data further includes a hash width.

Example 5 includes the subject matter of any of Examples 1-4, and wherein the each accelerator is further to determine whether the element width is greater than the hash width; program, in response to a determination that the element width is greater than the hash width, a hash function to generate a hash value that corresponds to the element value of the corresponding element; and generate, in response to programming of the hash function, a hash value for each element value by performing the hash function on the input data.

Example 6 includes the subject matter of any of Examples 1-5, and wherein to generate the write request comprises to generate a write request address based on a hash value of the corresponding element.

Example 7 includes the subject matter of any of Examples 1-6, and wherein to generate the write request comprises to determine a write request address based on an element value of the corresponding element.

Example 8 includes the subject matter of any of Examples 1-7, and wherein to generate the bit-map output table based on the query configuration data comprises to determine whether the element width of the input data exceeds a threshold; construct, in response to a determination that the element width exceeds the threshold, a large bit-map output table to store the bit-map output bits; and construct, in response to a determination that the element width does not exceed the threshold, a small bit-map output table to store the bit-map output bits.

Example 9 includes the subject matter of any of Examples 1-8, and wherein the large bit-map output table supports parallel accesses by duplication of the bit-map output table and the small-sized table supports multiple accesses via multiple write ports and duplication of the bit-map output table.

Example 10 includes the subject matter of any of Examples 1-9, and wherein to set the corresponding bit-map output bit comprises to determine whether the element width exceeds a threshold; access, in response to a determination that the element width exceeds the threshold, the large bit-map output table to set the corresponding bit-map output bit; and access, in response to a determination that the element width does not exceed the threshold, the small bit-map output table to set the corresponding bit-map output bit.

Example 11 includes the subject matter of any of Examples 1-10, and wherein to output the bit-map output table comprises to generate a population count indicating a number of unique elements based on the bit-map output table.

Example 12 includes the subject matter of any of Examples 1-11, and wherein the each accelerator is further to accumulate the bit-map output table until a width of the bit-map output table matches a data path width.

Example 13 includes a method for determining unique values by a compute device, the method comprising receiving, by an accelerator of the compute device, input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data; generating, in response to receiving the query configuration data and by the accelerator, a bit-map output table based on the query configuration data; generating, by the accelerator, a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element; setting, by the accelerator, the corresponding bit-map output bit to indicate a presence of the corresponding element in response to generating the write request; and outputting, by the accelerator, the bit-map output table indicative of unique elements that are present in the input data in response to setting the corresponding bit-map output bit.

Example 14 includes the subject matter of Example 13, and further including decompressing, in response to importing the input data and by the accelerator, the input data; and pre-processing, in response to decompressing the input data and by the accelerator, the decompressed input data.

Example 15 includes the subject matter of any of Examples 13 and 14, and wherein pre-processing the decompressed input data comprises aligning, by the accelerator, elements of the packed bit vector of the input data based on a width of elements of the decompressed input data and prepending, by the accelerator, zeroes to match a data path width.

Example 16 includes the subject matter of any of Examples 13-15, and wherein the query configuration data further includes a hash width.

Example 17 includes the subject matter of any of Examples 13-16, and further including determining, by the accelerator, whether the element width is greater than the hash width; programming, in response to a determination that the element width is greater than the hash width and by the accelerator, a hash function to generate a hash value that corresponds to the element value of the corresponding element; and generating, in response to programming the hash function and by the accelerator, a hash value for each element value by performing the hash function on the input data.

Example 18 includes the subject matter of any of Examples 13-17, and wherein generating the write comprises determining, by the accelerator, a write request address based on a hash value of the corresponding element.

Example 19 includes the subject matter of any of Examples 13-18, and wherein generating the write comprises determining, by the accelerator, a write request address based on an element value of the corresponding element.

Example 20 includes the subject matter of any of Examples 13-19, and wherein generating the bit-map output table based on the query configuration data comprises determining, by the accelerator, whether the element width of the input data exceeds a threshold; constructing, in response to a determination that the element width exceeds the threshold, a large bit-map output table to store the bit-map output bits; and constructing, in response to a determination that the element width does not exceed the threshold, a small bit-map output table to store the bit-map output bits.

Example 21 includes the subject matter of any of Examples 13-20, and wherein the large bit-map output table supports parallel accesses by duplicating the bit-map output table and the small-sized table supports multiple accesses via multiple write ports and duplicating the bit-map output table.

Example 22 includes the subject matter of any of Examples 13-21, and wherein setting the corresponding bit-map output bit comprises determining, by the accelerator, whether the element width exceeds a threshold; accessing, in response to a determination that the element width exceeds the threshold and by the accelerator, the large bit-map output table to set the corresponding bit-map output bit; and accessing, in response to a determination that the element width does not exceed the threshold and by the accelerator, the small bit-map output table to set the corresponding bit-map output bit.

Example 23 includes the subject matter of any of Examples 13-22, and wherein outputting the bit-map output table comprises generating, by the accelerator, a population count indicating a number of unique elements based on the bit-map output table.

Example 24 includes the subject matter of any of Examples 13-23, and further including accumulating, by the accelerator, the bit-map output table until a width of the bit-map output table matches a data path width.

Example 25 includes a compute device comprising means for performing the method of any of Examples 13-24.

Example 26 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute device to perform the method of any of Examples 13-24.

Example 27 includes a compute device comprising a compute engine to perform the method of any of Examples 13-24.

Example 28 includes a compute device for determining unique values, the compute device comprising one or more accelerator devices, each accelerator device comprising means for receiving input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data; means for generating, in response to receiving the query configuration data, a bit-map output table based on the query configuration data; means for generating a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element; means for setting the corresponding bit-map output bit to indicate a presence of the corresponding element in response to generating the write request; and means for outputting the bit-map output table indicative of unique elements that are present in the input data in response to setting the corresponding bit-map output bit.

Example 29 includes the subject matter of Example 28, and wherein the each accelerator device further comprises means for decompressing, in response to importing the input data, the input data; and means for pre-processing, in response to decompressing the input data, the decompressed input data.

Example 30 includes the subject matter of any of Examples 28 and 29, and wherein the means for pre-processing the decompressed input data comprises means for aligning elements of the packed bit vector of the input data based on a width of elements of the decompressed input data and means for prepending zeroes to match a data path width.

Example 31 includes the subject matter of any of Examples 28-30, and wherein the query configuration data further includes a hash width.

Example 32 includes the subject matter of any of Examples 28-31, and wherein the each accelerator further comprises means for determining whether the element width is greater than the hash width; means for programming, in response to a determination that the element width is greater than the hash width, a hash function to generate a hash value that corresponds to the element value of the corresponding element; and means for generating, in response to programming the hash function, a hash value for each element value by performing the hash function on the input data.

Example 33 includes the subject matter of any of Examples 28-32, and wherein the means for generating the write comprises means for determining a write request address based on a hash value of the corresponding element.

Example 34 includes the subject matter of any of Examples 28-33, and wherein the means for generating the write comprises means for determining a write request address based on an element value of the corresponding element.

Example 35 includes the subject matter of any of Examples 28-34, and wherein the means for generating the bit-map output table based on the query configuration data comprises means for determining whether the element width of the input data exceeds a threshold; means for constructing, in response to a determination that the element width exceeds the threshold, a large bit-map output table to store the bit-map output bits; and means for constructing, in response to a determination that the element width does not exceed the threshold, a small bit-map output table to store the bit-map output bits.

Example 36 includes the subject matter of any of Examples 28-35, and wherein the large bit-map output table supports parallel accesses by duplicating the bit-map output table and the small-sized table supports multiple accesses via multiple write ports and duplicating the bit-map output table.

Example 37 includes the subject matter of any of Examples 28-36, and wherein the means for setting the corresponding bit-map output bit comprises means for determining whether the element width exceeds a threshold; means for accessing, in response to a determination that the element width exceeds the threshold, the large bit-map output table to set the corresponding bit-map output bit; and means for accessing, in response to a determination that the element width does not exceed the threshold, the small bit-map output table to set the corresponding bit-map output bit.

Example 38 includes the subject matter of any of Examples 28-37, and wherein the means for outputting the bit-map output table comprises means for generating a population count indicating a number of unique elements based on the bit-map output table.

Example 39 includes the subject matter of any of Examples 28-38, and wherein the each accelerator further comprises means for accumulating the bit-map output table until a width of the bit-map output table matches a data path width.

Claims

1. A computing device for determining unique values, the computing device comprising one or more accelerator devices, each accelerator device is to: receive input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data;generate, in response to receiving the query configuration data, a bit-map output table based on the query configuration data;generate a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element;set the corresponding bit-map output bit to indicate a presence of the corresponding element in response to generation of the write request; andoutput the bit-map output table indicative of unique elements that are present in the input data in response to setting of the corresponding bit-map output bit.

2. The computing device of claim 1, wherein the each accelerator is further to: decompress, in response to importation of the input data, the input data; andpre-process, in response to decompression of the input data, the decompressed input data.

3. The computing device of claim 2, wherein to pre-process the decompressed input data comprises to align elements of the packed bit vector of the input data based on a width of elements of the decompressed input data and prepend zeroes to match a data path width.

4. The computing device of claim 1, wherein the query configuration data further includes a hash width.

5. The computing device of claim 4, wherein the each accelerator is further to: determine whether the element width is greater than the hash width;program, in response to a determination that the element width is greater than the hash width, a hash function to generate a hash value that corresponds to the element value of the corresponding element; andgenerate, in response to programming of the hash function, a hash value for each element value by performing the hash function on the input data.

6. The computing device of claim 4, wherein to generate the write request comprises to generate a write request address based on a hash value of the corresponding element.

7. The computing device of claim 1, wherein to generate the write request comprises to determine a write request address based on an element value of the corresponding element.

8. The computing device of claim 1, wherein to generate the bit-map output table based on the query configuration data comprises to: determine whether the element width of the input data exceeds a threshold;construct, in response to a determination that the element width exceeds the threshold, a large bit-map output table to store the bit-map output bits; andconstruct, in response to a determination that the element width does not exceed the threshold, a small bit-map output table to store the bit-map output bits.

9. The computing device of claim 8, wherein the large bit-map output table supports parallel accesses by duplication of the bit-map output table and the small-sized table supports multiple accesses via multiple write ports and duplication of the bit-map output table.

10. The computing device of claim 8, wherein to set the corresponding bit-map output bit comprises to: determine whether the element width exceeds a threshold;access, in response to a determination that the element width exceeds the threshold, the large bit-map output table to set the corresponding bit-map output bit; andaccess, in response to a determination that the element width does not exceed the threshold, the small bit-map output table to set the corresponding bit-map output bit.

11. The computing device of claim 10, wherein to output the bit-map output table comprises to generate a population count indicating a number of unique elements based on the bit-map output table.

12. The computing device of claim 10, wherein the each accelerator is further to accumulate the bit-map output table until a width of the bit-map output table matches a data path width.

13. One or more machine-readable storage media comprising a plurality of instructions stored thereon that, when executed by a compute device cause an accelerator of the compute device to: receive input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data;generate, in response to receiving the query configuration data, a bit-map output table based on the query configuration data;generate a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element;set the corresponding bit-map output bit to indicate a presence of the corresponding element in response to generation of the write request; andoutput the bit-map output table indicative of unique elements that are present in the input data in response to setting of the corresponding bit-map output bit.

14. The one or more machine-readable storage media of claim 13, further comprising a plurality of instructions stored thereon that, in response to being executed, cause the accelerator of the compute device to: decompress, in response to importation of the input data, the input data; andpre-process, in response to decompression of the input data, the decompressed input data.

15. The one or more machine-readable storage media of claim 14, wherein to pre-process the decompressed input data comprises to align elements of the packed bit vector of the input data based on a width of elements of the decompressed input data and prepend zeroes to match a data path width.

16. The one or more machine-readable storage media of claim 13, further comprising a plurality of instructions stored thereon that, in response to being executed, cause the accelerator of the compute device to: determine whether the element width is greater than a hash width, wherein the hash width is included in the query configuration data;program, in response to a determination that the element width is greater than the hash width, a hash function to generate a hash value that corresponds to the element value of the corresponding element; andgenerate, in response to programming of the hash function, a hash value for each element value by performing the hash function on the input data.

17. The one or more machine-readable storage media of claim 13, wherein to generate the bit-map output table based on the query configuration data comprises to: determine whether the element width of the input data exceeds a threshold;construct, in response to a determination that the element width exceeds the threshold, a large bit-map output table to store the bit-map output bits; andconstruct, in response to a determination that the element width does not exceed the threshold, a small bit-map output table to store the bit-map output bits.

18. The one or more machine-readable storage media of claim 17, wherein the large bit-map output table supports parallel accesses by duplication of the bit-map output table and the small-sized table supports multiple accesses via multiple write ports and duplication of the bit-map output table.

19. The one or more machine-readable storage media of claim 17, wherein to set the corresponding bit-map output bit comprises to: determine whether the element width exceeds a threshold;access, in response to a determination that the element width exceeds the threshold, the large bit-map output table to set the corresponding bit-map output bit; andaccess, in response to a determination that the element width does not exceed the threshold, the small bit-map output table to set the corresponding bit-map output bit.

20. A method for determining unique values by a computing device, the method comprising: receiving, by an accelerator of the computing device, input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data;generating, in response to receiving the query configuration data and by the accelerator, a bit-map output table based on the query configuration data;generating, by the accelerator, a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element;setting, by the accelerator, the corresponding bit-map output bit to indicate a presence of the corresponding element in response to generating the write request; andoutputting, by the accelerator, the bit-map output table indicative of unique elements that are present in the input data in response to setting the corresponding bit-map output bit.

21. The method of claim 20 further comprising: decompressing, in response to importing the input data and by the accelerator, the input data; andpre-processing, in response to decompressing the input data and by the accelerator, the decompressed input data.

22. The method of claim 20 further comprising: determining, by the accelerator, whether the element width is greater than a hash width, wherein the hash width is included in the query configuration data;programming, in response to a determination that the element width is greater than the hash width and by the accelerator, a hash function to generate a hash value that corresponds to the element value of the corresponding element; andgenerating, in response to programming the hash function and by the accelerator, a hash value for each element value by performing the hash function on the input data.

23. The method of claim 13, wherein generating the bit-map output table based on the query configuration data comprises: determining, by the accelerator, whether the element width of the input data exceeds a threshold;constructing, in response to a determination that the element width exceeds the threshold, a large bit-map output table to store the bit-map output bits; andconstructing, in response to a determination that the element width does not exceed the threshold, a small bit-map output table to store the bit-map output bits.

24. The method of claim 23, wherein the large bit-map output table supports parallel accesses by duplicating the bit-map output table and the small-sized table supports multiple accesses via multiple write ports and duplicating the bit-map output table.

25. The method of claim 23, wherein setting the corresponding bit-map output bit comprises: determining, by the accelerator, whether the element width exceeds a threshold;accessing, in response to a determination that the element width exceeds the threshold and by the accelerator, the large bit-map output table to set the corresponding bit-map output bit; andaccessing, in response to a determination that the element width does not exceed the threshold and by the accelerator, the small bit-map output table to set the corresponding bit-map output bit.